CN110970392B - Semiconductor device and method of forming a semiconductor device - Google Patents

Semiconductor device and method of forming a semiconductor device Download PDF

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Publication number
CN110970392B
CN110970392B CN201910922907.6A CN201910922907A CN110970392B CN 110970392 B CN110970392 B CN 110970392B CN 201910922907 A CN201910922907 A CN 201910922907A CN 110970392 B CN110970392 B CN 110970392B
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dielectric layer
conductive
layer
semiconductor device
metal cap
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CN201910922907.6A
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CN110970392A (en
Inventor
何嘉玮
徐俊伟
沈稘翔
刘启人
林易生
郑仰钧
洪伟伦
陈亮光
陈科维
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/525,186 external-priority patent/US11133247B2/en
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Abstract

The semiconductor device includes a first dielectric layer over the substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer away from the substrate to a second side of the first dielectric layer opposite the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line comprising a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap over and physically connected to the conductive line, the metal cap comprising a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via comprising a second conductive material. Embodiments of the present invention also relate to a method of forming a semiconductor device.

Description

Semiconductor device and method of forming a semiconductor device
Technical Field
Embodiments of the invention relate to a semiconductor device and a method of forming a semiconductor device.
Background
The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of various electrical components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the continuous reduction in minimum feature size, which allows more components to be integrated into a given area. As feature sizes continue to shrink in advanced process technologies, new process steps may be used to achieve performance goals for the formed semiconductor devices. New process steps may also present new challenges for semiconductor manufacturing.
Disclosure of Invention
An embodiment of the present invention provides a semiconductor device including: a first dielectric layer over a substrate, the first dielectric layer comprising a first dielectric material extending from a first side of the first dielectric layer away from the substrate to a second side of the first dielectric layer opposite the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line comprising a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap over and physically connected to the conductive line, the metal cap comprising a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via comprising the second conductive material.
Another embodiment of the present invention provides a semiconductor device including: a substrate; a first dielectric layer over the substrate, the first dielectric layer being a single layer; a conductive member in the first dielectric layer, the conductive member comprising a first conductive material, a first surface of the conductive member distal from the substrate being closer to the substrate than a first surface of the first dielectric layer distal from the substrate; a second dielectric layer over the first dielectric layer and the conductive feature; and a conductive plug having an upper portion and a lower portion, the upper portion and the lower portion comprising a second conductive material different from the first conductive material, the upper portion of the conductive plug disposed in the second dielectric layer, the lower portion of the conductive plug extending into the first dielectric layer and being physically connected to the conductive member.
Yet another embodiment of the present invention provides a method of forming a semiconductor device, the method including: forming a first dielectric layer over a substrate; forming a conductive line in the first dielectric layer using a first material, wherein after forming the conductive line, there is a recess in the first dielectric layer proximate an upper surface of the first dielectric layer distal from the substrate, wherein a bottom of the recess exposes the upper surface of the conductive line; filling the recess in the first dielectric layer with a second material different from the first material to form a metal cap, wherein the metal cap is wider than the conductive line; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer to expose the metal cap; and filling the opening with the second material to form a via.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1-7, 8A, 8B, and 9 illustrate cross-sectional views of a semiconductor device at various stages of fabrication, according to an embodiment.
Fig. 10-12 illustrate cross-sectional views of a semiconductor device at various stages of fabrication, according to an embodiment.
Fig. 13-19, 20A, 20B, and 21 illustrate cross-sectional views of a semiconductor device at various stages of fabrication, according to an embodiment.
Fig. 22 illustrates a flow diagram of a method for forming a semiconductor device in some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Embodiments of the present invention are discussed in the context of semiconductor device fabrication, and in particular, in the context of forming vias of semiconductor devices.
In some embodiments, a semiconductor device includes a metal line formed in a first dielectric layer. The metal line is formed of a first conductive material, and an upper surface of the metal line is recessed from an upper surface of the first dielectric layer. The semiconductor device further includes a metal cap located over and connected to the metal line. The metal cap is formed of a second conductive material different from the first conductive material. The metal cap is wider than the metal line and an upper surface of the metal cap is flush with an upper surface of the first dielectric layer. The semiconductor device also includes a second dielectric layer over the first dielectric layer, and a via in the second dielectric layer. A via is located over and connected to the metal cap. The via is formed of a second conductive material.
Fig. 1-7, 8A, 8B, and 9 illustrate cross-sectional views of a semiconductor device 100 at various stages of fabrication in an embodiment. The semiconductor device 100 may be a device wafer including active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, inductors, resistors, etc.). In some embodiments, semiconductor device 100 is an interposer wafer, which may or may not include active and/or passive devices. According to yet another embodiment of the present invention, the semiconductor device 100 is a package substrate tape, which may be a package substrate having a core therein, or may be a coreless package substrate. In the discussion that follows, a device wafer is used as an exemplary semiconductor device 100. The teachings of the present invention may also be applied to interposer wafers, package substrates, or other semiconductor structures.
As shown in fig. 1, the semiconductor device 100 includes a semiconductor substrate 20 and an integrated circuit device 22 (e.g., active device, passive device, conductive pad) formed on or in the semiconductor substrate 20. The semiconductor substrate 20 may include a semiconductor material, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 20 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.
In the example of fig. 1, the integrated circuit device 22 is formed on the semiconductor substrate 20 or in the semiconductor substrate 20. Exemplary integrated circuit devices 22 include transistors (e.g., Complementary Metal Oxide Semiconductor (CMOS) transistors), resistors, capacitors, diodes, and the like. Integrated circuit device 22 may be formed using any suitable method and details are not discussed herein.
After forming the integrated circuit device 22, an interlayer dielectric (ILD)24 is formed over the semiconductor substrate 20 and over the integrated circuit device 22. ILD24 may fill the spaces between the gate stacks of transistors (not separately shown) in integrated circuit device 22. According to some embodiments, ILD24 comprises phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), Tetraethylorthosilicate (TEOS), and the like. The ILD24 may be formed using spin coating, Flowable Chemical Vapor Deposition (FCVD), and the like. In some embodiments, ILD24 is formed using a suitable deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and the like.
Referring to fig. 1, contact plugs 28 are formed in ILD24 and electrically couple integrated circuit device 22 to overlying conductive features, such as metal lines, vias, and conductive pillars. According to some embodiments of the present invention, the contact plug 28 is formed of a conductive material such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multilayers thereof. The formation of contact plug 28 may include forming a contact opening in ILD24, filling the contact opening with a conductive material, and performing a planarization process, such as Chemical Mechanical Polishing (CMP), to make the top surface of contact plug 28 flush with the top surface of ILD 24.
Next, in fig. 2, an inter-metal dielectric (IMD) layer 30 is formed over the ILD24, and an opening 32 is formed in the IMD layer 30 to expose the contact plug 28. IMD layer 30 may be formed of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. According to some embodiments, IMD layer 30 is formed of a low-k dielectric material having a dielectric constant (k value) below 3.0, such as about 2.5, about 2.0, or even lower. IMD layer 30 may include black diamond (a registered trademark of applied materials), carbon-containing low-k dielectric materials, Hydrogen Silsesquioxane (HSQ), Methyl Silsesquioxane (MSQ), and the like. Formation of IMD layer 30 may include depositing a porogen-containing dielectric material over ILD24 and then performing a curing process to drive off the porogen to form porous IMD layer 30, as an example. Other suitable methods may also be used to form IMD layer 30.
The openings 32 are formed using suitable methods such as photolithography and etching techniques. In the example shown in fig. 2, opening 32 has an upper portion with a width W1 and a lower portion with a width W2, wherein W1 is greater than W2. In the example shown, opening 32 has straight sidewalls (e.g., perpendicular to the upper surface of ILD 24). In other embodiments, the openings may have sloped sidewalls (see, e.g., opening 33 in fig. 14), or have other shapes due to the process used to form the openings. The opening 32 may be formed by using, for example, two separate photolithography and etching processes. For example, a first photolithography and etching process using a first mask layer may be performed to form a first opening having a width W2, wherein the first opening extends through IMD layer 30 and exposes contact plug 28. Next, a second photolithography and etching process using a second mask layer may be performed after removing the first mask layer to form an upper portion of the opening 32 having a width W1. Other methods for forming the opening 32 are also possible and are fully intended to be included within the scope of the present invention.
Next, as shown in fig. 3, a conductive material 36 is formed to fill the opening 32 (see the mark in fig. 2). Conductive material 36 may be any suitable conductive material for forming, for example, a wire. In an embodiment, the conductive material 36 is cobalt (Co). Other examples of materials for conductive material 36 include W, Cu and Ru. As shown in fig. 3, a lower portion 36L of conductive material 36 fills a lower portion of opening 32 and an upper portion 36U of conductive material 36 fills an upper portion of opening 32. Conductive material 36 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), plating (e.g., electroplating or electroless plating), or other suitable methods. In some embodiments, conductive material 36 overfills opening 32 and covers the upper surface of IMD layer 30, and thus, a planarization process such as CMP is performed to remove excess portions of conductive material 36 from over the upper surface of IMD layer 30.
In some embodiments, a barrier layer 31 (also referred to as a diffusion barrier layer) is formed in the opening 32 prior to forming the conductive material 36, the barrier layer 31 lining the sidewalls and bottom of the opening 32. The barrier layer 31 may include titanium, titanium nitride, tantalum nitride, or the like, and may be formed by CVD, PVD, Atomic Layer Deposition (ALD), or the like. In other embodiments, barrier layer 31 is omitted. For simplicity, subsequent figures in this disclosure may not show barrier layer 31 between IMD layer 30 and conductive material 36, it being understood that barrier layer 31 may be formed between IMD layer 30 and conductive material 36.
Referring next to fig. 4, a thinning process is performed to reduce the thickness of IMD layer 30 and to reduce the thickness of upper portion 36U of conductive material 36. A planarization process such as CMP may be used as the thinning process. The thinning process stops before reaching the lower portion 36L of the conductive material 36, as shown in fig. 4. In the illustrated embodiment, after the thinning process, the thickness T1 of the remaining portion of upper portion 36U is between about 5nm and about 10nm, the thickness of IMD layer 30 is between about 0nm and about 30nm, and the distance W3 between the sidewalls of the remaining portion of upper portion 36U and the corresponding sidewalls of lower portion 36L is between about 2nm and about 3 nm. The dimensions discussed above are non-limiting examples. Other dimensions are possible and are fully intended to be included within the scope of the present invention. For example, the values for dimensions W3 and T1 may change (e.g., scale) among different process nodes.
Next, in fig. 5, the remaining portion of the upper portion 36U is removed (see fig. 4). In some embodiments, an etching process, such as a wet etching process, is performed to remove the remaining portion of the upper portion 36U. The wet etch process may use an etchant (e.g., HF, HCl, H) that is selective to (e.g., has a higher etch rate) the conductive material 362O2Or KOH) to remove conductive material 36 without substantially attacking IMD layer 30. After the etching process, the remaining portion of conductive material 36 in the lower portion of opening 32 forms conductive line 34. The upper surface 34T of the wire 34 may be flush with the bottom 32B of the upper portion of the opening 32. If formed, barrier layer 31 (see FIG. 3) along the sidewalls of upper portion 36U is also removed by the wet etch process.
In some embodiments, instead of performing a separate wet etch process, the remaining portion of the upper portion 36U (see fig. 4) is removed by a CMP process. For example, the slurry used in the CMP process may be adjusted (e.g., selected) to be selective to conductive material 36, such that conductive material 36 is removed at a faster rate than IMD layer 30. After the CMP process, the remaining portions of conductive material 36 form conductive lines 34. As shown in fig. 5, an upper surface 34T' (shown in dotted lines) of the conductive line 34 formed by the CMP process may be concave due to a dishing effect of the CMP process. For simplicity, subsequent figures in the present disclosure may not show the concave upper surface 34T 'of wire 34, it being understood that the upper surface of wire 34 may be flat (see, e.g., 34T) or concave (see, e.g., 34T'), depending on the process used to remove conductive material 36.
Referring next to fig. 6, a cap 38 (which may also be referred to as a metal cap) is formed over lead 34 and fills a recess in IMD layer 30 formed by removing conductive material 36 (see fig. 5). In the illustrated embodiment, the cap 38 and the wire 34 are formed of different materials. For example, the cap 38 is formed from a conductive material (e.g., a conductive material) that is different from the conductive material 36 of the wire 34. In the exemplary embodiment, wire 34 is formed from cobalt and cap 38 is formed from tungsten (W). Other examples of materials for the cap 38 include Co and Ru. In the illustrated embodiment, cap 38 is in direct contact (e.g., physical contact) with IMD layer 30.
The cap 38 may be formed using, for example, CVD, PVD, plating, or other suitable method. The material of cap 38 may overfill the recess in IMD layer 30, in which case a planarization process, such as CMP, may be performed to remove excess portions of the material of cap 38. In other embodiments, the material of the cap 38 is formed in and fills the recess without overfilling, and thus the planarization process is omitted.
In some embodiments, after formation, the thickness T of the cap 382Between about 5nm and about 10nm, and the distance W between the sidewalls of cap 38 and the corresponding sidewalls of wire 344Between about 2nm and about 3nm, although other dimensions are possible. In other words, the width (along W) of the cap 384Measured in the direction of (a) is greater than the width of the conductive line 34. In some embodiments, the thickness T of the cap 382And lead 34 is equal in thickness to IMD layer 30, which is between 5nm and about 30nm thick. As discussed in more detail below, because cap 38 is wider than wire 34, and because cap 38 is formed of a different material than wire 34, cap 38 can protect wire 34 from being etched by the slurry used in the subsequent CMP process for forming via 46 (see fig. 8A), thereby reducing or preventing the formation of cavities over wire 34 that may result in poor electrical connections or device failure。
Next, in fig. 7, an etch stop layer 42 and an IMD layer 44 are formed over IMD layer 30 and cap 38. Etch stop layer 42 is formed of a material having a high etch selectivity with respect to an overlying dielectric layer (e.g., 44) and may be used to control (e.g., stop) the etching process of the overlying dielectric layer. The etch stop layer 42 may be formed of silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., and may be formed using a suitable deposition process, such as PVD, CVD, combinations thereof, and the like. IMD layer 44 may be formed of the same or similar dielectric material (e.g., a low-k dielectric material) as IMD layer 30 and may be formed using the same or similar method as IMD layer 30, and therefore, details are not repeated.
Next, via openings 43 are formed in the IMD layer 44 using suitable methods such as photolithography and etching. Via opening 43 extends through IMD layer 44 and etch stop layer 42 and exposes cap 38. In the example of fig. 7, the width of the via opening 43 is less than the width of the cap 38, and thus, a portion of the upper surface of the cap 38 is exposed.
Next, in fig. 8A, a via 46 is formed in the via opening 43 (see fig. 7) using the conductive material (e.g., tungsten) of the cap 38. In other words, the via 46 and the cap 38 are formed of the same conductive material. The through-hole 46 is formed directly on (e.g., in direct contact with) the cap 38. There may or may not be an interface 37 between the via 46 and the cap 38, depending on the conductive material and process used to form the via 46. Vias 46 and caps 38 may be collectively referred to as vias 48, and vias 48 may also be referred to as plugs or conductive plugs. Through-hole 46 may be referred to as an upper portion of conductive plug 48, and cap 38 may be referred to as a lower portion of conductive plug 48.
The via 46 may be formed in the via opening 43 using a suitable formation method, such as CVD, PVD, plating, ALD, the like or combinations thereof. A planarization process such as CMP may be performed to remove excess portions of the material of vias 46 from over the upper surface of IMD layer 44.
In the illustrated embodiment, a via 46 is formed in the via opening 43 and is in direct contact with the IMD layer 44, the etch stop layer 42, and the cap 38. In other words, no barrier layer is formed between via 46 and IMD layer 44/etch stop layer 42/cap 38. In an improved process node, as device dimensions continue to shrink, the thickness of the barrier layer is no longer negligible compared to the dimensions of the features to be formed (e.g., via 46). Thus, in the illustrated embodiment, by not having a barrier layer, the vias 46 have a larger volume and therefore have a smaller resistance, thereby reducing the resistance-capacitance delay (RC delay) of the formed device. Therefore, it may be advantageous to form the via 46 without a barrier layer to reduce RC delay.
However, without a barrier layer (which may also serve as a glue layer between via 46 and IMD layer 44), adhesion between via 46 and IMD layer 44 may be reduced, and thus, there may be a slight crack between via 46 and IMD layer 44. During the CMP process to remove the excess portion of the material of via 46, the slurry used in the CMP process may penetrate through the micro cracks between via 46 and IMD layer 44 and reach lead 34. If wire 34 is etched by the paste (also referred to as corrosion or metal corrosion), cavities (e.g., grooves) may form at the upper surface of wire 34, which may result in unreliable electrical connections between via 46 and the underlying wire 34, and may even result in device failure.
The present invention prevents or reduces corrosion of the wires 34 by forming the cap 38 such that the cap 38 is wider than the underlying wire 34 and serves as a shield for the wire 34. Thus, cap 38 protects (e.g., shields) lead 34 from slurry that penetrates down through the micro-cracks between via 46 and IMD layer 44.
Furthermore, since vias 46 are formed using a different conductive material (e.g., tungsten) than the conductive material (e.g., cobalt) of wires 34, the slurry used in the CMP process (e.g., to remove excess portions of the material of vias 46) may be selected to be selective (e.g., have a higher etch rate) to the material of vias 46. Thus, the paste used to remove the material of via 46 does not substantially attack wire 34. In other words, during the CMP process for forming via 46, the etch selectivity between the two different conductive materials of via 46 and wire 34 may be utilized to reduce or prevent corrosion of wire 34. This may be accomplished by selecting an acidic paste (e.g., PH less than 7) or an alkaline paste (e.g., PH greater than 7) that reacts with the material of the via 46 but does not react readily with the material of the wire 34. For example, cobalt reacts readily with acidic slurries, but not readily with alkaline slurries; tungsten reacts readily with alkaline slurries but not acidic slurries.
In an exemplary embodiment, conductive line 34 is formed of cobalt, via 46/cap 38 is formed of tungsten, and the CMP process used to remove the excess portion of the material of via 46 uses an alkaline slurry that is reactive with tungsten but not reactive with cobalt, thus reducing or preventing corrosion of conductive line 34 during the CMP process. The alkaline slurry may be a slurry containing iron (Fe) ions or cobalt (Co) iron, from sources such as Fe (NO)3)3、Fe(CN)6 3-、Co(NO3)3、Co(CN)6 3-And the like. In some embodiments, the slurry reacts with the cap 38 and forms a byproduct of the material of the cap 38, such as oxide 38A (see fig. 8B), at the interface between the cap 38 and the etch stop layer 42. For simplicity, subsequent figures in the present disclosure may not show oxide 38A, but it is understood that oxide 38A may be formed at the interface between cap 38 and etch stop layer 42.
Fig. 8B shows an enlarged view of the through hole 48 in fig. 8A. In some embodiments, when forming the via 46 over the cap 38, two different forming methods are used to form the via 46. Specifically, an ALD deposition process is performed to form a first sub-layer 46A (e.g., a conformal layer) of the via 46, and a different deposition process, such as CVD, PVD, or plating, is used to fill the remainder of the via opening 43 (see fig. 7) and form a second sub-layer 46B of the via 46. In other words, although the first sub-layer 46A and the second sub-layer 46B are formed of the same material (e.g., tungsten), different deposition methods are used. An interface 47 may be present between the first sub-layer 46A and the second sub-layer 46B. The first sub-layer 46A may have a thickness between about 0nm and about 3 nm. Since the first sub-layer 46A is formed by ALD, its density is higher than that of the second sub-layer 46B. In some embodiments, having the first sub-layer 46A of higher quality (e.g., higher density) reduces the resistance of the formed vias 46. Forming the second sub-layer 46B by PVD, CVD or plating may advantageously reduce manufacturing time, as the deposition rate of the ALD deposition process may be lower than the deposition rate of PVD, CVD or plating, for example. Thus, the two-sublayer structure of via 46 allows a balance to be achieved between reducing the resistance (e.g., RC delay) of via 46 and reducing the manufacturing time.
In some embodiments, the overall density (e.g., average density) of the vias 46 is higher than the overall density of the caps 38 because the vias 46 have a first sub-layer 46A (e.g., a higher density material) formed by ALD, and the caps 38 are formed by CVD, PVD, or plating (e.g., a lower density material). In other embodiments, the vias 46 do not have multiple sublayers, and instead, the vias 46 are formed using a single deposition process such as CVD, PVD, plating, and the like, in which case the vias 46 and caps 38 may have the same density.
Next, in fig. 9, one or more IMD layers 53 including conductive features (e.g., conductive lines and vias) are formed over IMD layer 44 using the same or similar methods as described above for forming IMD layers (e.g., 30 or 44) and conductive features (e.g., 34, 38, 46). Next, a passivation layer 56 such as a polymer layer is formed over the IMD layer 53. After forming passivation layer 56, an Under Bump Metal (UBM) structure 62 is formed over passivation layer 56 and electrically coupled to conductive features 54 (e.g., conductive lines) of IMD layer 53.
In an embodiment, the UBM structure 62 includes three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. However, there are many suitable materials and arrangements of layers suitable for forming UBM structure 62, such as a chromium/chromium copper alloy/copper/gold arrangement, a titanium/titanium tungsten/copper arrangement, or a copper/nickel/gold arrangement. Any suitable material or layers of materials that may be used for UBM structure 62 are fully intended to be included within the scope of the present invention.
The UBM structure 62 may be formed by: forming an opening in passivation layer 56 to expose conductive feature 54 in IMD layer 53; forming a seed layer over the passivation layer 56 and along the inside of the opening in the passivation layer; forming a patterned masking layer (e.g., photoresist) over the seed layer; forming (e.g., by plating) a conductive material in the openings of the patterned mask layer and over the seed layer; the mask layer is removed and the portions of the seed layer on which the conductive material is not formed are removed. Other methods for forming UBM structure 62 are possible and are fully intended to be included within the scope of the present invention.
Still referring to fig. 9, next, an external connection 64 is formed on the UBM structure 62. In an embodiment, the external connections 64 are contact bumps, such as controlled collapse chip connection (C4) bumps, and comprise a material such as tin or other suitable material such as silver or copper. In embodiments where the external connections 64 are solder bumps, the external connections 64 may be formed by initially forming a layer of tin by any suitable method, such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once the tin layer is formed on the structure, reflow is performed to shape the material into a bump shape having a diameter of, for example, about 80 μm.
However, while the external connections 64 have been described above as C4 bumps, these are merely intended to be illustrative and not limiting embodiments. Rather, any suitable type of external contact may alternatively be utilized, such as Ball Grid Arrays (BGA), micro-bumps, copper posts, copper layers, nickel layers, lead-free (LF) layers, Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layers, Cu/LF layers, Sn/Ag layers, Sn/Pb, combinations of these, and the like. Any suitable external connection and any suitable process for forming an external connection may be used for external connection 64, and all such external connections are fully intended to be included within the scope of the embodiments.
Fig. 10-12 illustrate cross-sectional views of a semiconductor device 200 at various stages of fabrication in an embodiment. Unless otherwise noted, the same reference numerals in fig. 10 to 12 refer to the same or similar elements as in fig. 1 to 9 formed by the same or similar forming method, and thus the details may not be repeated. The process in fig. 10 follows the process shown in fig. 6, and thus fig. 1-6 and 10-12 illustrate another embodiment of the present invention.
Referring to fig. 10, an etch stop layer 42 and an IMD layer 44 are formed over IMD layer 30 and cap 38 after the process steps shown in fig. 6. Next, via openings 45 are formed in the IMD layer 44 using suitable methods such as photolithography and etching.Via opening 45 extends through IMD layer 44 and etch stop layer 42 and exposes cap 38. In the example of fig. 10, the width W of the via opening 459Is greater than the width of cap 38 and, therefore, exposes the upper surface of cap 38 and a portion of the upper surface of IMD layer 30. In some embodiments, the width W9Between about 15nm and about 40 nm.
Next, in fig. 11, a via 46 is formed in the via opening 45 (see fig. 10) using the conductive material (e.g., tungsten) of the cap 38. In other words, the via 46 and the cap 38 are formed of the same conductive material. The through-hole 46 is formed directly on (e.g., in direct contact with) the cap 38. There may or may not be an interface 37 between the via 46 and the cap 38, depending on the conductive material and process used to form the via 46. Vias 46 and caps 38 may be collectively referred to as vias 48, and vias 48 may also be referred to as plugs or conductive plugs. Through-hole 46 may be referred to as an upper portion of conductive plug 48, and cap 38 may be referred to as a lower portion of conductive plug 48.
The via 46 may be formed in the via opening 43 using a suitable formation method, such as CVD, PVD, plating, ALD, the like or combinations thereof. A planarization process such as CMP may be performed to remove excess portions of the material of vias 46 from over the upper surface of IMD layer 44.
In the illustrated embodiment, via 46 is formed in via opening 45 and is in direct contact with IMD layer 44, etch stop layer 42, IMD layer 30, and cap 38. In other words, no barrier layer is formed between via 46 and IMD layer 44/IMD layer 30/etch stop layer 42, which may advantageously reduce the RC delay of the formed semiconductor device 200. In some embodiments, when forming the via 46 over the cap 38, two different forming methods are used to form the via 46. Specifically, an ALD deposition process is performed to form a first sub-layer 46A of the via 46, and a different deposition process, such as CVD, PVD or plating, is used to fill the remainder of the via opening 45 (see fig. 10) and form a second sub-layer 46B of the via 46. In other words, the first and second sub-layers 46A and 46B are formed of the same material (e.g., tungsten), but using different deposition methods. An interface 47 may be present between the first sub-layer 46A and the second sub-layer 46B. The first sub-layer 46A may be between about 0nm and about 3nm thick. Since the first sub-layer 46A is formed by ALD, its density is higher than that of the second sub-layer 46B. In some embodiments, having the first sub-layer 46A of higher quality (e.g., higher density) reduces the resistance of the formed vias 46. Since the deposition rate of the ALD deposition process may be lower than the deposition rate of PVD, CVD, or plating, for example, forming the second sub-layer 46B by PVD, CVD, or plating may advantageously reduce the fabrication time, allowing a balance to be achieved between reducing the resistance (e.g., RC delay) of the via 46 and reducing the fabrication time.
In some embodiments, the overall density (e.g., average density) of the vias 46 is higher than the overall density of the caps 38 because the vias 46 have a first sub-layer 46A (e.g., a higher density material) formed by ALD, and the caps 38 are formed by CVD, PVD, or plating (e.g., a lower density material). In other embodiments, the vias 46 do not have multiple sublayers, and instead, the vias 46 are formed using a single deposition process such as CVD, PVD, plating, and the like, in which case the vias 46 and caps 38 may have the same density.
Next, in fig. 12, one or more IMD layers 53 including conductive features (e.g., conductive lines and vias) are formed over IMD layer 44 using the same or similar methods as described above for forming IMD layers (e.g., 30 or 44) and conductive features (e.g., 34, 38, 46). Next, a passivation layer 56 such as a polymer layer is formed over the IMD layer 53. After forming passivation layer 56, an Under Bump Metal (UBM) structure 62 is formed over passivation layer 56 and electrically coupled to conductive features 54 (e.g., conductive lines) of IMD layer 53. Next, an external connection 64 is formed on the UBM structure 62. The formation of UBM structure 62 and external connections 64 may be the same as or similar to those described above with reference to fig. 9, and therefore, details are not repeated.
Fig. 13-21 illustrate cross-sectional views of a semiconductor device 300 at various stages of fabrication in an embodiment. Unless otherwise noted, the same reference numerals in fig. 13 to 21 refer to the same or similar elements formed by the same or similar forming method as in fig. 1 to 9, and thus, the details may not be repeated. The process in fig. 13 follows the process shown in fig. 1, and thus fig. 1 and 13-21 illustrate another embodiment of the present invention.
Referring to fig. 13, an IMD layer 30 is formed over the ILD24 and over the contact plug 28. An opening 33 is formed in IMD layer 30 using a suitable method, such as photolithography and etching, to expose underlying contact plug 28. The etch may be anisotropic such that the sidewalls of the openings 33 are perpendicular to the upper surface of the ILD 24.
Next, in fig. 14, the profile (e.g., the shape of the sidewall) of the opening 33 is changed by an etching process such as a dry etching process. In some embodiments, the width of the upper portion of the opening 33 is expanded by another photolithography and etching process, and then a mask layer, such as photoresist, is formed at the bottom of the opening 33. A dry etching process is then performed to change the profile of the upper portion of the opening 33. In some embodiments, a plasma process is used to modify the profile of the upper portion of opening 33. The plasma process may use a gas source comprising argon. A gas source containing argon is activated into a plasma and the argon plasma bombards IMD layer 30 and changes the profile of opening 33. In some embodiments, the plasma process is performed at a temperature between about 25 ℃ and about 80 ℃ and at a pressure between about 0.002 torr and about 0.05 torr using an RF power between about 200 watts and about 600 watts. The flow rate of argon is between about 2 standard cubic centimeters per minute (sccm) and about 20 sccm. In some embodiments, the RF power of the plasma process is adjusted to change the lateral etch rate of the plasma process such that the lateral etch rate decreases in a direction from the upper surface of IMD layer 30 toward the lower surface of the IMD, thereby forming a sloped sidewall of the upper portion of opening 33. After the plasma process is completed, the mask layer is removed from the bottom of the opening 33 so that the bottom of the opening 33 still has vertical sidewalls.
After the etching process is completed, the upper portion of opening 33 has sloped sidewalls 30A and the lower portion of opening 33 has straight (e.g., perpendicular to the upper surface of ILD 24) sidewalls 30C. As shown in fig. 14, the distance between opposing sidewalls 30A decreases as opening 33 extends into IMD layer 30. In addition, sidewalls 30B, which are parallel to the upper surface of ILD24, provide a transition between sloped sidewalls 30A and straight sidewalls 30C. Thus, of openings 33The shape of the side wall includes a stepped shape (also referred to as a stepped shape). In fig. 14, the distance W between the inclined side walls 30A measured at the bottom of the inclined side walls 30A5Is greater than the distance W between the straight side walls 30C6. The distance W5 may be between about 20nm and about 40nm, and the distance W6And may be between about 15nm and about 35 nm.
Next, in fig. 15, a conductive material 36 such as cobalt is formed in the opening 33. As shown in fig. 15, a lower portion 36L of conductive material 36 fills a lower portion of opening 33, and an upper portion 36U of conductive material 36 fills an upper portion of opening 33. In some embodiments, conductive material 36 overfills opening 33 and covers the upper surface of IMD layer 30. A planarization process, such as CMP, is then performed to remove excess portions of conductive material 36 from over the upper surface of IMD layer 30.
In some embodiments, a barrier layer is formed in opening 33 lining the sidewalls and bottom of opening 33 prior to forming conductive material 36. An example of a barrier layer is shown in fig. 3. For simplicity, the barrier layer is not shown here. In other embodiments, the barrier layer is omitted.
Next, in fig. 16, a thinning process is performed to reduce the thickness of IMD layer 30 and to reduce the thickness of upper portion 36U of conductive material 36. A planarization process such as CMP may be used as the thinning process. The thinning process stops before reaching the lower portion 36L of the conductive material 36, as shown in fig. 16. Thickness T of the remaining portion of upper portion 36U after the thinning process3Between about 5nm and about 10nm, and in the illustrated embodiment, the distance W between the sidewalls of the remaining portion of the upper portion 36U and the corresponding sidewalls of the lower portion 36L7Between about 2nm and about 3 nm. IMD layer 30 may have a thickness between about 0nm and about 30 nm. The dimensions discussed above are non-limiting examples. Other dimensions are possible and are fully intended to be included within the scope of the present invention.
Next, in fig. 17, the remaining portion of the upper portion 36U is removed (see fig. 16). In some embodiments, an etching process, such as a wet etching process, is performed to remove the remaining portion of the upper portion 36U. The wet etch process may be selective to the conductive material 36 (e.g., withHigher etch rate) of an etchant (e.g., HF, HCl, H2O2Or KOH) such that conductive material 36 is removed without substantially attacking IMD layer 30. After the etching process, the remaining portion of conductive material 36 in the lower portion of opening 33 forms wire 34. The upper surface 34T of the wire 34 may be flush with the sidewall 30B.
In some embodiments, instead of performing a separate wet etch process, the remaining portion of the upper portion 36U is removed by a CMP process (see fig. 16). For example, the slurry used in the CMP process may be selective to conductive material 36, such that conductive material 36 is removed at a faster rate than IMD layer 30. After the CMP process, the remaining portions of conductive material 36 form conductive lines 34. As shown in fig. 17, an upper surface 34T' (shown in dotted lines) of the conductive line 34 formed by the CMP process may be concave due to a dishing effect of the CMP process. For simplicity, subsequent figures in the present disclosure may not show the concave upper surface 34T 'of wire 34, it being understood that the upper surface of wire 34 may be flat (see, e.g., 34T) or concave (see, e.g., 34T'), depending on the process used to remove conductive material 36.
Referring next to fig. 18, a cap 38 is formed over lead 34 and fills a recess in IMD layer 30 formed by removing conductive material 36 (see fig. 17). In the illustrated embodiment, the cap 38 and the wire 34 are formed of different materials. For example, the cap 38 is formed from a conductive material (e.g., a conductive material) that is different from the conductive material 36 of the wire 34. In the exemplary embodiment, wire 34 is formed from cobalt and cap 38 is formed from tungsten (W). Other examples of materials for the cap 38 include Ru, Al, and Cu. In the example of fig. 18, cap 38 also has sloped sidewalls due to the sloped sidewalls of the recess.
The cap 38 may be formed using, for example, CVD, PVD, plating, or other suitable method. The material of cap 38 may overfill the recess in IMD layer 30, in which case a planarization process such as CMP may be performed to remove excess portions of the material of cap 38. In other embodiments, the material of the cap 38 is formed in the recess and fills the recess without overfilling, and thus the planarization process is omitted.
In some embodiments, after formation, though the thickness T of the cap 384Between about 5nm and about 10nm, and the distance W between the sidewalls of the cap 38 and the corresponding sidewalls of the wires 348Between about 2nm and about 3nm, but other dimensions are possible. As shown in FIG. 18, the width (along W) of the cap 388Measured in direction) is greater than the width of the conductive line 34. In some embodiments, the width W8Between about 1nm and about 5 nm.
Next, in fig. 19, an etch stop layer 42 and an IMD layer 44 are formed over IMD layer 30 and cap 38. Next, a via opening 43 is formed in the IMD layer 40 using a suitable method such as photolithography and etching. A via opening 43 extends through IMD layer 40 and etch stop layer 42 and exposes cap 38. In the example of fig. 19, the width of the via opening 43 is smaller than the width of the cap 38, and thus, a part of the upper surface of the cap 38 is exposed. In other embodiments, the width of the via opening 43 is greater than the width of the cap 38, similar to the opening 45 in FIG. 10.
Next, in fig. 20A, a via 46 is formed in the via opening 43 (see fig. 19) using the conductive material (e.g., tungsten) of the cap 38. In other words, the via 46 and the cap 38 are formed of the same conductive material. The through-hole 46 is formed directly on (e.g., in direct contact with) the cap 38. There may or may not be an interface 37 between the via 46 and the cap 38, depending on the conductive material and process used to form the via 46. The through-hole 46 and the cap 38 may be collectively referred to as a through-hole 48.
The via 46 may be formed in the via opening 43 using a suitable formation method, such as CVD, PVD, plating, ALD, the like or combinations thereof. A planarization process such as CMP may be performed to remove excess portions of the material of vias 46 from over the upper surface of IMD layer 44. In the illustrated embodiment, a via 46 is formed in the via opening 43 and is in direct contact with the IMD layer 44 and the etch stop layer 42. In other words, no barrier layer is formed between the via 46 and the IMD layer 44/etch stop layer 42, which may advantageously reduce the RC delay of the semiconductor device 300.
Fig. 20B shows an enlarged view of the through hole 48 in fig. 20A. In some embodiments, when forming the via 46 over the cap 38, two different forming methods are used to form the via 46. Specifically, an ALD deposition process is performed to form a first sub-layer 46A of the via 46, and a different deposition process, such as CVD, PVD or plating, is used to fill the remainder of the via opening 43 (see fig. 19) and form a second sub-layer 46B of the via 46. In other words, the first and second sub-layers 46A, 46B are formed of the same material (e.g., tungsten), but using different deposition methods. An interface 47 may be present between the first sub-layer 46A and the second sub-layer 46B. Since the first sub-layer 46A is formed by ALD, its density is higher than that of the second sub-layer 46B. In some embodiments, having the first sub-layer 46A of higher quality (e.g., higher density) reduces the resistance of the formed vias 46. Since the deposition rate of the ALD deposition process may be lower than the deposition rate of PVD, CVD, or plating, for example, forming the second sub-layer 46B by PVD, CVD, or plating may advantageously reduce the fabrication time, allowing a balance to be achieved between reducing the resistance (e.g., RC delay) of the via 46 and reducing the fabrication time.
Still referring to fig. 20B, in some embodiments, the overall density (e.g., average density) of the vias 46 is higher than the overall density of the caps 38 because the vias 46 have a first sub-layer 46A (e.g., a higher density material) formed by ALD and the caps 38 are formed by CVD, PVD, or plating (e.g., a lower density material). In other embodiments, the vias 46 do not have multiple sublayers, and instead, the vias 46 are formed using a single deposition process such as CVD, PVD, plating, and the like, in which case the vias 46 and caps 38 may have the same density.
Next, in fig. 21, one or more IMD layers 53 including conductive features (e.g., conductive lines and vias) are formed over IMD layer 44 using the same or similar methods as described above for forming IMD (e.g., 30 or 44) layers and conductive features (e.g., 34, 38, 46). Next, a passivation layer 56 such as a polymer layer is formed on the IMD layer 53. After forming passivation layer 56, an Under Bump Metal (UBM) structure 62 is formed over passivation layer 56 and electrically coupled to conductive features 54 (e.g., conductive lines) of IMD layer 53. Next, an external connection 64 is formed on the UBM structure 62. The formation of UBM structure 62 and external connections 64 may be the same as or similar to those described above with reference to fig. 9, and therefore, details are not repeated.
Variations of the disclosed embodiments are possible and are fully intended to be included in the invention. For example, although cap 38 is shown formed under via 46 and in IMD layers (e.g., 44, 53), cap 38 may also be formed under contact plug 28 and in ILD 24. Since contact plug 28 is connected to an underlying conductive component (e.g., a gate of a transistor or a source/drain region of a transistor), the principles of the present invention may also be applied to forming a cap 38 between contact plug 28 and a conductive component of integrated circuit device 22. In other words, by forming the cap 38 using a material different from that of the conductive features of the integrated circuit device 22, corrosion of the conductive features of the integrated circuit device 22 may be prevented or reduced. As another example, the profile of the cap 38, such as the shape of the sidewall of the cap 38, may be modified to have other shapes and the benefits of the cap 38 still remain, for example, when the cap 38 is wider than the underlying wire (e.g., 34). These and other modifications are fully intended to be included within the scope of this invention.
Embodiments may achieve a number of advantages. The caps 38 shield the wires 34 from the slurry used in the subsequent CMP process, thus preventing or reducing corrosion of the wires 34, which improves the performance of the formed devices and improves yield. By using two different materials for cap 38 and wire 34, the etch selectivity between the two different materials may be utilized to reduce or prevent corrosion of wire 34. The present invention allows the via 46 to be formed without a barrier layer, advantageously reducing the RC delay of the resulting device.
Fig. 22 illustrates a flow diagram of a method for forming a semiconductor device according to some embodiments. It should be understood that the embodiment method shown in FIG. 22 is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as shown in FIG. 22 may be added, removed, replaced, rearranged and repeated.
Referring to fig. 22, in block 1010, a first dielectric layer is formed over a substrate. In block 1020, a conductive line is formed in a first dielectric layer using a first material, wherein after forming the conductive line, there is a recess in the first dielectric layer proximate an upper surface of the first dielectric layer away from the substrate, wherein a bottom of the recess exposes the upper surface of the conductive line. In block 1030, the recess in the first dielectric layer is filled with a second material different from the first material to form a metal cap, wherein the metal cap is wider than the conductive line. In block 1040, a second dielectric layer is formed over the first dielectric layer. In block 1050, an opening is formed in the second dielectric layer to expose the metal cap. In block 1060, the opening is filled with a second material to form a via.
In an embodiment, a semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer away from the substrate to a second side of the first dielectric layer opposite the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line comprising a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap over and physically connected to the conductive line, the metal cap comprising a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via comprising a second conductive material. In an embodiment, an upper surface of the metal cap is flush with an upper surface of the first dielectric layer. In an embodiment, the metal cap is wider than the wire. In an embodiment, the metal cap has a sidewall perpendicular to the upper surface of the wire. In an embodiment, the metal cap has a sidewall that is inclined with respect to an upper surface of the wire. In an embodiment, the first conductive material is cobalt and the second conductive material is tungsten. In an embodiment, the via is wider than the metal cap. In an embodiment, the semiconductor device further comprises an etch stop layer between the first dielectric layer and the second dielectric layer, wherein the via extends through the etch stop layer. In an embodiment, the via physically contacts the second dielectric layer. In an embodiment, the semiconductor device further comprises a barrier layer between the conductive line and the first dielectric layer.
In an embodiment, a semiconductor device includes a substrate; a first dielectric layer over the substrate, the first dielectric layer being a single layer; a conductive feature in the first dielectric layer, the conductive feature comprising a first conductive material, a first surface of the conductive feature distal from the substrate being closer to the substrate than a first surface of the first dielectric layer distal from the substrate; a second dielectric layer over the first dielectric layer and the conductive feature; and a conductive plug having upper and lower portions, the upper and lower portions comprising a second conductive material different from the first conductive material, the upper portion of the conductive plug disposed in the second dielectric layer, the lower portion of the conductive plug extending into the first dielectric layer and being physically connected to the conductive member. In an embodiment, a width of a lower portion of the conductive plug is greater than a width of the conductive member. In an embodiment, the conductive plug is in physical contact with the second dielectric layer. In an embodiment, the semiconductor device further comprises a barrier layer between the conductive feature and the first dielectric layer. In an embodiment, a first density of an upper portion of the conductive plug is higher than a second density of a lower portion of the conductive plug.
In an embodiment, a method of forming a semiconductor device includes forming a first dielectric layer over a substrate; forming a conductive line in the first dielectric layer using the first material, wherein after forming the conductive line, there is a recess in the first dielectric layer proximate an upper surface of the first dielectric layer remote from the substrate, wherein a bottom of the recess exposes the upper surface of the conductive line; filling the recess in the first dielectric layer with a second material different from the first material to form a metal cap, wherein the metal cap is wider than the conductive line; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer to expose the metal cap; and filling the opening with a second material to form a via. In an embodiment, forming the conductive line includes forming a through-hole in the first dielectric layer, the through-hole having an upper portion proximate to an upper surface of the first dielectric layer and a lower portion located below the upper portion, the upper portion of the through-hole being wider than the lower portion of the through-hole; filling the through-hole with a first material, a first portion of the first material filling an upper portion of the through-hole, and a second portion of the first material filling a lower portion of the through-hole; reducing the height of the first portion of the first material and the height of the first dielectric layer; after the reducing, a remaining portion of the first material is removed to form a recess in the first dielectric layer, wherein the second portion of the first material forms a conductive line after the removing. In an embodiment, filling the opening comprises depositing a first sub-layer comprising a second material in the opening using Atomic Layer Deposition (ALD); a second sub-layer comprising a second material is deposited over the first sub-layer in the opening using a deposition method other than ALD. In an embodiment, the opening is formed wider than the metal cap. In an embodiment, the first material is cobalt and the second material is tungsten.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A semiconductor device, comprising:
a first dielectric layer over a substrate, the first dielectric layer comprising a first dielectric material extending from a first side of the first dielectric layer away from the substrate to a second side of the first dielectric layer opposite the first side;
a second dielectric layer over the first dielectric layer;
a conductive line in the first dielectric layer, the conductive line comprising a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer;
a metal cap in the first dielectric layer, the metal cap overlying and physically connected to the conductive line, the metal cap comprising a second conductive material different from the first conductive material, a first width of the metal cap measured along a first direction parallel to a major upper surface of the substrate between opposing sidewalls of the metal cap being greater than a second width of the conductive line measured along the first direction between opposing sidewalls of the conductive line, and wherein a bottom surface of a portion of the metal cap extending beyond the conductive line physically contacts the first dielectric layer; and
a via in the second dielectric layer and physically connected to the metal cap, the via comprising the second conductive material.
2. The semiconductor device of claim 1, wherein an upper surface of the metal cap is flush with an upper surface of the first dielectric layer.
3. The semiconductor device of claim 1, wherein the via has an inner portion and an outer portion surrounding the inner portion, the outer portion physically contacting the second dielectric layer, wherein the outer portion of the via and the inner portion of the via comprise the second conductive material, and the first material density of the outer portion is higher than the second material density of the inner portion.
4. The semiconductor device of claim 3, wherein the metal cap has sidewalls perpendicular to an upper surface of the conductive line.
5. The semiconductor device of claim 3, wherein the metal cap has sidewalls that are sloped with respect to an upper surface of the conductive line.
6. The semiconductor device of claim 3, wherein the first conductive material is cobalt and the second conductive material is tungsten.
7. The semiconductor device of claim 3, wherein a third width of the via measured along the first direction between opposing sidewalls of the via is greater than the first width of the metal cap.
8. The semiconductor device of claim 1, further comprising an etch stop layer between the first dielectric layer and the second dielectric layer, wherein the via extends through the etch stop layer.
9. The semiconductor device of claim 1, wherein the via physically contacts the second dielectric layer.
10. The semiconductor device of claim 9, further comprising a barrier layer between the conductive line and the first dielectric layer.
11. A semiconductor device, comprising:
a substrate;
a first dielectric layer over the substrate, the first dielectric layer being a single layer;
a conductive member in the first dielectric layer, the conductive member comprising a first conductive material, a first surface of the conductive member distal from the substrate being closer to the substrate than a first surface of the first dielectric layer distal from the substrate;
a second dielectric layer over the first dielectric layer and the conductive feature; and
a conductive plug having an upper portion and a lower portion, the upper portion and the lower portion comprising a second conductive material different from the first conductive material, the upper portion of the conductive plug disposed in the second dielectric layer, the lower portion of the conductive plug extending into the first dielectric layer and being physically connected to the conductive member,
wherein a first width of a lower portion of the conductive plug measured between opposing sidewalls of the lower portion of the conductive plug along a first direction parallel to a major upper surface of the substrate is greater than a second width of the conductive feature measured between opposing sidewalls of the conductive feature along the first direction, and wherein a bottom surface of a portion of the lower portion of the conductive plug extending beyond the conductive feature physically contacts the first dielectric layer.
12. The semiconductor device of claim 11, wherein a width of a lower portion of the conductive plug is greater than a width of the conductive feature.
13. The semiconductor device of claim 12, wherein the conductive plug is in physical contact with the second dielectric layer.
14. The semiconductor device of claim 13, further comprising a barrier layer between the conductive feature and the first dielectric layer.
15. The semiconductor device of claim 12, wherein a first density of an upper portion of the conductive plug is higher than a second density of a lower portion of the conductive plug.
16. A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate;
forming a conductive line in the first dielectric layer using a first material, wherein after forming the conductive line, there is a recess in the first dielectric layer proximate an upper surface of the first dielectric layer distal from the substrate, wherein a bottom of the recess exposes the upper surface of the conductive line;
filling the recess in the first dielectric layer with a second material different from the first material to form a metal cap, wherein the metal cap is wider than the conductive line;
forming a second dielectric layer over the first dielectric layer;
forming an opening in the second dielectric layer to expose the metal cap; and
filling the opening with the second material to form a via,
wherein a first width of the metal cap measured between opposing sidewalls of the metal cap along a first direction parallel to a major upper surface of the substrate is greater than a second width of the conductive line measured between opposing sidewalls of the conductive line along the first direction, and wherein a bottom surface of a portion of the metal cap extending beyond the conductive line physically contacts the first dielectric layer.
17. The method of claim 16, wherein forming the conductive line comprises:
forming a through-hole in the first dielectric layer, the through-hole having an upper portion near an upper surface of the first dielectric layer and a lower portion located below the upper portion, the upper portion of the through-hole being wider than the lower portion of the through-hole;
filling the through-hole with the first material, a first portion of the first material filling an upper portion of the through-hole, and a second portion of the first material filling a lower portion of the through-hole;
reducing the height of the first portion of the first material and the height of the first dielectric layer; and
after the reducing, removing a remaining portion of the first material to form the recess in the first dielectric layer, wherein the second portion of the first material forms the conductive line after the removing.
18. The method of claim 16, wherein filling the opening comprises:
depositing a first sub-layer comprising the second material in the opening using Atomic Layer Deposition (ALD);
depositing a second sub-layer comprising a second material over the first sub-layer in the opening using a deposition method other than the atomic layer deposition.
19. The method of claim 16, wherein the opening is formed wider than the metal cap.
20. The method of claim 16, wherein the first material is cobalt and the second material is tungsten.
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US9437540B2 (en) * 2014-09-12 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Additional etching to increase via contact area

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