CN110970349A - Method for preparing a diffusion barrier comprising an α -Ta layer and composite diffusion barrier - Google Patents

Method for preparing a diffusion barrier comprising an α -Ta layer and composite diffusion barrier Download PDF

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Publication number
CN110970349A
CN110970349A CN201811142728.2A CN201811142728A CN110970349A CN 110970349 A CN110970349 A CN 110970349A CN 201811142728 A CN201811142728 A CN 201811142728A CN 110970349 A CN110970349 A CN 110970349A
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CN
China
Prior art keywords
layer
tan
diffusion barrier
copper
inert gas
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CN201811142728.2A
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Chinese (zh)
Inventor
任兴润
王婷
汪雷
刘洋
何丹丹
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN201811142728.2A priority Critical patent/CN110970349A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

Abstract

The invention provides a preparation method of a diffusion barrier layer containing a α -Ta layer, which comprises the steps of firstly forming a TaN layer, carrying out inert gas plasma treatment on the TaN layer, and then depositing Ta on the surface of the TaN layer subjected to inert gas plasma treatment to form a α -Ta layer.

Description

Method for preparing a diffusion barrier comprising an α -Ta layer and composite diffusion barrier
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a diffusion barrier layer containing an α -Ta layer, an obtained composite diffusion barrier layer and a copper interconnection forming method.
Background
Copper is widely used in metal interconnect processes for integrated circuits due to its relatively low resistivity and relatively good electromigration resistance. However, since copper is in the dielectric, such as silicon dioxide (SiO)2) Silicon (Si), etc., have strong diffusion capability, and therefore a diffusion barrier layer needs to be added between the copper and the dielectric. Refractory metals, particularly tantalum and its nitrides, are widely used due to their superior barrier properties and thermal stability.
Due to the shrinking of the manufacturing process, the size of the device is continuously reduced, the density of interconnection wiring is rapidly increased, the RC coupling parasitic effect brought by resistance and capacitance in an interconnection system is rapidly increased, and the speed of the device is influenced. As the line width is gradually reduced, the resistance of the metal line is also increased. The refractory metal barrier layer cannot be scaled down with the line width due to the need of keeping a certain thickness to stabilize the copper diffusion resistance, thereby seriously affecting the resistance of the metal line.
Tantalum is the most common diffusion barrier for copper and has two crystal structures, α phase with stable body-centered cubic structure and low resistance and β phase with tetragonal metastable phase and high resistance, for a typical diffusion barrier, the β -Ta layer has a resistance of about 180-220 μ Ω · cm, while the α -Ta layer has a resistance of only 24-50 μ Ω · cm.
In the existing dual damascene process, Ta is mainly deposited by PVD and other technologies as a diffusion barrier layer of copper, and the obtained Ta film is mainly β -phase Ta and has high resistance, so that the resistance of a wire is increased, RC delay is increased, and the performance of a device is influenced.
Disclosure of Invention
To overcome the defects of the prior art, the invention aims to provide a preparation method of a diffusion barrier layer containing α -Ta layer, which prepares α -phase Ta with low resistance in the formed Ta layer.
Another object of the present invention is to provide a method of forming a copper interconnect.
Another object of the present invention is to provide a composite diffusion barrier layer and a semiconductor device.
The preparation method of the diffusion impervious layer containing the α -Ta layer comprises the following steps:
s1: forming a TaN layer, and carrying out inert gas plasma treatment on the TaN layer; and
s2, depositing Ta on the surface of the TaN layer after the inert gas plasma treatment to form a α -Ta layer, and obtaining the diffusion barrier layer.
In the preparation method provided by the invention, the inert gas plasma in the step S1 is argon (Ar) or krypton (Kr) which is converted into plasma.
In the preparation method provided by the invention, in the inert gas plasma treatment in the step S1, the treatment time is 10-100S, the radio frequency energy is 100-2000W, and the gas flow is 10-100 sccm.
In the preparation method provided by the invention, the thickness of the TaN layer formed in the step S1 is 5-30 nm.
In the preparation method provided by the invention, the thickness of the TaN layer after inert gas plasma treatment is 3-25 nm.
In the preparation method provided by the invention, the thickness of the α -Ta layer in the step S2 is 5-30 nm.
The forming method of the copper interconnection provided by the invention comprises the following steps:
t1: preparing a dielectric layer with an interconnection groove on a substrate, wherein metal on the substrate is exposed to the bottom of the interconnection groove;
t2: forming a TaN layer on the surface of the interconnection groove;
t3: performing inert gas plasma treatment on the TaN layer;
t4 depositing Ta on the TaN layer to form α -Ta layer, and
t5: preparing a copper wire layer in the interconnection trench to thereby form a copper interconnection.
In the forming method of the copper interconnection, the thickness of the TaN layer after being treated by the inert gas plasma is 3-25 nm.
In the forming method of the copper interconnection, the α -Ta layer is 5-30nm thick.
In the method for forming the copper interconnection, the metal on the substrate is copper or tungsten.
The composite diffusion impervious layer provided by the invention is used for preventing copper from diffusing to a dielectric layer in a semiconductor device and comprises a TaN layer and an α -Ta layer covering the TaN layer.
In the composite diffusion impervious layer provided by the invention, the thickness of the TaN layer is 3-25 nm.
In the composite diffusion impervious layer provided by the invention, the thickness of the α -Ta layer is 5-30 nm.
The semiconductor device provided by the invention comprises a copper wire layer, a dielectric layer and a diffusion barrier layer for preventing copper from diffusing into the dielectric layer, wherein the diffusion barrier layer is the composite diffusion barrier layer in any one of the technical schemes.
The diffusion barrier layer formed by the preparation method comprises the TaN layer and the α -phase Ta layer with low resistance, the α -phase Ta layer can obviously reduce the resistance value of the barrier layer, and the TaN layer has the function of preventing metal diffusion and higher mechanical strength while providing nucleation growth points for the α -Ta layer, so that the performance of the composite diffusion barrier layer can be further improved.
The preparation method and the copper interconnection method can directly utilize the existing PVD and other devices to finish the deposition of the diffusion barrier layer and the metal in the same equipment, and have the advantages of simple process, convenient operation and easy industrial popularization.
Drawings
Fig. 1A to 1D are flowcharts of a method of forming a copper interconnect according to embodiment 1.
Fig. 2 is a schematic cross-sectional view of the composite diffusion barrier layer of example 1.
Fig. 3 is a schematic cross-sectional view of the formed interconnect trench in step 1 of embodiment 2.
Wherein the reference numerals are as follows:
101. a dielectric layer 102, a first copper wire layer 103, a barrier layer 104, a TaN layer 105, α -Ta layer;
201. a first dielectric layer; 202. a contact hole; 203. a barrier layer; 204. a second dielectric layer.
Detailed Description
To make the objects, technical solutions and advantages of the present invention clearer, example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
One aspect of the present invention provides a method of making a diffusion barrier comprising an α -Ta layer, the diffusion barrier being useful for blocking diffusion of copper into a dielectric layer in a semiconductor device, comprising the steps of:
s1: forming a TaN layer, and carrying out inert gas plasma treatment on the TaN layer; and
s2, depositing Ta on the surface of the TaN layer after the inert gas plasma treatment to form a α -Ta layer, and obtaining the diffusion barrier layer.
The preparation method of the invention is used for preparing a TaN/Ta double diffusion barrier layer, the TaN film is firstly formed by deposition, then the TaN film is treated by inert gas plasma, the content of N on the surface layer of the treated TaN is reduced, and smaller lattice mismatching degree can be provided for the subsequent Ta deposition, so that more α -Ta nucleation points are provided, the nucleation energy of α -Ta is reduced, the formation of α -Ta is facilitated, and β -phase Ta is difficult to form.
Another aspect of the present invention provides a method of forming a copper interconnect, comprising the steps of:
t1: preparing a dielectric layer with an interconnection groove on a substrate, wherein metal on the substrate is exposed to the bottom of the interconnection groove;
t2: forming a TaN layer on the surface of the interconnection groove;
t3: performing inert gas plasma treatment on the TaN layer;
t4 depositing Ta on the TaN layer to form α -Ta layer, and
t5: preparing a copper wire layer in the interconnection trench to thereby form a copper interconnection.
In one embodiment of the present invention, the dielectric layer may be a common dielectric layer material such as silicon dioxide, and may be formed by a conventional process.
In one embodiment according to the present invention, the TaN deposition process may be performed by a conventional process, using a conventional apparatus, such as PVD, MOCVD, ALD, etc. In a preferred embodiment, the deposition power can be 5-30KW, the deposition time can be 5-60s, and the thickness of the TaN layer obtained after deposition can be 5-30 nm.
In one embodiment according to the invention, the inert gas plasma may be argon or krypton plasma-ized of the plasma.
In one embodiment according to the present invention, the inert gas plasma treatment may be performed by a conventional process using a conventional apparatus. In a preferred embodiment, the plasma treatment time can be 10-100s, the RF power can be 100-2000W, and the gas flow can be 10-100 sccm.
In one embodiment according to the present invention, after the inert gas plasma treatment, the original TaN layer thickness is reduced compared to the TaN layer before the treatment due to the reduced N content of the TaN layer, and the reduced thickness may be 2-5nm, i.e. the TaN layer thickness after the inert gas plasma treatment may be 3-25 nm.
In one embodiment according to the present invention, the Ta deposition process may also be performed by a conventional process, using a conventional apparatus, such as PVD, MOCVD, ALD, etc. In a preferred embodiment, the deposition power may be 5-20KW and the deposition time may be 5-60 s.
In one embodiment according to the present invention, the thickness of the α -Ta layer may be determined based on resistance, diffusion barrier properties, device size, etc. in a preferred embodiment, the α -Ta layer may be 5-30nm thick.
In one embodiment of the present invention, the substrate may be a copper wire layer or a dielectric layer including a contact hole filled with metal tungsten. In a preferred embodiment, the substrate may be a copper wire layer, which is a first copper wire layer, and the copper wire layer formed within the interconnect trench is a second copper wire layer. In another preferred embodiment, the substrate may be a first dielectric layer containing contact holes, and a second dielectric layer having interconnection trenches is prepared on the substrate.
In one embodiment according to the present invention, the step T1 may be formed according to an existing process; in a preferred embodiment, the following steps may be included:
t11: providing a substrate;
t12: depositing a dielectric layer on the substrate; and
t13: and forming an interconnection groove on the dielectric layer, and exposing the metal on the substrate to the bottom of the interconnection groove.
In an embodiment according to the present invention, a pre-cleaning step for the interconnection trench may be further included between the steps T1 and T2.
Therefore, the invention also provides a composite diffusion barrier layer which can be used for preventing copper of a copper wire layer from diffusing to a dielectric layer in a semiconductor device and comprises a TaN layer and an α -Ta layer covering the TaN layer.
The thickness of the TaN layer can be 3-25nm, and the thickness of the α -Ta layer can be 5-30 nm.
The composite diffusion impervious layer can obviously reduce the resistance of the diffusion impervious layer, thereby reducing the resistance of the copper wire and further improving the performance of the semiconductor device. Therefore, the invention also provides a semiconductor device comprising a copper wire layer, a dielectric layer and a diffusion barrier layer for preventing copper from diffusing into the dielectric layer, wherein the diffusion barrier layer is the composite diffusion barrier layer.
The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Example 1
Forming a copper interconnect using a dual damascene process, comprising the steps of:
1. a substrate is provided as a first copper wire layer 102, a thin layer of silicon carbonitride (SiCN) is deposited as a barrier layer 103 on the first copper wire layer 102, then a layer of silicon dioxide with a certain thickness is deposited as a dielectric layer 101, and an interconnection trench is formed by photolithography, as shown in fig. 1A.
2. Using H2And pre-cleaning the formed interconnection trench.
3. A TaN layer 104 is deposited by PVD within the interconnect trench to a thickness of about 5-30nm as shown in fig. 1B.
4. Performing argon plasma treatment on the TaN layer 104 for 10-60s, wherein the argon flow is 10-100sccm, the RF energy is 100-2000W (RF1: 100-2000W; RF2:100-600W), and the thickness of the TaN layer 104 after the plasma treatment is about 3-25nm, as shown in FIG. 1C.
5. Ta is deposited on the TaN layer 104 treated by the argon plasma through a PVD process (direct current voltage: 5-20 KW; RF: 100-.
6. After the diffusion barrier layer was formed, a copper seed layer was deposited by PVD.
7. And finally, obtaining a second copper wire layer through a copper electroplating process, and forming interconnection with the first copper wire layer.
The diffusion barrier layer formed in the interconnect trench by the above process is a composite double diffusion barrier layer, i.e., a TaN layer 104 covering the bottom and sidewalls of the interconnect trench and an α -Ta layer 105 covering the TaN layer 104, as shown in fig. 2.
The film resistivity of α -Ta layer was tested to be less than 50 μ Ω cm and it can be seen that the Ta layer formed in example 1 was the low resistivity phase α -Ta.
Example 2
A copper interconnect was formed using a method similar to that of example 1.
1. Providing a substrate, wherein the substrate body is a first dielectric layer 201 of silicon dioxide, providing a contact hole 202, filling metal tungsten in the contact hole 202, depositing a barrier layer 203 on the substrate, then depositing silicon dioxide as a second dielectric layer 204, and forming an interconnection trench on the barrier layer 203 and the second dielectric layer 204 by photolithography, so that the metal tungsten is exposed at the bottom of the interconnection trench, as shown in fig. 3.
2. Using H2The interconnect trench is precleaned.
3. And depositing a TaN layer with the thickness of about 5-30nm in the interconnection trench after the pre-cleaning.
4. And performing argon plasma treatment on the TaN layer.
5. And depositing Ta on the TaN layer treated by the argon plasma, thereby forming an α -Ta layer with a thickness of about 5-30nm on the TaN layer.
6. And after the diffusion barrier layer is formed, sequentially carrying out copper seed layer deposition and copper electroplating processes to obtain a copper wire layer.
The film resistivity of the α -Ta layer was tested and was also less than 50 μ Ω cm.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (10)

1. A method of making a diffusion barrier comprising an α -Ta layer, comprising the steps of:
s1: forming a TaN layer, and carrying out inert gas plasma treatment on the TaN layer; and
s2, depositing Ta on the surface of the TaN layer after the inert gas plasma treatment to form a α -Ta layer, and obtaining the diffusion barrier layer.
2. The method of claim 1, wherein the inert gas plasma of step S1 is plasma-formed argon or krypton.
3. The method as claimed in claim 2, wherein in the inert gas plasma treatment of step S1, the treatment time is 10-100S, the RF energy is 100-2000W, and the gas flow rate is 10-100 sccm.
4. The method according to any of claims 1-3, wherein the TaN layer has a thickness of 5-30nm and a thickness of 3-25nm after the inert gas plasma treatment; and/or
The thickness of the α -Ta layer is 5-30 nm.
5. A method for forming a copper interconnect, comprising the steps of:
t1: preparing a dielectric layer with an interconnection groove on a substrate, wherein metal on the substrate is exposed to the bottom of the interconnection groove;
t2: forming a TaN layer on the surface of the interconnection groove;
t3: performing inert gas plasma treatment on the TaN layer;
t4 depositing Ta on the TaN layer to form α -Ta layer, and
t5: preparing a copper wire layer in the interconnection trench to thereby form a copper interconnection.
6. The method as claimed in claim 5, wherein the TaN layer has a thickness of 5-30nm and a thickness of 3-25nm after the inert gas plasma treatment; and/or
The thickness of the α -Ta layer is 5-30 nm.
7. The method of forming as claimed in claim 5 or 6, wherein the metal on the substrate is copper or tungsten.
8. A composite diffusion impervious layer is used for preventing copper from diffusing to a dielectric layer in a semiconductor device and is characterized by comprising a TaN layer and an α -Ta layer covering the TaN layer.
9. The composite diffusion barrier layer of claim 8 wherein the TaN layer is 3-25nm thick; and/or
The thickness of the α -Ta layer is 5-30 nm.
10. A semiconductor device comprising a copper wire layer, a dielectric layer and a diffusion barrier layer for preventing diffusion of copper into said dielectric layer, wherein said diffusion barrier layer is the composite diffusion barrier layer of claim 8 or 9.
CN201811142728.2A 2018-09-28 2018-09-28 Method for preparing a diffusion barrier comprising an α -Ta layer and composite diffusion barrier Pending CN110970349A (en)

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