CN110970312B

CN110970312B - Package and method of forming the same

Info

Publication number: CN110970312B
Application number: CN201910917900.5A
Authority: CN
Inventors: 蔡柏豪; 游明志; 许佳桂; 郑心圃; 庄博尧; 林孟良; 洪士庭; 林柏尧
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-09-28
Filing date: 2019-09-26
Publication date: 2022-03-04
Anticipated expiration: 2039-09-26
Also published as: KR102494297B1; CN110970312A; KR102383912B1; TW202032679A; KR20220045950A; KR20200037066A; TWI754839B; DE102019117199A1

Abstract

Embodiments include forming an interposer having a reinforcing structure disposed in a core layer of the interposer. The interposer may be attached to the packaged device by electrical connections. The reinforcing structure provides rigidity and heat dissipation to the packaged device. Some embodiments may include an interposer having openings to recessed bond pads in an upper core layer of the interposer. Some embodiments may also use connections between the interposer and the packaged device, where the solder material connected to the interposer surrounds the metal posts connected to the packaged device. Embodiments of the invention also relate to packages and methods of forming the same.

Description

Package and method of forming the same

Technical Field

Embodiments of the invention relate to a package and a method of forming the same.

Background

The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to the repeated reduction in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a need for smaller and more creative packaging techniques for semiconductor dies. An example of such a packaging system is the package on package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and small footprint on Printed Circuit Boards (PCBs).

Disclosure of Invention

An embodiment of the present invention provides a method of forming a package, including: forming an opening in a core layer of an interposer; forming a reinforcing structure in the opening, the reinforcing structure extending from the first surface of the interposer to the second surface of the interposer, the reinforcing structure being electrically isolated from the conductive features of the interposer; forming a first connection on the interposer at the first surface of the interposer; bonding the first connections of the interposer to second connections of a first packaged device; and forming a molding compound between the interposer and the first packaged device.

Another embodiment of the present invention provides a method of forming a package, including: aligning first connectors of a first package element with second connectors of a second package element, the first connectors comprising a solder material, each of the second connectors comprising a metal post protruding from a metal step; contacting the first connector with the second connector; reflowing the solder material, the solder material flowing to surround each of the metal pillars and contact each of the metal steps, wherein a portion of the solder material surrounding the metal pillars is located within a lateral extent of the metal steps.

Yet another embodiment of the present invention provides a package structure including: a first device package comprising: an integrated circuit die having an active side facing down, a redistribution structure, one or more contacts coupled to the integrated circuit die, and a first contact disposed at an upper surface of the redistribution structure; and an interposer, the interposer comprising: a substrate core layer, one or more metal vias disposed in the substrate core layer, one or more reinforcement structures disposed in the substrate core layer, the one or more reinforcement structures being electrically decoupled, and second contacts disposed at a lower surface of the interposer, the first contacts being coupled to respective ones of the second contacts.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1-13 illustrate various intermediate steps in a process of forming an interposer, according to some embodiments.

Fig. 14-30 illustrate various intermediate steps in a process of forming an interposer, according to some embodiments.

Fig. 31-36 illustrate various intermediate steps in a process of forming a fan-out bottom package, according to some embodiments.

Fig. 36-45 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer, according to some embodiments.

Fig. 46-47 illustrate views of a package including a fan-out bottom package and a second device attached together without an interposer, but using connectors around metal posts, according to some embodiments.

Fig. 48-50 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer with an adhesive formed therebetween, according to some embodiments.

Fig. 51-54 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package having a molding compound previously formed thereon and an interposer, according to some embodiments.

Fig. 55-70 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer with a cavity or through via formed therein, according to some embodiments.

Fig. 71-79 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer having an upper core layer with recessed bond pads formed therein, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

Some embodiments include a fan-out bottom package that includes a die and has an interposer attached thereto. The interposer may include a reinforcing structure disposed through a core layer of the interposer. The reinforcing structure may help provide support, rigidity, and heat dissipation. Due to the additional rigidity of the interposer with the reinforcing structure, packaging handling risks may be reduced. In addition, the support provided by the interposer may be used to better control package warpage, thereby providing better Dynamic Random Access Memory (DRAM) or Surface Mount Technology (SMT) connector windows. In some embodiments, the interposer may have a cavity or through-via disposed therein that is aligned with a die of the fan-out bottom package, wherein the die is at least partially disposed in the cavity or through-via to reduce an overall thickness of the package. In some embodiments, an adhesive may be used between the interposer and the die of the fan-out bottom package.

In some embodiments, the interposer may have a second core layer disposed above the first core layer with a recessed bond pad disposed between the first and second core layers. The recessed bond pads are exposed through the second core layer to provide a deep recess for a connector to an overlying device or package, thereby reducing the overall package height. The recessed bond pads also provide good alignment with the overlying devices. In some embodiments, the interposer may have a second core layer and a reinforcing structure disposed in one or both core layers. In some embodiments, the interposer may have a cavity or through-via disposed therein that is aligned with a die of the fan-out bottom package, wherein the die is at least partially disposed within the cavity or through-via.

In some embodiments, stepped bond pads may be used between the fanout bottom package and an overlying top package (e.g., interposer or second device). The stepped bond pads provide enhanced and robust junction reliability that may otherwise suffer from cracking due to warpage of the top package above. The stepped bond pads also support a fine pitch process to reduce the pitch between connectors. The stepped bond pads also provide a controllable joint support between the fanout bottom package and the top package above. The stepped bond pads also provide good self-alignment for bonding to the top package above. Stepped bond pads may be used with any of the other embodiments described herein, including any of the interposers discussed herein. The stepped bond pads may be used in embodiments that do not include an interposer, but the upper package is a device package bonded to a fan-out bottom package.

These embodiments will be discussed in detail by the description of the figures. However, it should be understood that the features of each embodiment discussed in detail herein may be combined in any suitable manner, even if such a combination is not explicitly disclosed.

Fig. 1-30 illustrate cross-sectional views of intermediate steps of a process for forming an interposer substrate 100 (fig. 1-13) or an interposer substrate 200 (fig. 14-30) according to some embodiments. Interposer substrate 100 includes one core layer as further described below, and interposer substrate 200 includes more than one core layer as further described below. Although the formation of one interposer substrate 100, such as in fig. 1-12, is shown, and the formation of one interposer substrate 200 is shown, such as in fig. 13-29, it is to be understood that multiple interposer substrates 100 or multiple interposer substrates 200 may be formed simultaneously using the same wafer or substrate, and may be subsequently singulated to form individual interposer substrates 100 or interposer substrates 200.

Fig. 1-13 show cross-sectional views of intermediate steps of a process for forming an interposer substrate 100. In fig. 1, a carrier substrate 102 is provided and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer such that multiple packages may be formed on the carrier substrate 102 at the same time. The release layer 104 may be formed of a polymer-based material, and the release layer 104 may be removed along with the carrier substrate 102 from overlying structures to be formed in a subsequent step. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesion upon heating, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an Ultraviolet (UV) glue that loses its adhesion when exposed to UV light. The release layer 104 may be dispensed as a liquid and cured, may be a laminate film laminated on the carrier substrate 102, or the like. The top surface of the release layer 104 may be horizontal.

A conductive layer 105 may be formed over the release layer 104. Conductive layer 105 may be one or more layers of copper, titanium, nickel, aluminum, combinations thereof, and the like, and may be formed using any suitable process, such as by metal foil lamination, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and the like.

Referring now to fig. 2, the conductive layer 105 may be patterned using acceptable photolithographic techniques to form a conductive pattern of conductive lines 106. For example, a photoresist may be deposited over conductive layer 105, the photoresist developed to expose negative portions of the conductive pattern, and the exposed portions of conductive layer 105 removed by an acceptable etching technique. The conductive pattern of the conductive lines 106 may route signal, power, and/or ground lines over the surface of a subsequently formed intermediate core layer, e.g., from one via through the core layer to another via in the core layer.

In some embodiments, the process of forming the conductive pattern of wires 106 may be repeated multiple times to form a redistribution structure, such as redistribution structure 306 discussed below with reference to fig. 32. In such embodiments, a dielectric layer may be used to separate the different layers of the conductive lines 106, as discussed below with respect to the redistribution structure 306.

Referring to fig. 3, one or more substrate cores are formed over conductive lines 106. For ease of reference, these will be referred to collectively asA substrate core 110. Substrate core 110 may be formed from pre-impregnated composite fibers ("prepreg"), insulating or laminate films, paper, fiberglass, non-woven glass fabric, silicon, and the like. In some embodiments, substrate core 110 is formed from a prepreg that includes glass fibers and a resin. In some embodiments, the substrate core 110 may be a copper clad epoxy impregnated glass cloth laminate, a copper clad polyimide impregnated glass cloth laminate, or the like. The substrate core 110 may have a thickness T between 20 μm to about 200 μm₁Such as about 100 μm, although other thicknesses are contemplated and may be used. The substrate core 110 may be made of several different layers.

A conductive layer 112 may be formed over the substrate core 110. Conductive layer 112 may be one or more layers of copper, titanium, nickel, aluminum, combinations thereof, and the like, and may be formed using any suitable process, such as by metal foil lamination, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and the like. In some embodiments, the conductive layer 112 may be a foil that is heat laminated to the substrate core 110.

In fig. 4, an opening 114 is formed through the conductive layer 112 to the substrate core 110. In some embodiments, the openings 114 are formed by laser drilling. Other processes, such as mechanical drilling using a drill bit, may also be used to form the opening 114. Any other suitable process may be used to form the opening 114. The opening 114 may have any top view shape, such as polygonal, circular, and the like. A cleaning process may then be performed to clean the area near the opening 114, which may have been contaminated with the removed material of the substrate core 110. Opening 114 may have a width W between about 50 μm and about 250 μm₁Such as about 100 μm, although other values are contemplated and may be used. In some embodiments, the openings 114 may be formed in a regular pattern having a pitch P between 100 μm and about 300 μm₁Such as about 230 μm, although other values are contemplated and may be used. In some embodiments, the width W of the opening 114₁May differ in different portions of the substrate core 110. For example, fig. 9 shows irregular reinforcing structures 122 resulting from corresponding irregular openings 114. In some embodiments of the present invention, the,the pattern of the openings 114 may be different for subsequently formed reinforcing structures and conductive vias. In some embodiments, the openings 114 may be random for subsequently formed reinforcing structures and conductive vias.

In fig. 5, conductive vias 116 are formed in some of the openings 114 and reinforcing structures 120 are formed in the remaining openings 114. In addition, the conductive layer 112 is used to form a wire 113 on the substrate core 110.

With respect to the conductive via 116 and the conductive line 113, the conductive via 116 may be formed of a conductive material such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, the conductive vias 116 and the conductive lines 113 may be formed of the same material or different materials, and may be formed by the same process or different processes. In other embodiments, conductive via 116 is formed by a first process and conductive line 113 is formed by a second process.

With respect to the reinforcement structure 120, in some embodiments, the reinforcement structure 120 may be formed in the same or different process as the conductive via 116. In embodiments where the enhancement structure 120 is formed in the same process as the conductive via 116, the enhancement structure 120 and the conductive via 116 may be formed from the same conductive material, however, the conductive material of the enhancement structure 120 is uncoupled and electrically floating. In embodiments where the enhancement structure 120 is formed in a different process than the conductive via 116, the enhancement structure 120 may be formed using the same or different material as the conductive via 116. In such embodiments, either the conductive vias 116 or the reinforcing structures 120 may be formed first.

Referring to the formation of conductive via 116 and conductive line 113, conductive via 116 and conductive line 113 may be formed by any suitable process. For example, in some embodiments, the opening 114 that will subsequently become the enhancement structure 120 is masked while the opening 114 that will become the conductive via 116 is exposed.

In the process of forming the conductive via 116 and the conductive line 113, respectively, a seed layer (not shown) may be formed in the exposed opening 114. A plating process, such as electroplating or electroless plating, may be used to deposit a conductive material in the openings 114 to form the conductive vias 116. To form conductive line 113, a photoresist may be formed over conductive layer 112 and patterned with a reverse image of conductive line 113 to expose portions of conductive layer 112 that are not included in the pattern of conductive line 113. The exposed portions of conductive layer 112 may then be removed, for example, by an appropriate etching process (e.g., by wet or dry etching) to form conductive lines 113. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. The conductive line 113 may be formed before or after the conductive via 116 is formed. An example structure resulting from this process is shown enlarged (left enlargement) in fig. 5.

In the process of forming the conductive via 116 and the conductive line 113 in the same process, a seed layer (not shown) formed in the exposure opening 114 may also extend over a portion of the conductive layer 112 that will become the conductive line 113. A photoresist may be formed over the conductive layer 112 and the seed layer and patterned with an image of the conductive lines 113 to expose portions of the seed layer included in the pattern of the conductive lines 113. The plating process may be for depositing a conductive material on the seed layer, the conductive material located in the openings 114 forming conductive vias 116, and the conductive material exposed by the photoresist forming conductive material 112 p. After plating, the photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. The exposed portions of the seed layer may then be removed, followed by the removal of the exposed portions of the conductive layer 112. Removing the seed layer and portions of the conductive layer 112 may be by an acceptable etch process, such as by wet or dry etching. The exemplary structure resulting from this process is shown enlarged in fig. 5 (right enlargement).

The photoresist used above may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive pattern of the conductive line 113 or the reverse pattern of the conductive line 113 according to the process used, such as described above.

In some embodiments, the process of forming the wires 113 may be repeated any number of times to form a redistribution structure, such as the redistribution structure 306 discussed below with reference to fig. 32. In such embodiments, a dielectric layer may be used to separate the different layers of the conductive lines 113, as discussed below with respect to the redistribution structure 306.

Referring now to the reinforcing structures 120, the reinforcing structures 120 are formed in some of the openings 114. In some embodiments, the reinforcing structure 120 may be formed of a material having a high thermal conductivity, for example, between about 10W/m-K and 475W/m-K, such as about 400W/m-K, although other values are contemplated and used. In some embodiments, the reinforcing structure 120 may be formed of a material having a high stiffness (young's modulus), for example, between about 10GPa and about 380GPa, such as about 120GPa, although other values are contemplated and may be used. In some embodiments, the reinforcement structure 120 may be formed of a material having a Coefficient of Thermal Expansion (CTE) similar to that of the substrate core 110, for example between about 20 parts per million per degree celsius (PPM/° c) to about 100PPM/° c, such as about 30PPM/° c, although other values are contemplated and used. The reinforcing structure 120 may be selected to have one or more of a high thermal conductivity, a high stiffness, and a particular CTE.

In some embodiments, the material of the reinforcing structure 120 may be a metallic material, such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, the reinforcing structure 120 may be formed of a ceramic, such as alumina, zirconia, or the like. In other embodiments, the reinforcing structure 120 may be formed from a polymeric material, a graphite material, a silicon material, or a metallic or non-metallic conductive film. In some embodiments, the reinforcing structure 120 may be formed from a composite material or a combination of any of the above.

The reinforcing structure 120 improves heat dissipation and at the same time reduces warpage. The reinforcement structure 120 having a larger young's modulus may increase the strength of the substrate core 110. Generally, the greater the density of the reinforcement structures 120 in the substrate core 110, the less warpage occurs in subsequent thermal processes. When the reinforcing structure 120 has a larger young's modulus and a higher thermal conductivity, heat is dissipated from the heat generating component through the reinforcing structure 120, and the reinforcing structure 120 is less susceptible to stress than the surrounding material of the substrate core 110.

The reinforcing structure 120 may be electrically floating, rather than electrically coupled to any other connection. The reinforcing structures 120 may have different shapes and sizes in a top view (see, e.g., fig. 9, showing reinforcing structures 122), and may be arranged in a pattern or randomly.

In other embodiments, the conductive vias 116 are formed using a different process. Depending on the material of the reinforcement structure 120, any suitable process may be used to form the reinforcement structure 120. For example, the metal may be formed in a manner similar to that described above with respect to conductive vias 116. Other materials may be formed by using photolithography to mask other openings 114 or conductive vias 116 and expose the openings 114 for forming the respective enhancement structures 120. A photoresist may be formed, for example, by spin coating or lamination, and then patterned by exposure to a suitable light source to expose the openings 114 to be used for the enhancement structures 120. After exposing the openings 114, the reinforcing structure 120 may be formed by electroplating or electroless plating of a metal material, or the like. After forming the enhancement structure 120, the photoresist may be removed by a wet and/or dry process, such as by an ashing technique. In another example, where the enhancement structure 120 is formed of a ceramic, the ceramic may be deposited using a CVD process. In yet another example, where the reinforcing structure 120 is formed of a polymer, the polymer may be deposited and cured using spin-coating or dispensing techniques. Other deposition methods are contemplated and may be used.

In some embodiments, a removal process, such as a planarization process, may be used to remove portions of the material of the enhancement structure 120, for example, to make the top of the enhancement structure 120 flush with another layer of the interposer substrate 100. In embodiments where the reinforcement structure 120 is formed prior to forming the conductive layer 112, the top of the reinforcement structure 120 may be flush with the top of the substrate core 110. In other embodiments, the top of the reinforcing structure may be flush with the top of the conductive line 113 or the top of the conductive via 116. In some embodiments, the same removal process or a separate removal process (such as a planarization process) may be used to make the top of the conductive line 113 flush with the top of the conductive via 116.

In fig. 6, the carrier substrate 102 is removed. The carrier substrate 102 may be detached (or "debonded") from the substrate core 110. In some embodiments, debonding includes projecting light, such as laser or UV light, onto the release layer 104 such that the release layer 104 decomposes under the heat of the light and the carrier substrate 102 may be removed.

A solder resist layer 124 is formed on the

conductive lines

106 and 113 on the opposite side of the substrate core 110. The solder resist layer 124 protects areas of the substrate core 110 from external damage. In some embodiments, the solder mask layer 124 is formed by depositing a photosensitive dielectric layer, exposing the photosensitive material with an optical pattern, and developing the exposed layer to form the opening 124 o. In some embodiments, the solder mask layer 124 is formed by depositing a non-photosensitive dielectric layer (e.g., silicon oxide or silicon nitride, etc.), and patterning the dielectric layer to form the opening 124o using acceptable photolithography and etching techniques. Opening 124o exposes underlying portions of conductive line 113 and conductive line 106, which may be used as connector pads or under bump metallization in subsequent processes. The opening 124o may be tapered with a smaller width W at the deepest portion of the opening 124o₂And a larger width W at the shallowest portion of the opening 124o₃. Width W₂May be between about 55 μm and about 320 μm, such as about 180 μm, although other dimensions are contemplated and may be used. Width W₃May be between about 70 μm and about 350 μm, such as about 210 μm, although other dimensions are contemplated and may be used. Thickness T of each solder resist layer₂May be between about 5 μm and about 50 μm, such as about 25 μm, although other thicknesses are contemplated. Total thickness T of interposer substrate 100₃May be between about 50 μm and about 300 μm, such as about 100 μm, although other thicknesses are contemplated.

In fig. 7, the conductive connection 126 is formed in the opening 124o (see fig. 6). The conductive connection 126 may contact the exposed portion of the wire 106. The conductive connections 126 may be Ball Grid Array (BGA) connections, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), or the like. The conductive connection 126 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connection 126 is a eutectic connection formed by first forming a layer of eutectic material, such as solder, by common methods such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once a layer of solder is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 126 comprises a metal pillar, such as a copper pillar, formed by printing, electroplating, electroless plating, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or the like. The metal pillars may be solder-free and have substantially vertical sidewalls.

Fig. 8 and 9 are horizontal cross-sectional views through a substrate core 110 of an interposer substrate 100 according to various embodiments. In the embodiment of interposer substrate 100 shown in FIG. 8, reinforcing structures 120 are formed at various locations throughout interposer substrate 100. The reinforcing structure 120 may have substantially the same dimensions as the conductive vias 116 or different dimensions. The reinforcing structure 120 may be formed in the same pattern as the pattern of the conductive via 116 or a different pattern. In some embodiments, the reinforcing structures 120 may be randomly distributed. The embodiment of interposer substrate 100 shown in fig. 9 shows reinforcement structure 122 having an irregular shape and including a region between about 2 and 100 times the area of the other regions of reinforcement structure 120, but this region may be less than 2 times the area of reinforcement structure 122 or greater than 100 times the area of reinforcement structure 122. The reinforcing structure 122 may be located and designed to correspond to a particular device or hot spot in the attached package, and may help dissipate heat from the attached package.

Both fig. 8 and 9 show line AA, which shows a cross section taken from fig. 7. In the views shown in fig. 8 and 9, the total area of all of the reinforcing

structures

120 and 122 may be between 5% and about 80% of the total area of the interposer substrate 100 in a top view. The total volume of all of the reinforcing

structures

120 and 122 may be between about 5% and about 80% of the volume of the substrate core 110 of the interposer substrate 100.

Fig. 10 shows a top view, an intermediate view, and a bottom view of interposer substrate 100. As shown in fig. 10, conductive vias 116 may be located in a peripheral region of interposer substrate 100, and conductive lines 113 may provide routing from one conductive via 116 to another conductive via 116. Reinforcing structures 120 and/or 122 may be formed through the middle of substrate core 110.

FIG. 11 illustrates an interposer substrate 100 having a cavity 130 disposed therein, according to some embodiments. The cavity 130 may be formed by removing portions of the substrate core 110 and the solder resist layer 124 before or after forming the conductive connection 126. The removal of material to form the cavity 130 may be accomplished by a mechanical drilling process with computer numerical control. In such embodiments, material is removed by a mechanical drill bit, the position of which is controlled by a computer or controller. The removal may also be accomplished by other processes, such as a laser cutting process, a laser drilling process, and the like. The remaining portion of the material forms interposer substrate 100. The cavity 130 may have a height H of between about 20 μm and about 270 μm₁Such as about 50 μm, although other heights are contemplated and may be used. In such embodiments, the reinforcing structures 120 and/or 122 may be disposed in a thin portion of the interposer substrate 100 and/or in a peripheral portion of the interposer substrate 100. Accordingly, some such reinforcing structures 120 and/or 122 may likewise be thinned when forming the cavity 130. The cavity 130 may be formed at the location of the interposer substrate 100 such that it is aligned with mounting devices of the bottom fan-out package (discussed in further detail below) to reduce the overall thickness of the package formed when the interposer substrate 100 is attached to the bottom fan-out package.

Fig. 12 illustrates interposer substrate 100 having through vias 140 disposed therein, providing a ring shape, according to some embodiments. In some embodiments, the cavity 130 may be formed completely through the substrate core 110 and the solder resist layer 124 to form the through via 140. In such embodiments, the reinforcing structures 120 and/or 122 may be disposed in a peripheral portion of the interposer substrate 100. The through via 140 may be formed at a location of the interposer substrate 100 such that it is aligned with a mounting device of the bottom fan-out package (discussed in further detail below) to reduce the overall thickness of the package formed when the interposer substrate 100 is attached to the bottom fan-out package.

Fig. 13 illustrates a horizontal cross-sectional view through the substrate core 110 of the ring-shaped interposer substrate 100 shown in fig. 12 according to some embodiments. Line AA shows the cross section taken in fig. 12. The reinforcing structures 120 are formed at various locations throughout the interposer substrate 100. The reinforcing structure 120 may have substantially the same dimensions as the conductive vias 116 or different dimensions. The reinforcing structure 120 may be formed in the same pattern as the pattern of the conductive via 116 or a different pattern. In some embodiments, the reinforcing structures 120 may be randomly distributed. Although not shown in this view, a reinforcing structure 122 (see fig. 9) may be included. The total area of all of the reinforcing structures 120 and/or reinforcing structures 122 may be between about 5% and about 80% of the total area of the interposer substrate 100. The total volume of all of the reinforcing

structures

120 and 122 may be between about 5% to about 80% of the volume of the substrate core 110 of the interposer substrate 100.

Fig. 14-30 illustrate various embodiments of an interposer substrate 200, the interposer substrate 200 including one or more additional layers of substrate core 210. Fig. 14 illustrates a second substrate core 210 formed over substrate core 110 and conductive lines 113 according to some embodiments. After the conductive vias 116 and the conductive lines 113 of fig. 5 are formed, the second substrate core 210 may be laminated to the first substrate core 110 and the conductive lines 113. The second substrate core 210 may be formed using similar materials and processes to those discussed above with respect to substrate core 110 and will not be repeated. Conductive lines 212 may be formed over second substrate core 210. The conductive lines 212 may be formed by first forming the conductive layer using processes and materials similar to those discussed above with respect to conductive layer 112, and then patterning the conductive layer using processes and materials similar to those discussed above in the patterning of conductive lines 113 to produce conductive lines 212, and are not repeated. As shown in fig. 14, in some embodiments, neither substrate core 110 nor substrate core 210 has a reinforcing structure disposed therein. In some embodiments, the process of forming the wires 212 may be repeated any number of times to form a redistribution structure, such as redistribution structure 306 discussed below with respect to fig. 32. In such embodiments, a dielectric layer may be used to separate the different layers of the conductive lines 212, as discussed below with respect to the redistribution structure 306.

Fig. 15 illustrates a second substrate core 210 formed over substrate core 110 and conductive line 113 according to some embodiments. After forming the conductive vias 116, the conductive lines 113, and the reinforcing structures 120 of fig. 5, the second substrate core 210 may be laminated to the first substrate core 110 and the conductive lines 113. Second substrate core 210 and wires 212 may be formed in a manner similar to that discussed for second substrate core 210 of fig. 14. As shown in fig. 15, in some embodiments, after the reinforcement structure 120 has been placed in the substrate core 110, the substrate core 210 may be formed over the substrate core 110, but without the reinforcement structure.

Fig. 16 illustrates a second substrate core 210 formed over substrate core 110 and conductive lines 113 according to some embodiments. After forming the conductive vias 116, the conductive lines 113, and the reinforcing structures 120 of fig. 5, the second substrate core 210 may be laminated to the first substrate core 110 and the conductive lines 113. In some embodiments, reinforcing structure 220 may be formed within second substrate core 210. In some embodiments, some or all of the reinforcement structures 220 may be aligned with respective reinforcement structures 120, while in other embodiments none of the reinforcement structures 220 are aligned with a reinforcement structure 120. In some embodiments, reinforcing structure 220 may include irregularly shaped reinforcing structures similar to reinforcing structure 122 discussed above. Reinforcing structure 220 may be formed using processes and materials similar to those discussed above in the formation of reinforcing structures 120 and/or 122 and will not be repeated.

Fig. 17 to 21 show respective intermediate processes for completing the interposer substrate 200. Although fig. 17-21 are illustrated based on interposer substrate 200 as shown in fig. 14, it should be understood that these processes may be applied to embodiments of interposer substrate 200 that are also consistent with those shown in fig. 15 and 16.

Fig. 17 shows the interposer substrate of fig. 14 after forming a recess 250 in second substrate core 210 to expose a recessed bond pad 113p corresponding to a portion of wire 113. In some embodiments, the groove 250 is formed by laser drilling. Other processes, such as mechanical drilling with a drill bit, may also be used to form the grooves 250. Any other suitable process may be used to form the groove 250. The groove 250 may have any top view shape, such as polygonal, circular, and the like. A cleaning process may then be performed to clean the area near the groove 250, which area isMay have been contaminated by the removed material of substrate core 210. The groove 250 may have a width W between about 70 μm and about 350 μm₄Such as about 210 μm, although other values are contemplated and may be used. In some embodiments, the grooves 250 may be formed in a regular pattern having a pitch P of between 70 μm and about 400 μm₄Such as about 260 μm, although other values are contemplated and may be used. In some embodiments, the width W at the top of the groove 250₄May be wider than the width W of the bottom of the groove 250₅The groove 250 has a tapered shape. Width W₅May be between about 55 μm and about 320 μm, such as about 180 μm. The recesses 250 can have a height H between about 20 μm and about 300 μm₄Such as about 30 μm, although other values are contemplated and may be used.

In fig. 18, the carrier substrate 102 is removed. The carrier substrate 102 may be detached (or "debonded") from the substrate core 110. In some embodiments, debonding includes projecting light, such as laser or UV light, onto the release layer 104 such that the release layer 104 decomposes under the heat of the light and the carrier substrate 102 may be removed. In some embodiments, additional substrate core layers may be added in a manner similar to that discussed above with respect to substrate core 210, with the conductive lines, vias, and reinforcing structures disposed therein in a manner consistent with that discussed above, and the topmost substrate core having a groove 250 formed therein.

In fig. 19, the solder resist layer 124 is formed on the

conductive lines

106 and 212 on opposite sides of the substrate core 110 and the substrate core 210. The solder resist layer 124 protects the substrate core 110 and areas of the substrate core 210 from external damage. The solder mask layer 124 may be formed using processes and materials similar to those discussed above with respect to fig. 6 and will not be repeated. Openings may be made in the solder resist layer 124 in a similar manner as described above. Thickness T of each solder resist layer₄May be between about 5 μm and about 50 μm, such as about 25 μm, although other thicknesses are also contemplated. Total thickness T of interposer substrate 200₅May be between about 30 μm and about 1500 μm, such as about 200 μm, although other thicknesses are contemplated.

In fig. 20, an optional metal pad 260 may be formed, wherein metal pad 260 lines recess 250 of second substrate core 210 to provide under bump metallization. In some embodiments, the metal pad 260 may be formed while the carrier substrate 102 is still attached and before the solder resist layer 124 is formed, e.g., after the groove 250 in fig. 17 is formed. In other embodiments, the metal pad 260 may be formed after the formation of the solder resist layer 124. The metal liner 260 may be one or more layers of copper, titanium, nickel, aluminum, combinations thereof, and the like, and may be formed using any suitable process, such as by metal foil lamination, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and the like. It should be understood that metal liner 260 is optional even though metal liner 260 is depicted in the figures discussed below that include interposer substrate 200.

In some embodiments, to form metal liner 260, a seed layer (not shown) may first be formed over substrate core 210. Next, a photoresist (not shown) is formed over the seed layer and patterned to expose the grooves 250. Then, a metal pad 260 may be formed in the groove 250. After the metal liner 260 is formed, the photoresist may be removed, for example by ashing, and the now exposed portions of the seed layer may be removed, such as by wet or dry etching.

In other embodiments, to form metal liner 260, a metal layer may be formed over substrate core 210 and a photoresist (not shown) deposited over the metal layer. The photoresist may be patterned to expose portions of the metal layer that are not to be maintained, and those portions may be removed, such as by wet or dry etching. The photoresist may be removed, such as by ashing, and the remaining portion of the metal layer may become the metal pad 260.

In fig. 21, a conductive connection 126 is formed in an opening in the solder resist layer 124. The conductive connection 126 may be formed using processes and materials similar to any of the processes and materials discussed above with respect to the conductive connection 126 of fig. 7.

Fig. 22-25 illustrate an interposer substrate 200 having a cavity 230 (fig. 22-24) or through via 240 (fig. 25) disposed therein, according to some embodiments. Air conditionerThe cavity 230 or the through via 240 may be formed using any of the processes discussed above with respect to the cavity 130 and the through via 140 and will not be repeated. The cavity 230 may have a height H between about 20 μm and about 1470 μm₂Other heights are contemplated and may be used. FIG. 22 illustrates an embodiment in which the cavity 230 is formed such that the height H of the removed portion₂Corresponding to the thickness of the substrate core 110. FIG. 23 illustrates an embodiment in which the cavity 230 is formed such that the height H of the removed portion₂Less than the thickness of the substrate core 110. FIG. 24 illustrates an embodiment in which the cavity 230 is formed such that the height H of the removed portion₂Greater than the thickness of the substrate core 110 and extending to, but not through, the second substrate core 210. Fig. 25 illustrates an embodiment in which the through-hole 240 extends completely through the substrate core 110 and the second substrate core 210.

Fig. 26 shows interposer substrate 200 with reinforcing

structures

120 and 220 disposed therein, which may follow an intermediate process such as that shown in fig. 16. It should be understood that the reinforcing structure 220 is optional, such as discussed above.

Fig. 27-30 illustrate an interposer substrate 200 having a cavity 230 (fig. 27-29) or through via 240 (fig. 30) disposed therein, according to some embodiments. The cavity 230 or the through vias 240 may be formed using any of the processes discussed above with respect to the cavity 130 and the through vias 140 and will not be repeated. The embodiments shown in fig. 27-30 have reinforcing structures 120 (and/or reinforcing structures 122) and/or reinforcing structures 220 disposed within their respective substrate cores.

FIG. 27 shows an embodiment where the cavity 230 is formed such that the height H of the removed portion₂Corresponding to the thickness of the substrate core 110. The reinforcing structure 120 may be disposed in a peripheral portion of the substrate core 110, and the reinforcing structure 220 may be disposed in a portion of the second substrate core 210 aligned with the cavity 230 and/or in a peripheral portion of the second substrate core 210 surrounding the cavity 230.

FIG. 28 illustrates one embodiment, where cavity 230 is formed such that the height H of the removed portion₂Smaller than the substrate core 110, in thickness. The reinforcement structure 120 may be disposed in an outer peripheral portion of the substrate core 110 and/or in a portion of the substrate core 110 aligned with the cavity 230, and the portion is thinned by a process of forming the cavity 230. The reinforcing structure 220 may be disposed in a portion of the second substrate core 210 aligned with the cavity 230 and/or in a peripheral portion of the second substrate core 210 surrounding the cavity 230.

FIG. 29 shows an embodiment in which the cavity 230 is formed such that the height H of the removed portion₂Greater than the thickness of the substrate core 110 and extends to the second substrate core 210, but does not pass all the way through the second substrate core 210. The reinforcing structure 120 may be disposed in an outer peripheral portion of the substrate core 110. The reinforcing structure 220 may be disposed in a peripheral portion of the second substrate core 210 surrounding the cavity 230 and/or may be disposed in a portion of the second substrate core that is aligned with the cavity 230 and may be thinned by a process of forming the cavity 230.

Fig. 30 illustrates an embodiment in which the through-hole 240 extends completely through the substrate core 110 and the second substrate core 210. The reinforcement structure 120 may be disposed in an outer peripheral portion of the substrate core 110, and the reinforcement structure 220 may be disposed in an outer peripheral portion of the second substrate core 210.

Fig. 31-79 illustrate cross-sectional views of intermediate steps of a process for packaging the interposer substrate 100 or interposer substrate 200 with other devices to form various package assemblies, in accordance with some embodiments. The package assembly may include a plurality of regions, and one

interposer substrate

100 or 200 is packaged in each region. One area of a package assembly is shown.

Fig. 31-42 illustrate cross-sectional views of intermediate steps of a process for forming a bottom fan-out package 300, according to some embodiments. The formation of the bottom fan-out package 300 may be used in any of the embodiments discussed below. In fig. 31, a carrier substrate 302 is provided, and a release layer 304 is formed on the carrier substrate 302. The carrier substrate 302 may be similar to any candidate of the carrier substrate 102, and the release layer 304 may be similar to any candidate of the release layer 104, each discussed above with reference to fig. 1. The top surface of the release layer 304 may be horizontal and may have a high degree of coplanarity.

In fig. 32, a first redistribution structure 306 is formed on the release layer 304. The first redistribution structure 306 includes

dielectric layers

308, 312, 316, and 320;

metallization patterns

310, 314, and 318. The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The first redistribution structure 306 is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the first redistribution structure 306. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

As an example of forming the first redistribution structure 306, a dielectric layer 308 is deposited on the release layer 304. In some embodiments, the dielectric layer 308 is formed of a photosensitive material, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like, which can be patterned using a photolithographic mask. The dielectric layer 308 may be formed by spin coating, lamination, CVD, the like, or combinations thereof. The dielectric layer 308 is then patterned. The patterning forms openings that expose portions of the release layer 304. The patterning may be by an acceptable process, such as by exposing the dielectric layer 308 to light when the dielectric layer 308 is a photosensitive material or by etching using, for example, anisotropic etching. If the dielectric layer 308 is a photosensitive material, the dielectric layer 308 can be developed after exposure.

A metallization pattern 310 is then formed. Metallization pattern 310 includes conductive lines that are located on and extend along a major surface of dielectric layer 308. Metallization pattern 310 also includes conductive vias that extend through dielectric layer 308. To form the metallization pattern 310, a seed layer is formed over the dielectric layer 308 and in the openings extending through the dielectric layer 308. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 310. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and the underlying portions of the seed layer form a metallization pattern 310. Portions of the photoresist and seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

A dielectric layer 312 is deposited over the metallization pattern 310 and the dielectric layer 308. The dielectric layer 312 may be formed in a similar manner as the dielectric layer 308 and may be formed of the same material as the dielectric layer 308.

A metallization pattern 314 is then formed. Metallization pattern 314 includes conductive lines that are located on and extend along a major surface of dielectric layer 312. Metallization pattern 314 also includes conductive vias that extend through dielectric layer 312 to physically and electrically connect to metallization pattern 310. Metallization pattern 314 may be formed in a similar manner as metallization pattern 310 and may be formed of the same material as metallization pattern 310. The width of the conductive via of metallization pattern 314 is less than the width of the conductive via of metallization pattern 310. Thus, when patterned dielectric layer 312 is used to pattern metallization 314, the width of the opening in dielectric layer 312 is less than the width of the opening in dielectric layer 308.

A dielectric layer 316 is deposited over metallization pattern 314 and dielectric layer 312. The dielectric layer 316 may be formed in a similar manner as the dielectric layer 308 and may be formed of the same material as the dielectric layer 308.

A metallization pattern 318 is then formed. Metallization pattern 318 includes conductive lines that are located on and extend along a major surface of dielectric layer 316. Metallization pattern 318 also includes conductive vias that extend through dielectric layer 316 to physically and electrically connect to metallization pattern 314. Metallization pattern 318 may be formed in a similar manner as metallization pattern 310 and may be formed of the same material as metallization pattern 310. The width of the conductive via of metallization pattern 318 is less than the width of the conductive via of metallization pattern 310. Thus, when the patterned dielectric layer 316 is used to pattern metallization 318, the width of the opening in the dielectric layer 316 is less than the width of the opening in the dielectric layer 308.

A dielectric layer 320 is deposited over metallization pattern 318 and dielectric layer 316. The dielectric layer 320 may be formed in a similar manner as the dielectric layer 308 and may be formed of the same material as the dielectric layer 308.

In fig. 33, UBM 322 is formed on dielectric layer 320 and extends through dielectric layer 320. As an example of forming UBM 322, dielectric layer 320 may be patterned to form an opening that exposes a portion of metallization pattern 318. The dielectric layer 320 may be formed by an acceptable process, such as by exposing the dielectric layer 320 to light when the dielectric layer 320 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 320 is a photosensitive material, the dielectric layer 320 can be developed after exposure. In some embodiments, the opening for UBM 322 may be wider than the openings for the conductive via portions of

metallization patterns

310, 314, and 318. In some embodiments, the opening of UBM 322 may be narrower than the opening for the conductive via portions of

metallization patterns

310, 314, and 318 or have the same width as the width of the opening for the conductive via portions of

metallization patterns

310, 314, and 318. A seed layer is formed on the dielectric layer 320 and in the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to UBM 322. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, nickel, titanium, tungsten, aluminum, and the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portion of the seed layer and the conductive material form a UBM 322. In embodiments where UBM 322 is formed differently, more photoresist and patterning steps may be used.

UBMs 322 may not all have the same width. In some embodiments, a first subset of UBMs 322 in first region 306A of first redistribution structure 306 has a first width W₆And a second subset of UBMs 322 in a second region 306B of the first redistribution structure 306 has a second width W₇. First width W₆May correspond to the second width W₇Differently, and in some embodiments, the first width W₆Is greater than the second width W₇. Width W₆May be between about 100 μm and about 250 μm, such as about 170 μm, although other values are contemplated and may be used. Width W₇May be between about 30 μm and about 70 μm, such as about 48 μm, although other values are contemplated and may be used.

In fig. 34, some or all of UBMs 322 of first region 306A may instead be formed as conductive pillars 322p, according to some embodiments. The UBM 322 of the first region 306A may continue to be plated through the photoresist until the conductive pillar 322p reaches the desired height H₈Conductive post 322p is formed, such as between about 10 μm and about 150 μm, such as about 60 μm, although other values are contemplated and may be used. In some embodiments, the width W of the conductive post₈May correspond to an opening in dielectric layer 320 where dielectric layer 320 is patterned to expose a portion of metallization pattern 318. In some embodiments, the width W₈May be wider or narrower than the opening in the dielectric layer 320. Width W₈Can be between about 80 μm and about 230 μm, such as about150 μm, but other values are contemplated and may be used.

In fig. 35, some or all of the UBMs 322 of the first region 306A may have conductive pillars 322p disposed thereon, according to some embodiments. After forming the UBM 322, another photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the pattern of the conductive pillars 322 p. The patterning forms an opening in the photoresist to expose UBM 322. The conductive material of the conductive post 322p can be formed by plating, such as electroplating or electroless plating, until the conductive post 322p reaches the desired height H₉Such as between about 10 μm and about 150 μm, such as about 60 μm, although other values are contemplated and may be used. Width W of conductive post₉Corresponding to the width of the opening of the pattern of the photoresist. Width W₉May be between about 80 μm and about 230 μm, such as about 150 μm, although other values are contemplated and may be used. The conductive material may include metals such as copper, titanium, tungsten, aluminum, and the like. The photoresist may then be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. The resulting structure may have a shoulder 322s of UBM 322 surrounding the base of conductive post 322 p.

While the remaining figures show conductive pillars 322p configured as described with respect to fig. 35, it should be understood that conductive pillars 322p configured as described with respect to fig. 34 may be substituted (i.e., without UBM 322) if appropriate unless otherwise noted.

Fig. 36-45 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer, according to some embodiments. In fig. 36, an integrated circuit die 324 is placed over the first redistribution structure 306. The integrated circuit die 324 may be a logic die (e.g., a central processing unit, a microcontroller, etc.), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof (e.g., a system on a chip (SoC)).

Integrated circuit die 324 includes a semiconductor substrate in and/or on which devices such as transistors, diodes, capacitors, resistors, and the like are formed. The devices may be interconnected by an interconnect structure formed by, for example, a metallization pattern in one or more dielectric layers on a semiconductor substrate to form an integrated circuit. Integrated circuit die 324 also includes a pad 326, such as an aluminum pad, with external connections formed on pad 326. Pads 326 are located on what may be referred to as the corresponding active side of integrated circuit die 324 and may be located in the uppermost layer of the interconnect structure. Because the active side of the integrated circuit die 324 faces the first redistribution structure 306, the first redistribution structure 306 may also be referred to as a front-side redistribution structure. And because the active side of the integrated circuit die 324 faces down to the first redistribution structure 306, the resulting package may be referred to as a bottom fan-out package. Conductive connections 328 may be formed on the pads 326. The conductive connection 328 may be formed of a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connection 328 is a solder connection.

The integrated circuit die 324 may be aligned and placed using, for example, a pick and place tool. The integrated circuit die 324 is placed on the redistribution structure 306 such that the conductive connections 328 are aligned with the UBM 322 in the second region 306B. After placing the integrated circuit die 324, the conductive connections 328 are reflowed to form joints between the corresponding UBM 322 and the pads 326, physically and electrically connecting the integrated circuit die 324 to the first redistribution structure 306.

An underfill 330 may be formed between the integrated circuit die 324 and the first redistribution structure 306, surrounding the conductive connections 328. In this way, the conductive connection 328 may be protected from mechanical forces. The underfill 330 may be formed by a capillary flow process after the integrated circuit die 324 is attached, or may be formed by a suitable deposition method before the integrated circuit die 324 is attached.

In fig. 37, the interposer substrate 100 (see, e.g., fig. 7) is aligned with the conductive posts 322p to couple the conductive connections 126 to the respective conductive posts 322p, according to some embodiments. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. Interposer substrate 100 is placed over redistribution structure 306 such that conductive connections 126 are aligned with UBM 322 and/or conductive pillars 322p in first region 306A.

In fig. 38, after placement of the interposer substrate 100, the conductive connections 126 are reflowed to form contacts between the respective conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. Encapsulant 334 is formed over the various components. Encapsulant 334 may be a molding compound, epoxy, etc., and may be applied by compression molding, transfer molding, etc. An encapsulant 334 may be formed over the first redistribution structure 306 so as to bury or cover the integrated circuit die 324 and fill the space between the interposer substrate 100 and the redistribution structure 306. The encapsulant 334 is then cured. In some embodiments, an encapsulant 334 is also formed between the first redistribution structure 306 and the integrated circuit die 324, for example, in embodiments where the underfill 330 is omitted.

In some embodiments, such as shown in fig. 39, the conductive connections 126 may be reflowed to form around the conductive posts 322 p. After placement of the integrated circuit die 324, the conductive connections 126 are reflowed to form joints between the respective conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. In such embodiments, the conductive connection 126 may be formed with an amount of material such that the material extends down the entire length of the conductive post 322p and contacts a portion of the shoulder 322s of the UBM 322, thereby embedding the conductive post 322p in the material of the conductive connection 126. The shoulder 322s portion of UBM 322 may also be referred to as a "step". The box drawn with the dotted line is enlarged in fig. 40.

In fig. 40, an enlarged view of the connector of fig. 39 is provided, according to some embodiments. As shown in fig. 39, after reflow, the material of the conductive connection 126 extends down the conductive post 322p, covering the top and sidewalls of the conductive post 322 p. Conducting electricityThe material of connection 126 extends to a shoulder 322s of UBM 322, shoulder 322s surrounding conductive post 322 p. The material of conductive connection 126 is formed within the lateral extent of UBM 322. When reflowing the material of the conductive connection 126, the conductive posts 322p act as a template for the flow of material, forming a substantially uniform layer of material on the sidewalls of the conductive posts 322 p. The shoulder 322s or step of the UBM 322 acts as a template to define the limits of the outer width of the reflowed conductive connection 126. The conductive post 322p has a width D that may be between about 80 μm and about 230 μm₁And a height D that may be between about 10 μm and about 150 μm₂. The conductive connection 126 may have a width D surrounding the conductive post 322p₃Width D₃Between about 100 μm and about 250 μm, wherein D₃Greater than D₁. In some embodiments, the width D over the conductive post 322p₄May be equal to the width D surrounding the conductive post 322p₃Producing a ratio D equal to 1₄/D₃. In some embodiments, D₄May be less than or greater than D₃Wherein D is₄/D₃Is between about 0.8 and about 1.4. Height D of conductive connection 126 after reflow₅Corresponding to the spacing between the substrate core 110 and the redistribution structure 306 of the interposer substrate 100 and may be between about 80 μm and about 180 μm. It should be understood that these dimensions are examples and that other dimensions may be used as appropriate.

Because the conductive posts 322p are encapsulated by the material of the conductive connections 126, strong joints are formed that can better withstand the warpage stresses caused by CTE mismatches between differently formed structures, such as interposer substrate 100 and redistribution structure 306. Resistance to buckling stress may reduce joint failure and reduce buckling. The process of forming a joint between the conductive post 322p and the conductive connection 126 also has the advantage of reducing the risk of bridging to other connections, since the conductive post 322p and shoulder 322s act as a template for controlling reflow. Although fine pitch joints can be achieved, the process still achieves good self-alignment. Robust joints provide high engagement rates and joint reliability. Also, the process provides a controllable joint gap using the conductive post 322 p.

In fig. 41, the carrier substrate 302 is removed. The carrier substrate 302 may be separated (or "debonded") from the redistribution structure 306. In some embodiments, debonding includes projecting light, such as laser or UV light, onto the release layer 304 such that the release layer 304 decomposes under the heat of the light and the carrier substrate 302 may be removed. The structure was then inverted and placed on tape. The debonding exposes the metallization pattern 310 of the redistribution structure 306.

In fig. 42, conductive connections 352 are formed over the redistribution structure 306. Conductive connection 352 contacts the exposed portion of metallization pattern 310. In some embodiments, a passivation layer may be used over metallization pattern 310 and patterned to expose portions of metallization pattern 310 prior to forming conductive connections 352. In some embodiments, a UBM may be formed over the exposed portions of metallization pattern 310. In such embodiments, the UBM may be formed using similar processes and materials as UBM 322. The conductive connections 352 may be Ball Grid Array (BGA) connections, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), or the like. The conductive connection 352 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, conductive connection 352 is a solder connection that is formed by initially forming a solder layer by conventional methods such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once a layer of solder is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 352 includes a metal pillar, such as a copper pillar, formed by printing, electroplating, electroless plating, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. After the conductive connection 352 is formed, the structure may be flipped over and placed on tape or secured by the conductive connection 352. In some embodiments, after forming the conductive connections 352, the package 300 may be singulated directly on a tape into dies (not shown).

In fig. 43, the device 500 may be mounted to an interposer substrate 100 to form a 3D package 600. Device 500 may include an integrated circuit die or another interposer. The device 500 may include an optional redistribution structure 506 and a device substrate 510. The redistribution structure 506 may be formed using processes and materials similar to those discussed above with respect to the redistribution structure 306. The device substrate 510 may include an integrated circuit die including an antenna, a memory die, an RF die, a passive device, combinations thereof, or the like. An integrated circuit die may include a semiconductor substrate in and/or on which devices such as transistors, diodes, capacitors, resistors, and the like are formed. The devices may be interconnected by an interconnect structure formed by, for example, a metallization pattern in one or more dielectric layers on a semiconductor substrate to form an integrated circuit. The device 500 may include conductive connections 536 formed on the redistribution structure 506. The conductive connection 536 may be formed of a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. The device 500 may be mounted to the interposer substrate 100 by coupling the conductive connections 536 to the portions of the leads 113 exposed through the solder resist layer 124. In some embodiments, conductive connections 536 are reflowed to attach the device 500 to the wires 113.

In fig. 44, package 600 (see, e.g., fig. 43) may be mounted to package substrate 650 using conductive connectors 352 to form 3D package 700. The package substrate 650 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. In addition, the package substrate 650 may be a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, Silicon Germanium On Insulator (SGOI), or combinations thereof. In an alternative embodiment, the package substrate 650 is based on an insulating core, such as a fiberglass reinforced resin core. One example core material is a fiberglass resin, such as FR 4. Alternatives to the core material include Bismaleimide Triazine (BT) resins, or alternatively, other PCB materials or films. A laminate film such as an ajinomoto laminate film (ABF), a multi-layer core (MLC) substrate, or other laminate may be used for the package substrate 650.

The package substrate 650 may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices, such as transistors, capacitors, resistors, combinations of these, and the like, may be used to create the structural and functional requirements of the design of the package substrate 650. Any suitable method may be used to form the device.

Package substrate 650 may also include metallization layers and vias (not shown) and bond pads 664 located over the metallization layers and vias. Metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating dielectric layers (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein vias interconnect the conductive material layers and may be formed by any suitable process, such as deposition, damascene, dual damascene, and the like. In some embodiments, the package substrate 650 is substantially free of active and passive devices.

In some embodiments, the conductive connectors 352 are reflowed to attach the package 600 (fig. 43) to the bond pads 664 of the package substrate 650. The conductive connectors 352 electrically and/or physically couple the package substrate 650 (including metallization layers in the package substrate 650) to the redistribution structure 306 of the package 300. In some embodiments, a passive device (e.g., a Surface Mount Device (SMD), not shown) may be attached to the package 300 (e.g., bonded to a surface of the redistribution structure 306) prior to mounting on the package substrate 650. In such embodiments, the passive devices may be bonded to the same surface of the package 300 as the conductive connectors 352.

In some embodiments, an underfill (not shown) may be formed between the package 300 and the package substrate 650 and around the conductive connectors 352. The underfill may be formed by a capillary flow process after the package 600 (fig. 43) is attached, or may be formed by a suitable deposition method before the package 600 is attached.

Other components and processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate, allowing testing of 3D packages or the use of 3DIC, probes, and/or probe cards, and the like. Verification tests may be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

Fig. 45 shows a package 700 that is similar to the package 700 of fig. 44, except that the package 300 is formed as discussed above with respect to fig. 39, i.e., with the conductive connections 126 extending down the conductive posts 322p and contacting the shoulders 322 s.

Fig. 46-47 illustrate views of a package including a fan-out bottom package and a second device attached together without an interposer, but using connectors around metal posts, according to some embodiments. Fig. 46 shows a package 700', the package 700' being similar to the package 700 of fig. 45, except that the interposer substrate 100 is not included. As described above, one of the purposes of interposer substrate 100 may be to provide support to reduce warpage and reduce the likelihood of faulty connections between packages. Conductive connections 126 (such as discussed above with respect to fig. 39 and 40) provide a secure connection such that, in some embodiments, interposer substrate 100 may be omitted. In such embodiments, the device 500 may be mounted to the conductive pillars 322p in a manner similar to the mounting of interposer substrate 100 to the conductive pillars 322p discussed above with reference to fig. 39 and 40.

Fig. 47 shows a package 700 'that is similar to the package 700' of fig. 46, except that an adhesive layer 332 may be used between the device 500 and the integrated circuit die 324. Adhesive layer 332 may be any suitable adhesive, epoxy, underfill, Die Attach Film (DAF), thermal interface material, or the like. For each integrated circuit die 324, an adhesive layer 332 may be applied to the back side of the integrated circuit die 324, or may be applied to the die attach area of the device 500. For example, adhesive layer 332 may be applied to the back side of integrated circuit die 324 prior to singulation to separate integrated circuit die 324, or adhesive layer 332 may be applied to the front side of device 500 prior to singulation to separate device 500. In some embodiments, the adhesive layer 332 may be added to the integrated circuit die 324 or the device 500 in a separate process prior to bonding the device 500 to the conductive pillars 322 p.

Fig. 48-79 illustrate an embodiment that is a variation of the previously discussed embodiments, incorporating different and/or additional components. Fig. 48-50 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer with an adhesive formed therebetween, in accordance with some embodiments. Fig. 48 shows an embodiment as discussed above with respect to fig. 37. In fig. 48, an adhesive layer 332 may be disposed on the interposer substrate 100 and/or the integrated circuit die 324 prior to connecting the interposer substrate 100 to the conductive pillars 322 p. Adhesive layer 332 may be any suitable adhesive, epoxy, underfill, Die Attach Film (DAF), thermal interface material, or the like. For each integrated circuit die 324, an adhesive layer 332 may be applied to the back side of the integrated circuit die 324, or may be applied to the die attach area of the interposer substrate 100. For example, the adhesive layer 332 may be applied to the back side of the integrated circuit die 324 prior to singulation to separate the integrated circuit die 324, or the adhesive layer 332 may be applied to the front side of the interposer substrate 100 prior to singulation to separate the interposer substrate 100.

In fig. 48, interposer substrate 100 is aligned with conductive pillars 322p, according to some embodiments. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. Interposer substrate 100 is placed over redistribution structure 306 such that conductive connections 126 are aligned with UBM 322 and/or conductive pillars 322p in first region 306A.

In fig. 49, after placing the interposer substrate 100, the conductive connections 126 are reflowed to form contacts between the respective conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. Encapsulant 334 may be formed, such as discussed above with respect to fig. 38.

In fig. 50, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 100, such as discussed above with respect to fig. 43, to form a package 600. The package 600 may be mounted to a package substrate 650, such as discussed above with reference to fig. 44.

Fig. 51 shows an embodiment as discussed above with respect to fig. 36. After the integrated circuit die 324 is mounted, an encapsulant 334 may be formed over the redistribution structure 306 to laterally surround the integrated circuit die 324 and the conductive posts 322 p. In some embodiments, the encapsulant 334 may also extend over the top surfaces of the integrated circuit die 324 and/or the conductive pillars 322 p. The upper portion of the encapsulant 334 may then be removed by a removal process to make the top surfaces of the conductive posts 322p flush with each other. In some embodiments, the top surfaces of the conductive pillars 322p may also be made flush with the top surface of the integrated circuit die 324 by a removal process. The removal process may be, for example, a CMP and/or etch back process. Encapsulant 334 may be formed using processes and materials similar to those discussed above with respect to fig. 38.

In fig. 52, an adhesive layer 332 may be disposed on the interposer substrate 100 and/or the integrated circuit die 324 prior to connecting the interposer substrate 100 to the conductive pillars 322 p. Adhesive layer 332 may be similar to adhesive layer 332 of fig. 48. Interposer substrate 100 is aligned with conductive pillars 322 p. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 100 is placed on the encapsulant 334 such that the conductive connections 126 are aligned with the conductive posts 322p in the first region 306A.

In fig. 53, after placing the interposer substrate 100, the conductive connections 126 are reflowed to form contacts between the respective conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. An adhesive layer 332 may be interposed between the interposer substrate 100 and the integrated circuit die 324 such that the adhesive layer 332 contacts the interposer substrate 100 and the integrated circuit die 324.

In fig. 54, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 100, such as discussed above with respect to fig. 43, to form a package 600. The package 600 may be mounted to a package substrate 650, such as discussed above with reference to fig. 44.

Fig. 55-70 illustrate various intermediate steps in a process of forming a package structure including a fan-out bottom package and an interposer with a cavity or through via formed therein, according to some embodiments. In fig. 55, an interposer substrate 100 is provided having a cavity 124c formed in a solder resist layer 124. The cavity 124c may be formed in a manner similar to the formation of the cavity 130 discussed above with reference to fig. 11. The cavity 124c may be formed such that the reinforcing structure 120 and/or the reinforcing structure 122 are closer to the integrated circuit die 324 once the interposer substrate 100 is mounted to the conductive pillars 322p and/or the UBM 322. In some embodiments, cavity 124c may be sized and positioned to allow integrated circuit die 324 to be recessed into cavity 124c when mounted. This may help to reduce the overall height of the completed package, as well as provide better heat dissipation from integrated circuit die 324 to enhancement structure 120 and/or enhancement structure 122.

According to some embodiments, interposer substrate 100 is aligned with conductive pillars 322 p. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. Interposer substrate 100 is placed over redistribution structure 306 such that conductive connections 126 are aligned with UBM 322 and/or conductive pillars 322p in first region 306A.

In fig. 56, after placing the interposer substrate 100, the conductive connections 126 are reflowed to form contacts between the respective conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. Encapsulant 334 may be formed, such as discussed above with respect to fig. 38. In some embodiments, encapsulant 334 may flow into the space between integrated circuit die 324 and interposer substrate 100 such that encapsulant 334 is disposed between the top surface of integrated circuit die 324 and the bottom of substrate core 110 of interposer substrate 100.

In fig. 57, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 100, such as discussed above with respect to fig. 43, to form a package 600. The package 600 may be mounted to a package substrate 650, such as discussed above with reference to fig. 44.

In fig. 58, an interposer substrate 100 is provided having an opening 124o formed in a solder resist layer 124, such as discussed above with respect to fig. 55. An adhesive layer 332 may be disposed on the interposer substrate 100 and/or the integrated circuit die 324 prior to connecting the interposer substrate 100 to the conductive pillars 322 p. Adhesive layer 332 may be similar to adhesive layer 332 of fig. 48. Interposer substrate 100 is aligned with conductive pillars 322 p. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 100 is placed over the redistribution structure 306 such that the conductive connections 126 are aligned with the conductive posts 322p in the first region 306A.

In fig. 59, after placing the interposer substrate 100, the conductive connections 126 are reflowed to form contacts between the corresponding conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. An adhesive layer 332 may be interposed between the interposer substrate 100 and the integrated circuit die 324 such that the adhesive layer 332 contacts the interposer substrate 100 and the integrated circuit die 324.

In fig. 60, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 100, such as discussed above with respect to fig. 43, to form a package 600. The package 600 may be mounted to a package substrate 650, such as discussed above with reference to fig. 44.

In fig. 61, an interposer substrate 100 is provided having a cavity 130 formed in a substrate core 110 (see fig. 11). The cavity 130 may be formed such that it is aligned with the integrated circuit die 324 such that the integrated circuit die 324 is at least partially disposed within the cavity 130 once the interposer substrate 100 is mounted to the conductive pillars 322p and/or the UBM 322. This may help to reduce the overall height of the completed package. Reinforcing structure 120 and/or reinforcing structure 122 may also provide support and heat dissipation for integrated circuit die 324.

According to some embodiments, interposer substrate 100 is aligned with conductive pillars 322 p. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 100 is placed over the redistribution structure 306 such that the conductive connections 126 are aligned with the conductive posts 322p in the first region 306A.

In fig. 62, after placement of the interposer substrate 100, the conductive connections 126 are reflowed to form contacts between the respective conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. Encapsulant 334 may be formed, such as discussed above with respect to fig. 38. In some embodiments, the encapsulant 334 may flow to the space between the integrated circuit die 324 and the interposer substrate 100 such that the encapsulant 334 is disposed between the top surface of the integrated circuit die 324 in the cavity 130 and the bottom of the substrate core 110 of the interposer substrate 100.

In some embodiments, the integrated circuit die 324 may be at least partially disposed in the cavity 130 (see fig. 61) after the interposer substrate 100 is connected to the conductive pillars 322 p.

In fig. 63, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 100, such as discussed above with respect to fig. 43, to form a package 600. The package 600 may be mounted to a package substrate 650, such as discussed above with reference to fig. 44.

In fig. 64, an interposer substrate 100 is provided having a cavity 130 formed therein, such as discussed above with respect to fig. 61. An adhesive layer 332 may be disposed on the interposer substrate 100 and/or the integrated circuit die 324 prior to connecting the interposer substrate 100 to the conductive pillars 322 p. Adhesive layer 332 may be similar to adhesive layer 332 of fig. 48. Interposer substrate 100 is aligned with conductive pillars 322 p. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 100 is placed over the redistribution structure 306 such that the conductive connections 126 are aligned with the conductive posts 322p in the first region 306A.

In fig. 65, after placing the interposer substrate 100, the conductive connections 126 are reflowed to form contacts between the corresponding conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. An adhesive layer 332 may be interposed between the interposer substrate 100 and the integrated circuit die 324 such that the adhesive layer 332 contacts the interposer substrate 100 and the integrated circuit die 324.

In some embodiments, the integrated circuit die 324 may be at least partially disposed in the cavity 130 after the interposer substrate 100 is connected to the conductive pillars 322p (see fig. 64).

In fig. 66, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 100, such as discussed above with respect to fig. 43, to form a package 600. The package 600 may be mounted to a package substrate 650, such as discussed above with reference to fig. 44, to form a package 700.

In fig. 67, an interposer substrate 100 is provided having through vias 140 formed in a substrate core 110 (see fig. 12). Through vias 140 may be formed such that they are aligned with integrated circuit die 324 such that integrated circuit die 324 is at least partially disposed within through vias 140 once interposer substrate 100 is mounted to conductive pillars 322p and/or UBM 322. In some embodiments, the integrated circuit die 324 may be mounted in the through vias 140 such that the top surface of the integrated circuit die 324 is flush with or lower than the top surface of the interposer substrate 100. This may reduce the overall height of the completed package. Reinforcing structures 120 and/or reinforcing structures 122 may be disposed in a peripheral portion of interposer substrate 100.

According to some embodiments, interposer substrate 100 is aligned with conductive pillars 322p or UBM 322. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 100 is placed over the redistribution structure 306 such that the conductive connections 126 are aligned with the conductive posts 322p or UBM 322 in the first region 306A.

In fig. 68, after placing the interposer substrate 100, the conductive connections 126 are reflowed to form contacts between the corresponding conductive pillars 322p or UBM 322 and the conductive lines 106, physically and electrically connecting the interposer substrate 100 to the first redistribution structure 306. Encapsulant 334 may be formed, such as discussed above with respect to fig. 38. In some embodiments, encapsulant 334 may flow around integrated circuit die 324 and interposer substrate 100 such that encapsulant 334 is interposed between the sides of integrated circuit die 324 and the sidewalls of through vias 140 of interposer substrate 100. The encapsulant 334 may also flow over the top surface of the interposer. A removal process, such as a CMP and/or etch-back process, may be used to make the top surface of the encapsulant 334 flush with the top surface of the interposer substrate 100 and/or the integrated circuit die 324.

In some embodiments, integrated circuit die 324 may be at least partially disposed in through vias 140 after connecting interposer substrate 100 to conductive pillars 322p or UBM 322 (see fig. 67).

In fig. 69, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 100, such as discussed above with respect to fig. 43, to form a package 600. The package 600 may be mounted to a package substrate 650, such as discussed above with reference to fig. 44, to form a package 700.

In fig. 70, an adhesive layer 332 may be disposed on the device 500 and/or the integrated circuit die 324 prior to connecting the interposer substrate 100 to the conductive pillars 322 p. Adhesive layer 332 may be similar to layer 332 of adhesive fig. 47. Adhesive layer 332 may help provide better stability and reduce warpage due to CTE mismatch. Adhesive layer 332 may also be a thermal compound to help dissipate heat from integrated circuit die 324. The interposer substrate 100 is aligned with the conductive pillars 322p or UBM 322 in the first region 306A. The interposer substrate 100 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 100 is placed over the redistribution structure 306 such that the conductive connections 126 are aligned with the conductive posts 322p or UBM 322 in the first region 306A.

Fig. 71-79 illustrate various embodiments similar to those discussed above with reference to fig. 44-70, except that an interposer substrate 200 is used. As described above, interposer substrate 200 has at least two core substrate layers with recessed bond pads formed therein, e.g., core substrate layers such as substrate core 110 and substrate core 210 shown in fig. 71. Fig. 71 also shows that interposer substrate 200 has a recess 250 formed through top substrate core 210, recess 250 exposing the underlying recessed bond pad 113 p. The interposer substrate 200 is also shown with a metal liner 260 lining the recess 250, such as discussed above with reference to fig. 21. It should be understood that the metal pad 260 is optional even though it is shown in the figures discussed below. For example, in fig. 71, a reinforcing structure 120 and a reinforcing structure 220 are shown, which are formed in an interposer substrate 200. As discussed above with respect to fig. 17-25, any of the reinforcing

structures

120, 122, and/or 220 may optionally be omitted. It should be understood that although reinforcing

structures

120 and 220 are shown for the sake of context, embodiments are included that do not have reinforcing

structures

120, 122, and/or 220.

The recess 250 in the interposer substrate 200 reduces the overall package height when additional devices or packages are bonded to the recessed bond pads 113 p. The deep recess also provides good alignment for bonding additional devices or packages. Even without the optional reinforcing

structures

120, 122, or 220, the interposer substrate 200 still provides some structural support and helps reduce warpage.

In fig. 71, interposer substrate 200 is aligned with conductive pillars 322p, according to some embodiments. The interposer substrate 200 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 200 is placed over the redistribution structure 306 such that the conductive connections 126 are aligned with the conductive posts 322p in the first region 306A.

After placing interposer 200, conductive connections 126 are reflowed to form contacts between corresponding conductive pillars 322p and/or UBMs 322 and conductive lines 106, physically and electrically connecting interposer 200 to first redistribution structure 306. As shown in fig. 71, in some embodiments, the conductive connection 126 may extend from the interposer 200 to the UBM 322 with a conductive connection 126 a. Encapsulant 334 may be formed, such as discussed above with reference to fig. 38.

In fig. 72, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 200, such as discussed above with respect to fig. 43, to form a package 600. Package 600 may be mounted to a package substrate 650, such as discussed above with reference to fig. 44, to form package 800.

In fig. 73, an adhesive layer 332 may be disposed on the device 500 and/or the integrated circuit die 324 prior to connecting the interposer substrate 200 to the conductive pillars 322 p. Adhesive layer 332 may be similar to adhesive layer 332 of fig. 47.

In fig. 74, an interposer substrate 200 is provided in which a cavity 230 is formed (see fig. 27 to 29). The cavity 230 may be formed such that it is aligned with the integrated circuit die 324 such that the integrated circuit die 324 is at least partially disposed within the cavity 230 once the interposer substrate 200 is mounted to the conductive pillars 322 p. This helps to reduce the overall height of the finished package. The height of the cavity 230 may vary as discussed above with respect to fig. 22-24 and 27-29. Reinforcing structure 120 and/or reinforcing structure 122 and/or reinforcing structure 220 may also provide support and heat dissipation for integrated circuit die 324.

According to some embodiments, interposer substrate 200 is aligned with conductive pillars 322 p. The interposer substrate 200 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 200 is placed over the redistribution structure 306 such that the conductive connections 126 are aligned with the conductive posts 322p in the first region 306A.

After placing the interposer 200, the conductive connections 126 are reflowed to form joints between the respective conductive pillars 322p and the conductive lines 106, physically and electrically connecting the interposer 200 to the first redistribution structure 306. Encapsulant 334 may be formed, such as discussed above with respect to fig. 38. In some embodiments, encapsulant 334 may flow into the space between integrated circuit die 324 and interposer substrate 200 such that encapsulant 334 is disposed between the top surface of integrated circuit die 324 in cavity 230 and the bottom of substrate core 110 of interposer substrate 200.

In some embodiments, the integrated circuit die 324 may be at least partially disposed in the cavity 230 after the interposer substrate 200 is connected to the conductive pillars 322 p.

In fig. 75, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 200, such as discussed above with reference to fig. 43, to form a package 600. Because interposer substrate 200 has recessed bond pads 113p, device 500 is securely attached using larger conductive connections 536 relative to the absence of a recess for the bond pads. Recessed bond pads 113p may also help reduce overall package height. The package 600 may be mounted to a package substrate 650, such as discussed above with respect to fig. 44.

In fig. 76, an adhesive layer 332 may be disposed on the device 500 and/or the integrated circuit die 324 prior to connecting the interposer substrate 200 to the conductive pillars 322 p. Adhesive layer 332 may be similar to adhesive layer 332 of fig. 47.

In fig. 77, an interposer substrate 200 is provided in which a through-hole 240 is formed (see, for example, fig. 25 or fig. 30). The through vias 240 may be formed such that they are aligned with the integrated circuit die 324 such that the integrated circuit die 324 is at least partially disposed within the through vias 240 once the interposer substrate 200 is mounted to the conductive pillars 322p and/or the UBM 322. This helps to reduce the overall height of the finished package. In some embodiments, the integrated circuit die 324 may be mounted in the through vias 240 such that the top surface of the integrated circuit die 324 is flush with the top surface of the interposer substrate 200 or lower than the top surface of the interposer substrate 200. Reinforcing structure 120 and/or reinforcing structure 122 and/or reinforcing structure 220 may be disposed in a peripheral portion of interposer substrate 200 and may provide support and heat dissipation for integrated circuit die 324.

According to some embodiments, interposer substrate 200 is aligned with conductive pillars 322p and/or UBM 322. The interposer substrate 200 may be aligned and placed using, for example, a pick and place tool. The interposer substrate 200 is placed over the redistribution structure 306 such that the conductive connections 126 are aligned with the conductive posts 322p and/or UBM 322 in the first region 306A.

After placing interposer 200, conductive connections 126 are reflowed to form contacts between respective conductive pillars 322p and/or UBMs 322 and conductive lines 106, physically and electrically connecting interposer 200 to first redistribution structure 306. Encapsulant 334 may be formed, such as discussed above with respect to fig. 38. In some embodiments, encapsulant 334 may flow around and over integrated circuit die 324, such as described above with respect to fig. 68.

In some embodiments, integrated circuit die 324 may be at least partially disposed in through vias 240 after connecting interposer substrate 200 to conductive pillars 322p and/or UBM 322.

In fig. 78, the carrier substrate 302 is removed, such as discussed above with respect to fig. 41. Conductive connections 352 are formed over the redistribution structure 306, such as discussed above with respect to fig. 42. The device 500 may be mounted to an interposer substrate 200, such as discussed above with reference to fig. 43, to form a package 600. Because interposer substrate 200 has recessed bond pads 113p, device 500 is securely attached using larger conductive connections 536 relative to the absence of a recess for the bond pads. Recessed bond pads also help to reduce overall package height. The package 600 may be mounted to a package substrate 650, such as discussed above with respect to fig. 44.

In fig. 79, an adhesive layer 332 may be disposed on device 500 and/or integrated circuit die 324 prior to connecting interposer substrate 200 to conductive pillars 322p and/or UBM 322. Adhesive layer 332 may be similar to adhesive layer 332 of fig. 47.

Embodiments provide an interposer bonded to a packaged device, wherein the interposer includes reinforcing structures 120, irregular reinforcing structures 122, reinforcing structures 220, or a combination thereof. The reinforcing structure provides rigidity, heat dissipation, and helps reduce stress and package warpage. An adhesive layer may be used between the interposer and the integrated circuit die to improve adhesion and/or heat dissipation. In some embodiments, the molding compound may be formed before bonding the interposer to the packaged device, while in other embodiments, the molding compound may be formed after bonding the interposer to the packaged device.

In some embodiments, a cavity or through via may be formed in the interposer to help reduce the overall height of the package by aligning the cavity or through via with an integrated circuit die of the packaged device such that the integrated circuit die is at least partially disposed in the cavity or through via. Where a cavity is used, an adhesive layer may be used between the interposer and the integrated circuit die. Where through vias are used, an adhesive layer may be used between the integrated circuit die and the overlying device bonded to the top of the interposer.

In some embodiments, the interposer can have at least a second core substrate layer such that recessed bond pads can be formed between the two core substrate layers. The recessed bond pads provide a strong interface point for mounting the device on top of the interposer. Recessed bond pads also help to reduce the overall height of the finished package. An optional adhesive layer may be used between the interposer and the device mounted on top of the interposer. In some embodiments, the recessed bond pads may further include metal pads lining the openings in the interposer to the recessed bond pads. In embodiments having at least a second core layer, the reinforcement structure may be omitted from the interposer.

Each of these embodiments may include a coupling technique for coupling the interposer to a packaged device that uses stepped bond pads that embed metal posts in solder material from the interposer. In some embodiments, coupling techniques using stepped bond pads may be used to mount a device directly to a packaged device without the use of an interposer.

Embodiments provide various ways to increase the rigidity and strength of the finished package using bottom fan-out device packages and interposers (including, for example, reinforcement structures, recessed bond pads, and stepped bond pads). Some embodiments also use techniques to reduce the overall height of the package to advantageously help save space and provide more efficient heat dissipation through thinner components.

While efforts have been made to describe variations of the embodiments, it will be understood that techniques described in the embodiments discussed herein can be combined to produce variations of these embodiments that combine aspects from one embodiment with aspects from one or more other embodiments. Such combinations should not be considered too cumbersome or require too much experimentation, and should be considered within the scope of the present invention.

One embodiment is a method comprising forming an opening in a core layer of an interposer. A reinforcing structure is formed in the opening, the reinforcing structure extending from the first surface of the interposer to the second surface of the interposer, wherein the reinforcing structure is electrically isolated from the conductive features of the interposer. A first connection is formed on the interposer at the first surface of the interposer. The first connectors of the interposer are bonded to the second connectors of the first packaged device. A molding compound is formed between the interposer and the first packaged device.

In the above method, further comprising: an adhesive layer is formed between the integrated circuit die and the interposer of the first packaged device, the adhesive layer contacting the integrated circuit die and the interposer.

In the above method, further comprising: forming a cavity in the core layer of the interposer, wherein the integrated circuit die is at least partially disposed within the cavity after bonding the first connection to the second connection.

In the above method, further comprising: forming a cavity in the core layer of the interposer, wherein the integrated circuit die is at least partially disposed within the cavity after bonding the first connection to the second connection, wherein the cavity extends completely through the interposer to form a through via.

In the above method, wherein the core layer of the interposer is a first core layer, the method further comprising: forming a second core layer of the interposer; and forming a second opening in the second core layer of the interposer, the second opening exposing a recessed bond pad disposed between the first core layer and the second core layer.

In the above method, wherein the core layer of the interposer is a first core layer, the method further comprising: forming a second core layer of the interposer; and forming a second opening in the second core layer of the interposer, the second opening exposing a recessed bond pad disposed between the first core layer and the second core layer, further comprising: forming a metal film in the second opening, the metal film lining sidewalls and a bottom of the second opening.

In the above method, wherein bonding the first connection of the interposer to the second connection of the first packaged device comprises: aligning the first connector with the second connector; and reflowing a eutectic material to couple the first connector to the second connector.

In the above method, wherein bonding the first connection of the interposer to the second connection of the first packaged device comprises: aligning the first connector with the second connector; and reflowing eutectic material to couple the first connector to the second connector, wherein the eutectic material laterally seals a first vertical portion of the second connector and contacts a second horizontal portion of the second connector, the first vertical portion including a metal post, the second horizontal portion including a step from which the metal post protrudes.

In the above method, wherein bonding the first connection of the interposer to the second connection of the first packaged device comprises: aligning the first connector with the second connector; and reflowing eutectic material to couple the first connector to the second connector, wherein the eutectic material laterally seals a first vertical portion of the second connector and contacts a second horizontal portion of the second connector, the first vertical portion including a metal post and the second horizontal portion including a step from which the metal post protrudes, wherein the eutectic material is within a lateral extent of the second horizontal portion.

Another embodiment is a method comprising aligning first connections of a first package component with second connections of a second package component, the first connections comprising solder material, each second connection comprising a metal post protruding from a metal step. The first connection is in contact with the second connection and the solder material is reflowed, wherein the solder material flows to surround each metal pillar and contact each metal step. The portion of the solder material surrounding the metal pillar is located within the lateral extent of the metal step.

In the above method, wherein the first package component comprises an interposer or an integrated circuit die and the second package component corresponds to a bottom fan-out package.

In the above method, further comprising: after reflowing the solder material, a molding compound is deposited on the first package component and the second package component, the molding compound surrounding the solder material.

In the above method, further comprising: after reflowing the solder material, depositing a molding compound at the first package element and the second package element, the molding compound surrounding the solder material, wherein the second package element is coupled to the first package element at a first surface of the first package element, the method further comprising: coupling a third package element to a second surface of the first package element, the second surface being opposite the first surface.

In the above method, further comprising: a thermal adhesive layer is formed between the first package component and the second package component, the thermal adhesive layer contacting the integrated circuit dies of the first package component and the second package component.

In the above method, wherein the first package element comprises one or more core substrate layers having reinforcing structures disposed therein, each of the reinforcing structures being electrically floating.

Another embodiment is a structure comprising a first device package including an integrated circuit die having an active side, the active side facing down. The first device package also includes a redistribution structure coupled to the one or more contacts of the integrated circuit die and a first contact disposed at an upper surface of the redistribution structure. The structure also includes an interposer that includes a substrate core layer having one or more metal vias disposed therein and one or more reinforcing structures disposed in the substrate core layer. The one or more reinforcing structures are electrically decoupled. Second contacts are disposed at a lower surface of the interposer, the first contacts being coupled to respective second contacts.

In the above structure, wherein the interposer further comprises: a metallization formed on the substrate core layer, the metallization including a bond pad; a second substrate core layer formed over the metallization; and a third contact formed through the second substrate core layer and coupled to the bonding pad.

In the above structure, wherein the interposer further comprises: a metallization formed on the substrate core layer, the metallization including a bond pad; a second substrate core layer formed over the metallization; and third contacts formed through the second substrate core layer and coupled to the bonding pads, wherein the interposer further includes a metallic liner layer surrounding sides and a bottom of each of the third contacts, the metallic liner layer being interposed between the third contact and the bonding pad.

In the above structure, wherein in a top view, a total area of the one or more reinforcing structures is between 5% and 80% of a total area of the substrate core layer.

In the above structure, wherein each of the second contacts comprises a metal post disposed on top of a metal shoulder, wherein each of the first contacts comprises a solder material electrically coupled to a respective one of the one or more metal vias, wherein the solder material encapsulates the metal post, and wherein a lateral extent of the solder material is within a lateral extent of the metal shoulder.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a package structure, comprising:

forming an opening in a core layer of an interposer;

forming a reinforcing structure in the opening, the reinforcing structure extending from the first surface of the interposer to the second surface of the interposer, the reinforcing structure being electrically isolated from the conductive features of the interposer;

forming a first connection on the interposer at the first surface of the interposer;

bonding the first connections of the interposer to second connections of a first packaged device; and

forming a molding compound between the interposer and the first packaged device,

wherein the second connections comprise metal posts extending vertically from a step, wherein bonding the first connections of the interposer to the second connections of the first packaged device comprises:

aligning the first connector with the second connector, wherein the first connector comprises a eutectic material; and

reflowing the eutectic material to couple the first connection to the second connection,

wherein the eutectic material seals the metal pillar, a lateral extent of the eutectic material being within a lateral extent of the step.

2. The method of claim 1, further comprising:

an adhesive layer is formed between the integrated circuit die and the interposer of the first packaged device, the adhesive layer contacting the integrated circuit die and the interposer.

3. The method of claim 2, further comprising:

forming a cavity in the core layer of the interposer, wherein the integrated circuit die is at least partially disposed within the cavity after bonding the first connection to the second connection.

4. The method of claim 3, wherein the cavity extends completely through the interposer to form a through via.

5. The method of claim 1, wherein the core layer of the interposer is a first core layer, the method further comprising:

forming a second core layer of the interposer; and

forming a second opening in the second core layer of the interposer, the second opening exposing a recessed bond pad disposed between the first core layer and the second core layer.

6. The method of claim 5, further comprising:

forming a metal film in the second opening, the metal film lining sidewalls and a bottom of the second opening.

7. The method of claim 1, wherein the reinforcing structures are formed of a different material than the conductive features of the interposer.

8. The method of claim 1, wherein the eutectic material contacts a step of the second connection.

9. The method of claim 1, wherein, in a top view, a total area of the reinforcement structures is between 5% and 80% of a total area of the core layer.

10. A method of forming a package structure, comprising:

aligning first connections of a first package element with second connections of a second package element, the first connections comprising solder material, each of the second connections comprising a metal pillar protruding from a metal step;

contacting the first connector with the second connector;

reflowing the solder material, the solder material flowing to surround each of the metal pillars and to contact each of the metal steps, wherein a portion of the solder material surrounding the metal pillars is located within a lateral extent of the metal steps,

wherein the first package element includes one or more core substrate layers having reinforcing structures disposed therein, each of the reinforcing structures being electrically floating.

11. The method of claim 10, wherein the first package element comprises an interposer or an integrated circuit die and the second package element corresponds to a bottom fan-out package.

12. The method of claim 10, further comprising:

after reflowing the solder material, a molding compound is deposited on the first package component and the second package component, the molding compound surrounding the solder material.

13. The method of claim 12, wherein the second package element is coupled to the first package element at a first surface of the first package element, the method further comprising:

coupling a third package element to a second surface of the first package element, the second surface being opposite the first surface.

14. The method of claim 10, further comprising:

a thermal adhesive layer is formed between the first package component and the second package component, the thermal adhesive layer contacting the integrated circuit dies of the first package component and the second package component.

15. The method of claim 10, further comprising: a cavity is formed in the one or more core substrate layers.

16. A package structure comprising:

a first device package comprising:

an integrated circuit die having an active side, the active side facing down,

a redistribution structure, one or more contacts coupled to the integrated circuit die, and

a first contact disposed at an upper surface of the redistribution structure; and

an interposer, the interposer comprising:

a core layer of the substrate,

one or more metal vias disposed in the substrate core layer,

one or more reinforcing structures disposed in the substrate core layer, the one or more reinforcing structures being electrically decoupled, and

second contacts disposed at a lower surface of the interposer, the first contacts being coupled to the respective second contacts,

wherein each of the second contacts comprises a metal post disposed on top of a metal shoulder, wherein each of the first contacts comprises a solder material electrically coupled to a respective metal via of the one or more metal vias, wherein the solder material encapsulates the metal post, and wherein a lateral extent of the solder material is within a lateral extent of the metal shoulder.

17. The package structure of claim 16, wherein the interposer further comprises:

a metallization formed on the substrate core layer, the metallization including a bond pad;

a second substrate core layer formed over the metallization; and

a third contact formed through the second substrate core layer and coupled to the bonding pad.

18. The package structure of claim 17, wherein the interposer further comprises a metallic liner layer surrounding sides and bottom of each of the third contacts, the metallic liner layer interposed between the third contacts and the bond pads.

19. The package structure of claim 16, wherein a total area of the one or more reinforcement structures is between 5% and 80% of a total area of the substrate core layer in a top view.

20. The package structure of claim 16, wherein the one or more reinforcing structures and the one or more metal vias are formed of different materials.