CN110957264A - Preparation method of copper diffusion barrier layer - Google Patents
Preparation method of copper diffusion barrier layer Download PDFInfo
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- CN110957264A CN110957264A CN201811123568.7A CN201811123568A CN110957264A CN 110957264 A CN110957264 A CN 110957264A CN 201811123568 A CN201811123568 A CN 201811123568A CN 110957264 A CN110957264 A CN 110957264A
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- silicon nitride
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
- C23C16/513—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using plasma jets
Abstract
The invention provides a preparation method of a copper diffusion impervious layer, which comprises the following steps: providing a semiconductor substrate with a copper metal layer; depositing a silicon nitride layer on the copper metal layer by adopting a plasma enhanced atomic layer deposition process; and depositing a silicon carbonitride layer on the silicon nitride layer. The preparation method reduces the dielectric constant of the SiN layer, thereby reducing the dielectric constant of the whole film, improving the bonding performance of the copper diffusion barrier layer and the copper metal layer, not affecting the dielectric constant of the whole dielectric, reducing the generation of protrusion defects and holes, and greatly improving the performance and reliability of the device.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a preparation method of a copper diffusion barrier layer.
Background
As process dimensions shrink, the cross-sectional area and line spacing of metal interconnect lines continue to decrease. The increased interconnect resistance R and parasitic capacitance C cause the RC delay of the interconnect to increase substantially. In order to solve the above problems, it is necessary to use a metal having a lower resistivity as an interconnect material. Meanwhile, since the thickness of the dielectric layer is continuously reduced, the dielectric constant k of the dielectric layer must be reduced to maintain the same capacitance, and therefore, the development of low-k dielectric materials is also required. Against the background of this demand, copper is gradually replacing conventional aluminum as a new interconnect metal due to its lower resistance R.
However, the diffusion coefficient of copper in the dielectric is high, and once diffused, leakage may occur, so that a diffusion barrier layer needs to be added between Cu and the dielectric layer to prevent copper diffusion. The basic requirements of the layer film are good bonding with Cu and low-k dielectric, and the k value of the layer film itself cannot be too high. The adhesion of the diffusion barrier to Cu can directly affect the performance of subsequent processes, such as Chemical Mechanical Polishing (CMP).
One existing copper barrier material is BLOK, which is a compound having a Si-C-N structure with a k value of about 5, but it does not adhere strongly to the underlying copper, about 6J/m2On the other hand, a silicon nitride (SiN) adhesion layer is usually added between silicon carbonitride (SiCN) and copper to achieve 12J/m by using the adhesion between SiN and Cu2The characteristics are used for improving the adhesion between the dielectric substance and the copper metal layer, and conditions are created for the subsequent machining of the chip.
Currently, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process is usually used to prepare the SiN layer, but the SiN layer prepared by PECVD has many disadvantages, such as a large k value of dielectric constant, easy formation of a protrusion defect (hillockdefect), easy generation of a void (void) phenomenon due to copper diffusion at a Cu-SiN interface, etc., which increases the dielectric constant of the whole thin film and easily causes performance degradation and even failure of a semiconductor device.
Therefore, there is a need for an improved process for the preparation of an existing SiN layer to improve the performance of a copper diffusion barrier.
Disclosure of Invention
The invention mainly aims to overcome the defects in the prior art and provide a preparation method of a copper diffusion barrier layer, which overcomes the defects of the existing SiN layer while ensuring the bonding performance of a copper barrier material and a copper metal layer.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method of making a copper diffusion barrier layer comprising:
providing a semiconductor substrate with a copper metal layer;
depositing a silicon nitride layer on the copper metal layer using a Plasma Enhanced Atomic Layer Deposition (PEALD) process; and
depositing a silicon carbonitride layer on the silicon nitride layer.
According to one embodiment of the invention, the silicon nitride layer has a thickness of 3-10 nm.
According to one embodiment of the invention, the silicon nitride layer has a dielectric constant of 4 to 5.
According to an embodiment of the invention, the step of plasma enhanced atomic layer deposition process comprises: introducing silicon source gas into the reaction cavity; removing redundant silicon source gas by inert gas purging; and introducing nitrogen source gas into the reaction cavity, and simultaneously starting the radio frequency power supply to deposit the silicon nitride layer.
According to one embodiment of the invention, the power of the radio frequency power supply is 50-150W.
According to an embodiment of the invention, the deposition temperature of the plasma enhanced atomic layer deposition process is 300-.
According to one embodiment of the invention, the silicon source is tetramethylsilane, ethyl orthosilicate or silane, and the nitrogen source is NH3Or N2And the inert gas is He or Ar.
According to one embodiment of the present invention, the flow rate of the silicon source gas is 50 to 300sccm, and the flow rate of the nitrogen source gas is 100 to 300 sccm.
According to one embodiment of the present invention, the plasma enhanced atomic layer deposition process may be repeated for a plurality of cycles.
According to one embodiment of the invention, the deposition rate of the plasma-enhanced atomic layer deposition process is
And/or circulation.
The preparation method reduces the dielectric constant of the SiN layer, thereby reducing the dielectric constant of the whole film, improving the bonding performance of the copper diffusion barrier layer and the copper metal layer, not affecting the dielectric constant of the whole dielectric, reducing the generation of protrusion defects and holes, and greatly improving the performance and reliability of the device.
Drawings
FIG. 1 is a diagram of a BLOK in a conventional DRAM architecture;
FIG. 2 is a flow chart of a process for fabricating the BLOK structure of FIG. 1;
FIG. 3 is a flow chart of a process for preparing a SiN layer by PECVD in the prior art;
FIG. 4 is a schematic view showing the occurrence of protrusion defects in the conventional PECVD method;
FIG. 5 is a schematic view of holes in a PECVD process according to the prior art;
FIG. 6 is a process flow diagram of a SiN layer produced by PEALD, in accordance with one embodiment of the present invention;
FIG. 7 is a graph comparing protrusion defects of a SiN layer according to the present invention prepared by PEALD and a SiN layer according to the prior art prepared by PECVD.
Wherein the reference numerals are as follows:
100: tantalum metal layer
110: first oxide layer
120: copper metal layer
130: SiN layer
140: SiCN layer
150: second oxide layer
200: copper (Cu)
210: SiN layer
220: protrusion defect
230: defect of hole
Detailed Description
The present invention is described in further detail below by way of specific embodiments in conjunction with the attached drawings, it being understood that the specific embodiments described herein are merely illustrative and explanatory of the invention and do not limit the invention in any way.
In the present invention, anything or matters not mentioned is directly applicable to those known in the art without any change except those explicitly described. Moreover, any embodiment described herein may be freely combined with one or more other embodiments described herein, and the technical solutions or ideas thus formed are considered part of the original disclosure or original description of the present invention, and should not be considered as new matters not disclosed or contemplated herein, unless a person skilled in the art would consider such combination to be clearly unreasonable.
All features disclosed in this invention may be combined in any combination and such combinations are understood to be disclosed or described herein unless a person skilled in the art would consider such combinations to be clearly unreasonable. The numerical points disclosed in the present specification include not only the numerical points specifically disclosed in the examples but also the endpoints of each numerical range in the specification, and ranges in which any combination of the numerical points is disclosed or recited should be considered as ranges of the present invention.
Fig. 1 is a schematic diagram of a BLOK in a conventional DRAM (dynamic random access memory) structure, as shown in fig. 1, two sides of a tantalum metal layer 100 are first oxide layers 110, a copper (Cu) metal layer 120 is half-clad by the tantalum (Ta) metal layer 100, an SiN layer 130 is formed on a surface of the copper metal layer 120, a SiCN layer 140 is formed on the SiN layer 130, and a second oxide layer 150 is formed on the SiCN layer 140.
The silicon carbonitride (SiCN) film is a novel ternary film material, has the advantages of high hardness, wide optical band gap, high-temperature oxidation resistance, corrosion resistance and the like, and has very wide application prospect in the fields of microelectronic semiconductors, ultra-large scale integrated circuits, computer industries and the like.
Fig. 2 is a flow chart illustrating a process for fabricating the BLOK structure of fig. 1, and as shown in fig. 2, the process for fabricating the BLOK structure includes the following steps.
The method comprises the following steps: and etching the oxide layer to form a groove.
Step two: tantalum metal is deposited to cover the surface of the oxide layer and the sidewalls and floor of the recess.
Step three: and (4) evaporating or sputtering metal copper, wherein the copper fills the groove and covers the surface of the oxide layer.
Step four: and performing a Chemical Mechanical Polishing (CMP) process to remove the excessive tantalum metal and copper metal.
Step five: a SiN layer is deposited on the polished surface by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
Step six: and depositing a SiCN layer on the SiN layer to form a BLOK structure.
The structure combines the characteristics of high bonding property of silicon nitride and low dielectric constant of silicon carbonitride, but the SiN layer prepared by PECVD has a larger dielectric constant k value and is easy to generate various defects.
FIG. 3 is a flow chart illustrating a process for preparing SiN layer by PECVD method in the prior art, as shown in FIG. 3, in which SiN is prepared by introducing silicon source gas (e.g., SiH) into the reaction chamber4) And nitrogen source gases (e.g., NH)3) Then, a plasma enhanced deposition is performed on the copper surface, the RF power is usually 650-850W, the deposition temperature is 350-400 ℃, and finally N is performed2Purging, the resulting Cu-Si-N bonds are less, and thus the resulting SiN layer has a large k value (about 6-7), which affects the dielectric constant of the overall dielectric and limits device performance.
Fig. 4 is a schematic diagram illustrating a protrusion defect occurring in the preparation by the PECVD method in the prior art, as shown in fig. 4, when the SiN layer is prepared by the PECVD method, the RF power is high (generally about 650-.
Fig. 5 is a schematic diagram of holes occurring in the PECVD process in the prior art, as shown in fig. 5, when the SiN layer 210 is prepared by PECVD, the quality of the SiN layer 210 is generally poor, and copper 200 is easily diffused at the Cu-SiN interface, thereby causing a void (void) defect 230, and easily causing performance degradation and even failure of the semiconductor device.
In view of the above-mentioned prior art bottlenecks, the present invention provides an improved method for preparing a copper diffusion barrier layer to overcome the drawbacks of the prior art PECVD-deposited SiN.
The preparation method of the copper diffusion impervious layer comprises the following steps:
providing a semiconductor substrate with a copper metal layer;
depositing a silicon nitride (SiN) layer on the copper metal layer by adopting a plasma enhanced atomic layer deposition process; and
a silicon carbonitride (SiCN) layer is deposited on the silicon nitride layer.
The SiN layer is arranged between the copper metal layer and the SiCN layer and used for improving the bonding performance of the copper metal layer and the SiCN layer, and the thickness of the SiN layer is 3-10 nm.
The SiN layer is obtained by adopting a plasma enhanced atomic layer deposition process, more Cu-Si-N bonds are formed, the dielectric constant is 4-5, and the dielectric constant is obviously lower than that of the SiN layer obtained by PECVD deposition in the prior art.
The SiCN layer can be prepared by adopting a PECVD process.
Fig. 6 is a flowchart illustrating a process of manufacturing a SiN layer by PEALD according to an embodiment of the present invention, where the step of manufacturing SiN by a plasma enhanced atomic layer deposition process, as shown in fig. 6, includes:
placing a semiconductor substrate with a copper metal layer into a reaction cavity,
introducing silicon source gas into the reaction cavity;
purging with an inert gas to remove excess silicon source gas (not shown); and
and introducing nitrogen source gas into the reaction cavity, and simultaneously starting a radio frequency power supply to deposit the SiN layer on the copper metal layer.
In the plasma enhanced atomic layer deposition process, the RF power of the radio frequency power supply is 50-150W, which is far lower than 650-850W commonly used in the PECVD method, so that the heat effect of the plasma can be effectively reduced, the damage of the radio frequency plasma to the bottom layer copper can be reduced, and the generation of the protrusion defect can be avoided.
In the plasma enhanced atomic layer deposition process, the deposition temperature is 300-.
In the plasma enhanced atomic layer deposition process, the silicon source is a compound containing silicon group, such as Tetramethylsilane (TMS), tetraethoxysilane or silane, and the nitrogen source is NH3Or N2The inert gas is He or Ar, etc., but not limited thereto.
In the deposition process, the flow rate of the silicon source gas is 50-300 sccm, and the flow rate of the nitrogen source gas is 100-300 sccm.
The plasma enhanced atomic layer deposition process can be repeatedly carried out for a plurality of cycles until the preset film thickness is reached, each cycle can comprise the steps of introducing silicon source gas, inert gas purging, introducing nitrogen source gas and starting radio frequency for deposition, and the deposition rate of each cycle is
And the residual gas in the reaction cavity can be purged by inert gas between each cycle.
Compared with the PECVD method, the SiN film formed by the PEALD method is denser, has higher Si content and lower dielectric constant.
Comparing the protrusion defect of the SiN layer prepared by the PEALD method of the present invention with the SiN layer prepared by the PECVD method of the prior art, the result is shown in fig. 7, which shows that the protrusion defect of the SiN layer prepared by the PECVD method on the left side is significantly large, and the protrusion defect of the SiN layer prepared by the PEALD method on the right side is significantly reduced.
In conclusion, the preparation method of the invention reduces the dielectric constant of the SiN layer, thereby reducing the dielectric constant of the whole film, not only improving the bonding performance of the copper diffusion barrier layer and the copper metal layer, but also not influencing the dielectric constant of the whole dielectric, simultaneously reducing the generation of protrusion defects and holes, and greatly improving the performance and reliability of the device.
It should be noted by those skilled in the art that the described embodiments of the present invention are merely exemplary and that various other substitutions, alterations, and modifications may be made within the scope of the present invention. Accordingly, the present invention is not limited to the above-described embodiments, but is only limited by the claims.
Claims (10)
1. A method of making a copper diffusion barrier layer comprising:
providing a semiconductor substrate with a copper metal layer;
depositing a silicon nitride layer on the copper metal layer by adopting a plasma enhanced atomic layer deposition process; and
depositing a silicon carbonitride layer on the silicon nitride layer.
2. The production method according to claim 1, wherein the thickness of the silicon nitride layer is 3 to 10 nm.
3. The production method according to claim 1, wherein the silicon nitride layer has a dielectric constant of 4 to 5.
4. A method of manufacturing as claimed in claim 1, wherein the step of plasma enhanced atomic layer deposition process comprises:
introducing silicon source gas into the reaction cavity;
removing redundant silicon source gas by inert gas purging; and
and introducing nitrogen source gas into the reaction cavity, and simultaneously starting a radio frequency power supply to deposit the silicon nitride layer.
5. The method of claim 4, wherein the power of the RF power source is 50-150W.
6. The method as claimed in claim 4, wherein the deposition temperature of the PECVD process is 300-350 ℃, and the deposition pressure is 2-5 torr.
7. The method according to claim 4, wherein the silicon source is tetramethylsilane, tetraethoxysilane or silane, and the nitrogen source is NH3Or N2And the inert gas is He or Ar.
8. The method as claimed in claim 4, wherein the silicon source gas has a flow rate of 50 to 300sccm, and the nitrogen source gas has a flow rate of 100 to 300 sccm.
9. A method of manufacturing as recited in claim 4, wherein the plasma enhanced atomic layer deposition process is repeated for a plurality of cycles.
10. The method of claim 9, wherein the plasma enhanced atomic layer deposition process has a deposition rate of
And/or circulation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785747A (en) * | 2020-07-17 | 2020-10-16 | 上海华力集成电路制造有限公司 | CMOS protective layer structure and manufacturing method thereof |
| CN112921303A (en) * | 2021-01-22 | 2021-06-08 | 上海交通大学 | Method for forming protective layer on metal copper |
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| CN103219321A (en) * | 2013-04-09 | 2013-07-24 | 上海华力微电子有限公司 | Composite copper diffusion blocking layer and preparation method thereof |
| CN104217993A (en) * | 2014-09-15 | 2014-12-17 | 上海华力微电子有限公司 | Copper interconnection process |
| CN107017298A (en) * | 2015-12-15 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Field effect transistor |
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2018
- 2018-09-26 CN CN201811123568.7A patent/CN110957264A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219321A (en) * | 2013-04-09 | 2013-07-24 | 上海华力微电子有限公司 | Composite copper diffusion blocking layer and preparation method thereof |
| CN104217993A (en) * | 2014-09-15 | 2014-12-17 | 上海华力微电子有限公司 | Copper interconnection process |
| CN107017298A (en) * | 2015-12-15 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785747A (en) * | 2020-07-17 | 2020-10-16 | 上海华力集成电路制造有限公司 | CMOS protective layer structure and manufacturing method thereof |
| CN112921303A (en) * | 2021-01-22 | 2021-06-08 | 上海交通大学 | Method for forming protective layer on metal copper |
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