CN105470309A - Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor - Google Patents
Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor Download PDFInfo
- Publication number
- CN105470309A CN105470309A CN201610006300.XA CN201610006300A CN105470309A CN 105470309 A CN105470309 A CN 105470309A CN 201610006300 A CN201610006300 A CN 201610006300A CN 105470309 A CN105470309 A CN 105470309A
- Authority
- CN
- China
- Prior art keywords
- groove
- cellular
- semiconductor substrate
- cut
- interarea
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 105
- 239000004065 semiconductor Substances 0.000 claims abstract description 97
- 239000002184 metal Substances 0.000 claims abstract description 65
- 230000001413 cellular effect Effects 0.000 claims description 128
- 238000009413 insulation Methods 0.000 claims description 61
- 229920005591 polysilicon Polymers 0.000 claims description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 23
- 238000005468 ion implantation Methods 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 230000003068 static effect Effects 0.000 abstract 1
- 108010063955 thrombin receptor peptide (42-47) Proteins 0.000 description 41
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a low-voltage MOSFET device with an antistatic protection structure and a manufacturing method therefor. A static protection region comprises a second conductive type well region positioned at the upper part of a first conductive type drift region, and an insulating supporting layer positioned above the second conductive type well region; the second conductive type well region penetrates through a terminal protection region; the insulating supporting layer is positioned on a first main surface of a semiconductor substrate and is in contact with the second conductive type well region; a polycrystalline silicon diode group is arranged on the insulating supporting layer; the polycrystalline silicon diode group comprises a first diode and a second diode; the negative electrode end of the first diode is connected with the negative electrode end of the second diode; the positive electrode end of the first diode is in ohmic contact with the a grid electrode metal on the upward side; and the positive electrode end of the second diode is in ohmic contact with the a source electrode metal on the upward side. The low-voltage MOSFET device is compact in structure, compatible with the existing technological steps, safe, reliable, and capable of improving the voltage resistance of the device with ESD (Electro-static Discharge) protection and reducing manufacturing cost.
Description
Technical field
The present invention relates to a kind of MOSFET element and manufacture method thereof, especially a kind of low pressure MOSFET element and manufacture method thereof with anti-electrostatic protecting structure, belongs to the technical field of semiconductor MOSFET device.
Background technology
Easily there is Electro-static Driven Comb (Electro-Staticdischarge) phenomenon in power MOSFET device, electrostatic can make dielectric between grid source breakdown, thus causes component failure in encapsulation, packaging, transport, assembling and use procedure.For pursuing higher rate of finished products, device reliability, more and more MOSFET requires to design with esd protection.
In existing technological design, common design method is access polysilicon diode group in parallel between grid and source electrode, and when there being electrostatic to occur, diode group can be breakdown prior to grid oxic horizon, immediate leakage electric current and voltage, thus protection MOSFET is not damaged.
The design of the VDMOSFET of normal tape esd protection structure will have an oxide structure, field oxygen layer thickness is generally between 6000 à-10000 à, specifically determine according to device performance and technological level, field oxygen plays two effects, one is use as terminal pressure-resistance structure, two is the insulating blankets serving as polysilicon diode group structure, in manufacturing and designing, field oxygen layer needs 1 piece of reticle, namely technological process and production cost can be caused to increase all thereupon, termination field plate project organization also occupies cellular region usable floor area simultaneously, device synthesis performance can not get improving, especially the featured resistance of low pressure MOSFET can not get optimizing.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art; a kind of low pressure MOSFET element and the manufacture method thereof with anti-electrostatic protecting structure are provided; its compact conformation; compatible with existing processing step; improve the device withstand voltage with esd protection; effective reduction featured resistance and reduction manufacturing cost, safe and reliable.
According to technical scheme provided by the invention, the described low pressure MOSFET element with electrostatic preventing structure, in the top plan view of described MOSFET element, comprise and be positioned at cellular region on semiconductor substrate and terminal protection district, described cellular region is positioned at the center of semiconductor substrate, terminal protection district be positioned at cellular region outer ring and around encirclement described cellular region; Described terminal protection district comprises the electrostatic protection district of next-door neighbour cellular region; On the cross section of described MOSFET element, described semiconductor substrate comprises the first conduction type drift region being positioned at top and the first conductivity type substrate being positioned at below, described first conductivity type substrate adjoins the first conduction type drift region, the upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, and the lower surface of the first conductivity type substrate forms the second interarea of semiconductor substrate; Its innovation is:
On the cross section of described MOSFET element, described electrostatic protection district comprises the second conduction type well region being positioned at the first conduction type drift region internal upper part and the insulation support layer be positioned at above described second conduction type well region, described second conduction type well region runs through terminal protection district, and the first interarea that insulation support layer is positioned at semiconductor substrate contacts with described second conduction type well region; Described insulation support layer is provided with polysilicon diode group, described polysilicon diode group comprises the first diode and the second diode, the cathode terminal of described first diode is connected with the cathode terminal of the second diode, the anode tap of the first diode and the gate metal ohmic contact of top, the anode tap of the second diode and the source metal ohmic contact of top.
Described terminal protection district also comprises dividing potential drop protection zone and cut-off protection zone, and described cut-off protection zone is positioned at the outer ring in terminal protection district, and dividing potential drop protection zone is between electrostatic protection district and cut-off protection zone;
On the cross section of described MOSFET element, at least one potential dividing ring is comprised in described dividing potential drop protection zone, described potential dividing ring adopts groove structure, and described dividing groove is positioned at the second conduction type well region, and the degree of depth of dividing groove stretches in the first conduction type drift region below the second conduction type well region; The sidewall of described dividing groove and diapire growth have dividing groove insulated gate oxide layer, have in the dividing groove of dividing groove insulated gate oxide layer in growth and be filled with dividing groove conductive polycrystalline silicon, the notch of described dividing groove is covered by insulating medium layer, and described insulating medium layer is positioned on the first interarea of semiconductor substrate.
On the cross section of described MOSFET element, described cut-off protection zone adopts groove structure, and described cut-off groove is positioned at the second conduction type well region, and the degree of depth of cut-off groove stretches in the first conduction type drift region below the second conduction type well region; The sidewall of described cut-off groove and diapire growth have cut-off channel insulation gate oxide, are filled with cut-off groove conductive polycrystalline silicon in the cut-off groove that growth has cut-off channel insulation gate oxide; The top of the contiguous dividing groove lateral wall of cut-off groove is provided with the first conduction type cut-off active area, and insulating medium layer covers with on the first interarea of the corresponding semiconductor substrate in described cut-off protection zone; First conduction type cut-off active region is provided with cut-off metal, and described cut-off metal is through ending active area with the first conduction type after insulating medium layer and ending groove conductive polycrystalline silicon ohmic contact.
On the cross section of described MOSFET element, cellular region comprises some regular array and the active cellular of the distribution that is parallel to each other, described active cellular adopts groove structure, described cellular groove extends vertically downward from the first interarea of semiconductor substrate, the bottom land of cellular groove stretches into the first conduction type drift region through after the second conduction type well region, and the second conduction type well region runs through cellular region, cellular channel insulation gate oxide is had at the sidewall of described cellular groove and diapire growth, cellular groove conductive polycrystalline silicon is filled with in the cellular groove that described growth has cellular channel insulation gate oxide, the first conduction type cellular active area is provided with above corresponding lateral wall between adjacent cellular groove, described first conduction type cellular active area, the second conduction type well region between adjacent cellular groove and the source metal ohmic contact above semiconductor substrate first interarea, described source metal is insulated by the insulating medium layer on semiconductor substrate first interarea and cellular groove conductive polycrystalline silicon and isolates.
Have a manufacture method for the low pressure MOSFET element of electrostatic preventing structure, the manufacture method of described low pressure MOSFET element comprises the steps:
A, provide the semiconductor substrate with two opposing main faces, described two opposing main faces comprise the first interarea and the second interarea, comprise the first conduction type drift region and be positioned at the first conductivity type substrate below described first conduction type drift region between the first interarea and the second interarea;
B, on the first interarea of above-mentioned semiconductor substrate deposit hard mask layer, optionally shelter and etch described hard mask layer, to obtain the hard mask window of required through hard mask layer;
C, first interarea of above-mentioned hard mask window to semiconductor substrate is utilized to etch, to obtain required cellular groove, dividing groove and cut-off groove;
D, remove above-mentioned hard mask layer, and the first oxide layer needed for generating at the first interarea of above-mentioned semiconductor substrate, to obtain covering the sidewall of cellular groove and cellular channel insulation gate oxide, the covering sidewall of dividing groove and the dividing groove insulated gate oxide layer of diapire of diapire and covering the cut-off sidewall of groove and the cut-off channel insulation gate oxide of diapire;
E, the first interarea deposit conductive polycrystalline silicon at above-mentioned semiconductor substrate, described conductive polycrystalline silicon is covered in the first interarea of semiconductor substrate and is filled in cellular groove, dividing groove and cut-off groove, etching removes the conductive polycrystalline silicon on semiconductor substrate first interarea, with obtain being positioned at cellular groove cellular groove conductive polycrystalline silicon, be positioned at the dividing groove conductive polycrystalline silicon of dividing groove and be positioned at the cut-off groove conductive polycrystalline silicon of cut-off groove;
F, carry out the second conductive type impurity ion implantation at the first interarea of above-mentioned semiconductor substrate and anneal, to obtain the second conduction type well region being positioned at semiconductor substrate first conduction type drift region, described second conduction type well region extends vertically downward from the first interarea of semiconductor substrate;
G, on the first interarea of above-mentioned semiconductor substrate deposit second oxide layer, and in described second oxide layer deposit electrostatic protection conductive polycrystalline silicon;
H, optionally shelter above-mentioned electrostatic protection conductive polycrystalline silicon, to obtain electrostatic protection ion implantation window; Utilize described electrostatic protection ion implantation window to carry out the second conductive type impurity injection, after annealing, form polysilicon diode group region;
I, optionally shelter and etch above-mentioned second oxide layer and electrostatic protection conductive polycrystalline silicon, remove extra-regional second oxide layer of polysilicon diode group and electrostatic protection conductive polycrystalline silicon, to obtain insulation support layer and to be positioned at the polysilicon diode group on described insulation support layer;
J, carry out the first conductive type impurity ion implantation at the first interarea of above-mentioned semiconductor substrate, to obtain the first required conduction type cellular active area and the first conduction type cut-off active area;
K, the first interarea deposit insulating medium layer at above-mentioned semiconductor substrate, on the first interarea that described insulating medium layer covers semiconductor substrate and in polysilicon diode group, and etching obtains required contact hole on described insulating medium layer;
L, on above-mentioned insulating medium layer deposited metal, and described metal level is optionally sheltered and etches, to obtain required source metal, gate metal and cut-off metal.
The material of described semiconductor substrate comprises silicon.
State that hard mask layer is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
In both described " the first conduction type " and " the second conduction type ", for N-type power MOSFET device, the first conduction type refers to N-type, and the second conduction type is P type; For P type power MOSFET device, the first conduction type is just in time contrary with N type semiconductor device with the type of the second conduction type indication.
Advantage of the present invention: the second conduction type well region runs through terminal protection district, insulation support layer and polysilicon diode group are obtained by a step etching, there is between insulation support layer and the first conduction type drift region the second conduction type well region, insulation support layer need not be born withstand voltage, reduce cost of manufacture, save process time; Utilize the withstand voltage of dividing potential drop protection zone, can voltage endurance capability, thus the doping content of the first conduction type drift region can be improved, specific on-resistance can obviously decline, and reduces chip area, compatible with existing processing step, safe and reliable.
Accompanying drawing explanation
Fig. 1 is equivalent schematic diagram of the present invention.
Fig. 2 is vertical view of the present invention.
Fig. 3 is the F-F cutaway view of Fig. 2 of the present invention.
Fig. 4 is the G-G cutaway view of Fig. 2 of the present invention.
Description of reference numerals: 1-drain electrode end, 2-gate terminal, 3-source terminal, 4-N+ substrate, 5-N type drift region, 6-P trap, 7-dividing groove, 8-cellular groove, 9-cellular channel insulation gate oxide, 10-cellular groove conductive polycrystalline silicon, 11-insulating medium layer, 12-gate metal, 13-polysilicon diode group, 14-source metal, 15-N+ cellular groove active area, 16-ends metal, 17-ends groove, 18-insulation support layer, 19-dividing groove insulated gate oxide layer, 20-dividing groove conductive polycrystalline silicon, 21-ends channel insulation gate oxide, 22-ends groove conductive polycrystalline silicon, 23-N+ ends groove active area, A-terminal protection district, B-electrostatic protection district, C-dividing potential drop protection zone, D-ends protection zone and E-cellular region.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Figure 1, Figure 2, Figure 3 and Figure 4: in order to improve the device withstand voltage with esd protection, reduce manufacturing cost, for N-type low pressure MOSFET element, the present invention is in the top plan view of described MOSFET element, comprise and be positioned at cellular region E on semiconductor substrate and terminal protection district A, described cellular region E is positioned at the center of semiconductor substrate, terminal protection district A be positioned at cellular region outer ring and around encirclement described cellular region A; Described terminal protection district A comprises the electrostatic protection district B of next-door neighbour cellular region A; On the cross section of described MOSFET element, described semiconductor substrate comprises the N-type drift region 5 being positioned at top and the N+ substrate 4 being positioned at below, described N+ substrate 4 adjoins N-type drift region 5, the upper surface of N-type drift region 5 forms the first interarea of semiconductor substrate, and the lower surface of N+ substrate forms the second interarea of semiconductor substrate;
On the cross section of described MOSFET element, described electrostatic protection district B comprises the P trap 6 being positioned at N-type drift region 5 internal upper part and the insulation support layer 18 be positioned at above institute P trap 6, described P trap 6 runs through terminal protection district A, and the first interarea that insulation support layer 18 is positioned at semiconductor substrate contacts with P well region 6; Described insulation support layer 18 is provided with polysilicon diode group 13, described polysilicon diode group 13 comprises the first diode and the second diode, the cathode terminal of described first diode is connected with the cathode terminal of the second diode, the anode tap of the first diode and gate metal 12 ohmic contact of top, the anode tap of the second diode and source metal 14 ohmic contact of top.
Particularly, cellular region E is positioned at the center of semiconductor substrate, and the region of E outer ring, cellular region forms the region of next-door neighbour cellular region E in terminal protection district A, terminal protection district A for the formation of electrostatic protection district B.On the cross section of described MOSFET element, P trap 6 extends vertically downward from the first interarea of semiconductor substrate, the degree of depth of P trap 6 in N-type drift region 5 is less than the thickness in described N-type drift region 5, insulation support layer 18 is directly supported on the first interarea of semiconductor substrate, and contacts with the P trap 6 of below.The top of P trap 6 is covered by insulation support layer 18 and SI semi-insulation dielectric layer 11; the P trap 6 in electrostatic protection district B is made also to be in floating state; P trap 6 in electrostatic protection district B forms PN junction with the N-type drift region 5 of below; insulation support layer 18 is positioned on P trap 6; insulation support layer 18 is also born withstand voltage; and utilize the withstand voltage of described PN junction, the width of insulation support layer 18 can be reduced.
Insulation support layer 18 can be silicon dioxide layer, and polysilicon diode group 13 is distributed on whole insulation support layer 18, and polysilicon diode group 13 is insulated by insulation support layer 18 and P trap 6 and isolates.Two pieces of N conductive regions are included in polysilicon diode group 13; P conductive region is provided with in the both sides of each N conductive region; thus first diode that can be formed needed for two and the second diode; source metal 14 extends to the top of polysilicon diode group 13 from cellular region E; gate metal 12 is positioned at the top of electrostatic protection district B; the P conductive region ohmic contact of gate metal 12 and below; the P conductive region ohmic contact that source metal 14 is corresponding to below, thus the equivalent structure shown in Fig. 1 can be formed.Gate metal 12, source metal 14 are isolated by the insulating medium layer 11 in polysilicon diode group 13 and remaining P conductive region in polysilicon diode group 13 and N conductive region mutually insulated.
Further, described terminal protection district A also comprises dividing potential drop protection zone C and cut-off protection zone D, and described cut-off protection zone D is positioned at the outer ring of terminal protection district A, and dividing potential drop protection zone C is between electrostatic protection district B and cut-off protection zone D;
On the cross section of described MOSFET element, comprise at least one potential dividing ring in described dividing potential drop protection zone C, described potential dividing ring adopts groove structure, and described dividing groove 7 is positioned at P trap 6, and the degree of depth of dividing groove 7 stretches in the N-type drift region 5 below P trap 6; The sidewall of described dividing groove 7 and diapire growth have dividing groove insulated gate oxide layer 19, have in the dividing groove 7 of dividing groove insulated gate oxide layer 19 in growth and be filled with dividing groove conductive polycrystalline silicon 20, the notch of described dividing groove 7 covers 11 by insulating medium layer, and described insulating medium layer 11 is positioned on the first interarea of semiconductor substrate.
In the embodiment of the present invention, the bottom land of dividing groove 7 is positioned at the below of P trap 6, when comprising multiple potential dividing ring in dividing potential drop protection zone C, between adjacent dividing groove 7 by P trap 6 separately, having illustrated in Fig. 3, having had situation during three potential dividing rings in the C of dividing potential drop protection zone.Insulating medium layer 11 covers the notch of dividing groove 7, forms floating state to make the dividing groove conductive polycrystalline silicon in dividing groove 7.
On the cross section of described MOSFET element, described cut-off protection zone D adopts groove structure, and described cut-off groove 17 is positioned at P trap 6, and the degree of depth of cut-off groove 17 stretches in the N-type drift region 5 below P trap 6; The sidewall of described cut-off groove 17 and diapire growth have cut-off channel insulation gate oxide 21, in the cut-off groove 17 that growth has cut-off channel insulation gate oxide 21, be filled with cut-off groove conductive polycrystalline silicon 22; The top of contiguous dividing groove 7 lateral wall of cut-off groove 17 is provided with N+ and ends active area 23, and insulating medium layer 11 covers with on the first interarea of the corresponding semiconductor substrate of described cut-off protection zone D; N+ ends above active area 23 and is provided with cut-off metal 16, described cut-off metal 16 through after insulating medium layer 11 and N+ end active area 23 and end groove conductive polycrystalline silicon 22 ohmic contact.
In the embodiment of the present invention, cut-off groove 17 is same manufacture technics layer with dividing groove 7, cut-off channel insulation gate oxide 21 is same fabrication layer with dividing groove insulated gate oxide layer 19, and cut-off groove conductive polycrystalline silicon 22 is same fabrication layer with dividing groove conductive polycrystalline silicon 20.Insulating medium layer 11 covers with on the first interarea of the corresponding semiconductor substrate of cut-off protection zone D, and cut-off protection zone D is positioned at the outmost turns of whole terminal protection district A.N+ ends the top that active area 23 is positioned at contiguous dividing groove 7 lateral wall of cut-off groove 17 correspondence, and N+ ends active area 23 and is positioned at P trap 6 and contacts with the lateral wall of cut-off groove 17.End directly over active area 23 at N+ and be provided with cut-off contact hole, the through insulating medium layer 11 of described cut-off contact hole, cut-off metal 16 is filled in and ends in contact hole and cover on insulating medium layer 11, cut-off metal 16 ends active area 23 ohmic contact with N+, and ends groove conductive polycrystalline silicon 22 ohmic contact with the part in cut-off groove 17.Described cut-off metal 16 is same fabrication layer with gate metal 12 and source metal 14.
On the cross section of described MOSFET element, cellular region E comprises some regular array and the active cellular of the distribution that is parallel to each other, described active cellular adopts groove structure, described cellular groove 8 extends vertically downward from the first interarea of semiconductor substrate, the bottom land of cellular groove 8 runs through cellular region E through stretching into N-type drift region 5, P trap 6 after P trap 6, cellular channel insulation gate oxide 9 is had at the sidewall of described cellular groove 8 and diapire growth, cellular groove conductive polycrystalline silicon 10 is filled with in the cellular groove 8 that described growth has cellular channel insulation gate oxide 9, N+ cellular active area 15 is provided with above corresponding lateral wall between adjacent cellular groove 10, described N+ cellular active area 15, P trap 6 between adjacent cellular groove 10 and source metal 14 ohmic contact above semiconductor substrate first interarea, described source metal 14 is insulated by the insulating medium layer 11 on semiconductor substrate first interarea and cellular groove conductive polycrystalline silicon 10 and isolates.
In the embodiment of the present invention, active cellular in the E of cellular region is by the cellular groove conductive polycrystalline silicon 10 in cellular groove 8 and join together, and cellular groove conductive polycrystalline silicon 10 and dividing groove conductive polycrystalline silicon 20, to end groove conductive polycrystalline silicon 22 be same fabrication layer; Cellular channel insulation gate oxide 9 and dividing groove insulated gate oxide layer 19 and to end channel insulation gate oxide 21 be same fabrication layer.P trap 6 runs through whole cellular region E equally, and namely P trap 6 runs through semiconductor substrate.The bottom land of cellular groove 8 is positioned at the below of P trap 6, and the bottom land of cellular groove 8 is positioned at N-type drift region 5.N+ cellular active area 15 is positioned at the top of the corresponding lateral wall of adjacent cellular groove 8, and N+ cellular active area 15 is positioned at the top of P trap 6, and N+ cellular active area 15 contacts with the lateral wall of cellular groove 8.Between adjacent cellular cellular 8, be provided with the cellular contact hole of through dielectric 11, source metal 14 is filled in cellular contact hole, thus can P trap 6 ohmic contact between dead source metal 14 and N+ cellular active area 15 and adjacent cellular groove 8.Source metal 14 can also be contacted with cellular groove conductive polycrystalline silicon 10 by insulating medium layer 11 and isolate.
The above-mentioned low pressure MOSFET element with electrostatic preventing structure, can be prepared by following processing step, and the manufacture method of described low pressure MOSFET element comprises the steps:
A, provide the semiconductor substrate with two opposing main faces, described two opposing main faces comprise the first interarea and the second interarea, comprise N-type drift region 5 and be positioned at the N+ substrate below described N-type drift region 5 between the first interarea and the second interarea;
In the embodiment of the present invention, semiconductor substrate can adopt existing conventional semi-conducting material, as silicon etc.
B, on the first interarea of above-mentioned semiconductor substrate deposit hard mask layer, optionally shelter and etch described hard mask layer, to obtain the hard mask window of required through hard mask layer;
In the embodiment of the present invention, state that hard mask layer is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.On the first interarea of semiconductor substrate, deposit hard mask layer and the process that obtains hard mask window are known by the art personnel, repeat no more herein.
C, first interarea of above-mentioned hard mask window to semiconductor substrate is utilized to etch, to obtain required cellular groove 8, dividing groove 7 and cut-off groove 17;
In the embodiment of the present invention; due to the through hard mask layer of hard mask window; namely the first interarea of corresponding semiconductor substrate can be made exposed by hard mask window; thus can etch in the region exposed to semiconductor substrate; obtain cellular groove 8, dividing groove 7 and cut-off groove 17 simultaneously; wherein; the dividing potential drop protection zone C that cellular groove 8 is positioned at the active area E of semiconductor substrate, dividing groove 7 is positioned at setting; cut-off groove 17 is positioned at the cut-off protection zone D of setting; be specially known by the art personnel, repeat no more herein.
D, remove above-mentioned hard mask layer, and the first oxide layer needed for generating at the first interarea of above-mentioned semiconductor substrate, to obtain covering the sidewall of cellular groove 8 and cellular channel insulation gate oxide 9, the covering sidewall of dividing groove 7 and the dividing groove insulated gate oxide layer 19 of diapire of diapire and covering the cut-off sidewall of groove 17 and the cut-off channel insulation gate oxide 21 of diapire;
In the embodiment of the present invention, the first oxide layer can be silicon dioxide layer, and the process removing hard mask layer and the process generating the first oxide layer are known by the art personnel, repeat no more herein.While the first interarea of semiconductor substrate generates the first oxide layer, cellular channel insulation gate oxide 9, dividing groove insulated gate oxide layer 19 and cut-off channel insulation gate oxide 21 can be obtained.
E, the first interarea deposit conductive polycrystalline silicon at above-mentioned semiconductor substrate, described conductive polycrystalline silicon is covered in the first interarea of semiconductor substrate and is filled in cellular groove 8, dividing groove 7 and cut-off groove 17, etching removes the conductive polycrystalline silicon on semiconductor substrate first interarea, with obtain being positioned at cellular groove 8 cellular groove conductive polycrystalline silicon 10, be positioned at the dividing groove conductive polycrystalline silicon 20 of dividing groove 7 and be positioned at the cut-off groove conductive polycrystalline silicon 22 of cut-off groove 17;
In the embodiment of the present invention, on the first interarea of semiconductor substrate during deposit conductive polycrystalline silicon, described conductive polycrystalline silicon can be filled in cellular groove 8, dividing groove 7 and cut-off groove 17 simultaneously, removal is covered in corresponding conductive polycrystalline silicon on semiconductor substrate, can obtain required cellular groove conductive polycrystalline silicon 10, dividing groove conductive polycrystalline silicon 20 and cut-off groove conductive polycrystalline silicon 22.
F, carry out p type impurity ion implantation at the first interarea of above-mentioned semiconductor substrate and anneal, to obtain the P trap 6 being positioned at semiconductor substrate N-type drift region 5, described P trap 6 extends vertically downward from the first interarea of semiconductor substrate;
In the embodiment of the present invention, conduction type due to N-type drift region 5 is N-type, after implanting p-type foreign ion is also annealed, P trap 6 can be formed, the degree of depth of P trap 6 is less than the thickness of N-type drift region 5, and P trap 6 is all positioned at the top of cellular groove 8 bottom land, the top of dividing groove 7 bottom land and ends the top of groove 17 bottom land, the technical process forming P trap 6 is known by the art personnel, repeats no more herein.
G, on the first interarea of above-mentioned semiconductor substrate deposit second oxide layer, and in described second oxide layer deposit electrostatic protection conductive polycrystalline silicon;
In the embodiment of the present invention, the second oxide layer covers the first interarea of semiconductor substrate, and electrostatic protection conductive polycrystalline silicon is covered in the second oxide layer, and the second oxide layer can be silicon dioxide layer.
H, optionally shelter above-mentioned electrostatic protection conductive polycrystalline silicon, to obtain electrostatic protection ion implantation window; Utilize described electrostatic protection ion implantation window to carry out p type impurity injection, after annealing, form polysilicon diode group region;
In the embodiment of the present invention; ion implantation mask layer can be set on electrostatic protection polysilicon layer, by optionally sheltering described ion implantation mask layer and etch, electrostatic protection ion implantation window can be obtained; wherein, described electrostatic protection ion implantation window is positioned at electrostatic protection district B.After utilizing electrostatic protection ion implantation window to carry out p type impurity ion implantation; polysilicon diode group region can be obtained; described polysilicon diode group region comprises the P conductive region, N conductive region, P conductive region, N conductive region and the P conductive region that connect successively; thus the first required diode and the second diode can be formed; the cathode terminal of the first diode is connected with the cathode terminal of the second diode, as shown in Figure 4.
I, optionally shelter and etch above-mentioned second oxide layer and electrostatic protection conductive polycrystalline silicon, remove extra-regional second oxide layer of polysilicon diode group and electrostatic protection conductive polycrystalline silicon, to obtain insulation support layer 18 and to be positioned at the polysilicon diode group 13 on described insulation support layer 18;
In the embodiment of the present invention; remove above-mentioned ion implantation mask layer; and described electrostatic protection conductive polycrystalline silicon and the second oxide layer are etched simultaneously; only retain the second oxide layer of polysilicon diode group region and below; thus polysilicon diode group 13 and insulation support layer 18 can be obtained; the process that etching obtains polysilicon diode group 13 and insulation support layer 18 is known by the art personnel, repeats no more herein.
J, carry out N-type impurity ion implantation at the first interarea of above-mentioned semiconductor substrate, to obtain required N+ cellular active area 15 and N+ ends active area 23;
In the embodiment of the present invention, before carrying out N-type impurity ion implantation, selectivity can be carried out on the first interarea of semiconductor substrate to shelter, only be positioned at above the corresponding lateral wall of adjacent cellular groove 8 to make N+ cellular active area 15, and N+ ends the top that active area 23 is positioned at contiguous dividing groove 7 lateral wall of cut-off groove 17 correspondence, inject N-type impurity ion, the process obtaining N+ cellular active area 15 and N+ cut-off active area 23, known by the art personnel, repeats no more herein.
K, the first interarea deposit insulating medium layer 11 at above-mentioned semiconductor substrate, on the first interarea that described insulating medium layer 11 covers semiconductor substrate and in polysilicon diode group 13, and etching obtains required contact hole on described insulating medium layer 11;
In the embodiment of the present invention; in the first interarea that insulating medium layer 11 covers semiconductor substrate and polysilicon diode group 13; described contact hole comprises the electrostatic protection contact hole above cut-off contact hole, cellular contact hole and polysilicon diode group 13, the through insulating medium layer 11 of described contact hole.
L, on above-mentioned insulating medium layer 11 deposited metal, and described metal level is optionally sheltered and etches, to obtain required source metal 14, gate metal 12 and cut-off metal 16.
In the embodiment of the present invention, Conventional process steps is adopted to obtain being positioned at the metal level on insulating medium layer 11, described metal level fills above-mentioned contact hole, optionally shelters and etch described metal level, can obtain source metal 14, gate metal 12 and cut-off metal 16.Contacting metal 16 is filled in cut-off contact hole; end active area 23 to make cut-off metal 16 with N+ and end groove conductive polycrystalline silicon 22 ohmic contact; source metal 14 and N+ cellular active area 15 and corresponding P trap 6 ohmic contact, and source metal 14, gate metal 12 are by electrostatic protection contact hole and the anode tap of the first diode, the anode tap ohmic contact of the second diode.
In the embodiment of the present invention, utilize N+ substrate 4 can be formed MOSFET element drain electrode end 1, utilize source metal 14 can form the source terminal 3 of MOSFET element, utilize gate metal 12 can form gate terminal 2.P trap 6 is present in whole terminal protection district A, has P trap 6 between multiple dividing groove 7.
When the drain electrode end 1 in described N-type MOSFET element adds forward bias voltage, during source terminal 32 ground connection extreme with Gate, maximum crash ionization rate is in the bottom of cellular region groove 8, and MOSFET element punctures in cellular region 8.The PN junction that P trap 6 in N-type drift region 5 and cellular region E is formed is reverse-biased, and depletion layer can be expanded to lightly doped N-type drift region 5, and when depletion layer expands in electrostatic protection district B, the P trap 6 in electrostatic protection district B is born withstand voltage with the PN junction that N-type drift region 5 forms.When depletion layer expands to dividing potential drop protection zone C, dividing groove 7 starts to bear withstand voltage, effectively can improve the voltage endurance capability of MOSFET element.
In the electrostatic protection district of existing MOSFET element, owing to there is not P trap 6, namely insulation support layer 18 directly contacts with N-type drift region 5.Now, drain electrode end 1 adds forward bias voltage, during source terminal 32 ground connection extreme with Gate, maximum crash ionization rate is in the infall of the main knot cellular groove 8 corresponding with it, and namely device punctures at terminal protection district A.Described master becomes the PN junction that the P trap 6 on the left of the outermost cellular groove 8 of cellular region E forms with N-type drift region 5.In existing electrostatic protection district, insulation support layer 18 also needs to bear withstand voltage, therefore, needs reticle photoetching to form insulation support layer, causes the production cost of MOSFET element greatly to increase.
P trap 6 of the present invention runs through terminal protection district A, insulation support layer 18 and polysilicon diode group 13 are obtained by a step etching, and have P trap 6 between insulation support layer 18 and N-type drift region 5, insulation support layer 18 need not be born withstand voltage, reduce cost of manufacture, save process time; Utilize that dividing potential drop protection zone C's is withstand voltage, can voltage endurance capability, thus the doping content of N-type drift region 5 can be improved, specific on-resistance can obviously decline, and reduces chip area, compatible with existing processing step, safe and reliable.
Claims (7)
1. one kind has the low pressure MOSFET element of electrostatic preventing structure, in the top plan view of described MOSFET element, comprise and be positioned at cellular region on semiconductor substrate and terminal protection district, described cellular region is positioned at the center of semiconductor substrate, terminal protection district be positioned at cellular region outer ring and around encirclement described cellular region; Described terminal protection district comprises the electrostatic protection district of next-door neighbour cellular region; On the cross section of described MOSFET element, described semiconductor substrate comprises the first conduction type drift region being positioned at top and the first conductivity type substrate being positioned at below, described first conductivity type substrate adjoins the first conduction type drift region, the upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, and the lower surface of the first conductivity type substrate forms the second interarea of semiconductor substrate; It is characterized in that:
On the cross section of described MOSFET element, described electrostatic protection district comprises the second conduction type well region being positioned at the first conduction type drift region internal upper part and the insulation support layer be positioned at above described second conduction type well region, described second conduction type well region runs through terminal protection district, and the first interarea that insulation support layer is positioned at semiconductor substrate contacts with described second conduction type well region; Described insulation support layer is provided with polysilicon diode group, described polysilicon diode group comprises the first diode and the second diode, the cathode terminal of described first diode is connected with the cathode terminal of the second diode, the anode tap of the first diode and the gate metal ohmic contact of top, the anode tap of the second diode and the source metal ohmic contact of top.
2. the low pressure MOSFET element with electrostatic preventing structure according to claim 1, it is characterized in that: described terminal protection district also comprises dividing potential drop protection zone and cut-off protection zone, described cut-off protection zone is positioned at the outer ring in terminal protection district, and dividing potential drop protection zone is between electrostatic protection district and cut-off protection zone;
On the cross section of described MOSFET element, at least one potential dividing ring is comprised in described dividing potential drop protection zone, described potential dividing ring adopts groove structure, and described dividing groove is positioned at the second conduction type well region, and the degree of depth of dividing groove stretches in the first conduction type drift region below the second conduction type well region; The sidewall of described dividing groove and diapire growth have dividing groove insulated gate oxide layer, have in the dividing groove of dividing groove insulated gate oxide layer in growth and be filled with dividing groove conductive polycrystalline silicon, the notch of described dividing groove is covered by insulating medium layer, and described insulating medium layer is positioned on the first interarea of semiconductor substrate.
3. the low pressure MOSFET element with electrostatic preventing structure according to claim 2, it is characterized in that: on the cross section of described MOSFET element, described cut-off protection zone adopts groove structure, described cut-off groove is positioned at the second conduction type well region, and the degree of depth of cut-off groove stretches in the first conduction type drift region below the second conduction type well region; The sidewall of described cut-off groove and diapire growth have cut-off channel insulation gate oxide, are filled with cut-off groove conductive polycrystalline silicon in the cut-off groove that growth has cut-off channel insulation gate oxide; The top of the contiguous dividing groove lateral wall of cut-off groove is provided with the first conduction type cut-off active area, and insulating medium layer covers with on the first interarea of the corresponding semiconductor substrate in described cut-off protection zone; First conduction type cut-off active region is provided with cut-off metal, and described cut-off metal is through ending active area with the first conduction type after insulating medium layer and ending groove conductive polycrystalline silicon ohmic contact.
4. the low pressure MOSFET element with electrostatic preventing structure according to claim 1, it is characterized in that: on the cross section of described MOSFET element, cellular region comprises some regular array and the active cellular of the distribution that is parallel to each other, described active cellular adopts groove structure, described cellular groove extends vertically downward from the first interarea of semiconductor substrate, the bottom land of cellular groove stretches into the first conduction type drift region through after the second conduction type well region, and the second conduction type well region runs through cellular region, cellular channel insulation gate oxide is had at the sidewall of described cellular groove and diapire growth, cellular groove conductive polycrystalline silicon is filled with in the cellular groove that described growth has cellular channel insulation gate oxide, the first conduction type cellular active area is provided with above corresponding lateral wall between adjacent cellular groove, described first conduction type cellular active area, the second conduction type well region between adjacent cellular groove and the source metal ohmic contact above semiconductor substrate first interarea, described source metal is insulated by the insulating medium layer on semiconductor substrate first interarea and cellular groove conductive polycrystalline silicon and isolates.
5. have a manufacture method for the low pressure MOSFET element of electrostatic preventing structure, it is characterized in that, the manufacture method of described low pressure MOSFET element comprises the steps:
(a), the semiconductor substrate with two opposing main faces is provided, described two opposing main faces comprise the first interarea and the second interarea, comprise the first conduction type drift region and be positioned at the first conductivity type substrate below described first conduction type drift region between the first interarea and the second interarea;
(b), on the first interarea of above-mentioned semiconductor substrate deposit hard mask layer, optionally shelter and etch described hard mask layer, to obtain the hard mask window of required through hard mask layer;
(c), utilize first interarea of above-mentioned hard mask window to semiconductor substrate to etch, with obtain required cellular groove, dividing groove and cut-off groove;
(d), remove above-mentioned hard mask layer, and the first oxide layer needed for generating at the first interarea of above-mentioned semiconductor substrate, to obtain covering the sidewall of cellular groove and cellular channel insulation gate oxide, the covering sidewall of dividing groove and the dividing groove insulated gate oxide layer of diapire of diapire and covering the cut-off sidewall of groove and the cut-off channel insulation gate oxide of diapire;
(e), the first interarea deposit conductive polycrystalline silicon at above-mentioned semiconductor substrate, described conductive polycrystalline silicon is covered in the first interarea of semiconductor substrate and is filled in cellular groove, dividing groove and cut-off groove, etching removes the conductive polycrystalline silicon on semiconductor substrate first interarea, with obtain being positioned at cellular groove cellular groove conductive polycrystalline silicon, be positioned at the dividing groove conductive polycrystalline silicon of dividing groove and be positioned at the cut-off groove conductive polycrystalline silicon of cut-off groove;
(f), carry out the second conductive type impurity ion implantation at the first interarea of above-mentioned semiconductor substrate and anneal, to obtain the second conduction type well region being positioned at semiconductor substrate first conduction type drift region, described second conduction type well region extends vertically downward from the first interarea of semiconductor substrate;
(g), on the first interarea of above-mentioned semiconductor substrate deposit second oxide layer, and in described second oxide layer deposit electrostatic protection conductive polycrystalline silicon;
(h), optionally shelter above-mentioned electrostatic protection conductive polycrystalline silicon, to obtain electrostatic protection ion implantation window; Utilize described electrostatic protection ion implantation window to carry out the second conductive type impurity injection, after annealing, form polysilicon diode group region;
(i), optionally shelter and etch above-mentioned second oxide layer and electrostatic protection conductive polycrystalline silicon, remove extra-regional second oxide layer of polysilicon diode group and electrostatic protection conductive polycrystalline silicon, to obtain insulation support layer and to be positioned at the polysilicon diode group on described insulation support layer;
(j), carry out the first conductive type impurity ion implantation at the first interarea of above-mentioned semiconductor substrate, with obtain the first required conduction type cellular active area and the first conduction type cut-off active area;
(k), the first interarea deposit insulating medium layer at above-mentioned semiconductor substrate, on the first interarea that described insulating medium layer covers semiconductor substrate and in polysilicon diode group, and etching obtains required contact hole on described insulating medium layer;
(l), on above-mentioned insulating medium layer deposited metal, and described metal level is optionally sheltered and etches, to obtain required source metal, gate metal and cut-off metal.
6. there is the manufacture method of the low pressure MOSFET element of electrostatic preventing structure according to claim 5, it is characterized in that: the material of described semiconductor substrate comprises silicon.
7. there is the manufacture method of the low pressure MOSFET element of electrostatic preventing structure according to claim 5, it is characterized in that: state that hard mask layer is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610006300.XA CN105470309A (en) | 2016-01-06 | 2016-01-06 | Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610006300.XA CN105470309A (en) | 2016-01-06 | 2016-01-06 | Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105470309A true CN105470309A (en) | 2016-04-06 |
Family
ID=55607834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610006300.XA Pending CN105470309A (en) | 2016-01-06 | 2016-01-06 | Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105470309A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024634A (en) * | 2016-07-06 | 2016-10-12 | 深圳深爱半导体股份有限公司 | Power transistor with electrostatic discharge protection diode structures, and manufacturing method thereof |
| CN106654523A (en) * | 2016-12-20 | 2017-05-10 | 西安科锐盛创新科技有限公司 | Preparation method of Si-based SPiN diode for reconfigurable multi-layer holographic antenna |
| CN106785336A (en) * | 2016-12-20 | 2017-05-31 | 西安电子科技大学 | Possesses SiO2The preparation method of the frequency reconfigurable holographic antenna of protective layer |
| CN107994000A (en) * | 2017-12-15 | 2018-05-04 | 西安科锐盛创新科技有限公司 | TSV pinboards for system in package and preparation method thereof |
| CN108054139A (en) * | 2017-12-15 | 2018-05-18 | 西安科锐盛创新科技有限公司 | TSV pinboards and preparation method thereof |
| CN108091573A (en) * | 2017-12-20 | 2018-05-29 | 西安龙腾新能源科技发展有限公司 | Shield grid groove MOSFET ESD structures and its manufacturing method |
| CN108389859A (en) * | 2018-03-30 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | The structures and methods of ESD polysilicon layers are integrated in trench gate mosfet |
| CN109244134A (en) * | 2018-09-04 | 2019-01-18 | 深圳市南硕明泰科技有限公司 | A kind of field effect transistor and preparation method thereof |
| CN110660795A (en) * | 2018-06-28 | 2020-01-07 | 英飞凌科技股份有限公司 | Power semiconductor device |
| CN111276476A (en) * | 2018-12-05 | 2020-06-12 | 无锡华润上华科技有限公司 | Semiconductor device manufacturing method |
| CN111490094A (en) * | 2020-04-20 | 2020-08-04 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
| CN114156343A (en) * | 2022-02-08 | 2022-03-08 | 绍兴中芯集成电路制造股份有限公司 | Trench power semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6249023B1 (en) * | 1998-08-21 | 2001-06-19 | Zetex Plc | Gated semiconductor device |
| US20070176239A1 (en) * | 2006-01-31 | 2007-08-02 | M-Mos Semiconductor Sdn. Bhd. | Trenched MOSFETS with improved ESD protection capability |
| CN101752375A (en) * | 2009-12-29 | 2010-06-23 | 无锡新洁能功率半导体有限公司 | Groove type power MOS device with improved terminal protective structure |
| CN203850305U (en) * | 2014-05-26 | 2014-09-24 | 无锡新洁能股份有限公司 | Groove type power MOSFET device with current sampling function |
| CN205319162U (en) * | 2016-01-06 | 2016-06-15 | 无锡新洁能股份有限公司 | Low pressure MOSFET device with prevent electrostatic protection structure |
-
2016
- 2016-01-06 CN CN201610006300.XA patent/CN105470309A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6249023B1 (en) * | 1998-08-21 | 2001-06-19 | Zetex Plc | Gated semiconductor device |
| US20070176239A1 (en) * | 2006-01-31 | 2007-08-02 | M-Mos Semiconductor Sdn. Bhd. | Trenched MOSFETS with improved ESD protection capability |
| CN101752375A (en) * | 2009-12-29 | 2010-06-23 | 无锡新洁能功率半导体有限公司 | Groove type power MOS device with improved terminal protective structure |
| CN203850305U (en) * | 2014-05-26 | 2014-09-24 | 无锡新洁能股份有限公司 | Groove type power MOSFET device with current sampling function |
| CN205319162U (en) * | 2016-01-06 | 2016-06-15 | 无锡新洁能股份有限公司 | Low pressure MOSFET device with prevent electrostatic protection structure |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024634A (en) * | 2016-07-06 | 2016-10-12 | 深圳深爱半导体股份有限公司 | Power transistor with electrostatic discharge protection diode structures, and manufacturing method thereof |
| CN106024634B (en) * | 2016-07-06 | 2022-11-18 | 深圳深爱半导体股份有限公司 | Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof |
| CN106654523A (en) * | 2016-12-20 | 2017-05-10 | 西安科锐盛创新科技有限公司 | Preparation method of Si-based SPiN diode for reconfigurable multi-layer holographic antenna |
| CN106785336A (en) * | 2016-12-20 | 2017-05-31 | 西安电子科技大学 | Possesses SiO2The preparation method of the frequency reconfigurable holographic antenna of protective layer |
| CN107994000B (en) * | 2017-12-15 | 2021-01-12 | 浙江清华柔性电子技术研究院 | TSV adapter plate for system-in-package and preparation method thereof |
| CN108054139B (en) * | 2017-12-15 | 2020-12-18 | 浙江清华柔性电子技术研究院 | TSV adapter plate and preparation method thereof |
| CN108054139A (en) * | 2017-12-15 | 2018-05-18 | 西安科锐盛创新科技有限公司 | TSV pinboards and preparation method thereof |
| CN107994000A (en) * | 2017-12-15 | 2018-05-04 | 西安科锐盛创新科技有限公司 | TSV pinboards for system in package and preparation method thereof |
| CN108091573A (en) * | 2017-12-20 | 2018-05-29 | 西安龙腾新能源科技发展有限公司 | Shield grid groove MOSFET ESD structures and its manufacturing method |
| CN108389859A (en) * | 2018-03-30 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | The structures and methods of ESD polysilicon layers are integrated in trench gate mosfet |
| CN110660795A (en) * | 2018-06-28 | 2020-01-07 | 英飞凌科技股份有限公司 | Power semiconductor device |
| CN109244134A (en) * | 2018-09-04 | 2019-01-18 | 深圳市南硕明泰科技有限公司 | A kind of field effect transistor and preparation method thereof |
| CN111276476A (en) * | 2018-12-05 | 2020-06-12 | 无锡华润上华科技有限公司 | Semiconductor device manufacturing method |
| CN111276476B (en) * | 2018-12-05 | 2022-09-09 | 无锡华润上华科技有限公司 | Semiconductor device manufacturing method |
| CN111490094A (en) * | 2020-04-20 | 2020-08-04 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
| CN111490094B (en) * | 2020-04-20 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
| CN114156343A (en) * | 2022-02-08 | 2022-03-08 | 绍兴中芯集成电路制造股份有限公司 | Trench power semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105470309A (en) | Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor | |
| US9576841B2 (en) | Semiconductor device and manufacturing method | |
| US6710418B1 (en) | Schottky rectifier with insulation-filled trenches and method of forming the same | |
| CN101180739B (en) | Semiconductor device with edge termination | |
| JP6092749B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN109659351B (en) | Insulated gate bipolar transistor | |
| CN107342326B (en) | Power semiconductor device capable of reducing on-resistance and manufacturing method thereof | |
| TW201622096A (en) | TVS structures for high surge and low capacitance and preparing method thereof | |
| CN101150146A (en) | Semiconductor device and method for fabricating thereof | |
| CN108091573B (en) | Manufacturing method of shielded gate trench MOSFET ESD structure | |
| CN110739303B (en) | Trench VDMOS device integrated with ESD protection and manufacturing method | |
| CN205319162U (en) | Low pressure MOSFET device with prevent electrostatic protection structure | |
| CN101471381B (en) | Trench gate mosfet and method for fabricating the same | |
| US11075292B2 (en) | Insulated gate bipolar transistor, and manufacturing method therefor | |
| CN110416284B (en) | Trench type semiconductor power device terminal protection structure and power device | |
| CN116741828A (en) | Trench gate transistor assembly | |
| CN111863750B (en) | Method for manufacturing semiconductor device | |
| CN102064193B (en) | Double diffusion drain metal oxide semiconductor field effect transistor (DDDMOS) and manufacturing method thereof | |
| JPS63194367A (en) | Semiconductor device | |
| CN116598359B (en) | Trench MOSFET device integrated with junction barrier Schottky diode and manufacturing method | |
| CN110911495B (en) | Groove VDMOS device integrated with ESD protection and manufacturing method | |
| CN214152910U (en) | High-voltage plane VDMOS device integrated with ESD structure | |
| CN116344534B (en) | ESD-resistant groove type power semiconductor device and preparation method thereof | |
| CN111863618B (en) | Method for manufacturing semiconductor device | |
| TWI575570B (en) | Semiconductor device and method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160406 |