CN110911398A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110911398A
CN110911398A CN201910022345.XA CN201910022345A CN110911398A CN 110911398 A CN110911398 A CN 110911398A CN 201910022345 A CN201910022345 A CN 201910022345A CN 110911398 A CN110911398 A CN 110911398A
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semiconductor layer
electrode
semiconductor
layer
conductivity type
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河村圭子
小仓常雄
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Abstract

半导体装置具备：第1电极；第2电极，配置在与上述第1电极对置的位置；以及半导体部，设置在上述第1电极与上述第2电极之间，包括第1导电型的第1半导体层。上述半导体部还包括：设置在上述第1半导体层与上述第1电极之间的第2导电型的第2半导体层、及选择性地设置在上述第1半导体层中、并被配置在与上述第2半导体层分离的位置的第2导电型的第3半导体层。上述第1电极具有延伸部，该延伸部与上述第2半导体层电连接，贯穿上述第2半导体层地在朝向上述第2电极的第1方向上延伸，并与上述第3半导体层连接。

Description

半导体装置
关联申请
本申请享受以日本专利申请2018－172650号(申请日：2018年9月14日)为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
实施方式涉及半导体装置。
背景技术
在电力控制用半导体装置中，要求降低正向电压及开关损失。正向电压能够通过提高半导体中的载流子浓度来降低。另一方面，开关损失通过将在半导体装置的关断时将半导体中的载流子向电极牵引的时间缩短来降低。因此，难以将正向电压及开关损失这两者降低。
发明内容
实施方式提供能够降低开关损失的半导体装置。
实施方式所涉及的半导体装置具备：第1电极；第2电极，配置在与上述第1电极对置的位置；以及半导体部，设置在上述第1电极与上述第2电极之间，包括第1导电型的第1半导体层。上述半导体部还包括：第2导电型的第2半导体层，设置在上述第1半导体层与上述第1电极之间；以及第2导电型的第3半导体层，选择性地设置在上述第1半导体层中，被配置在与上述第2半导体层分离的位置。上述第1电极具有延伸部，该延伸部与上述第2半导体层电连接，贯穿上述第2半导体层地在朝向上述第2电极的第1方向上延伸，并与上述第3半导体层连接。
附图说明
图1是表示第1实施方式所涉及的半导体装置的示意剖视图。
图2A及图2B是表示第1实施方式所涉及的半导体装置的示意俯视图。
图3A及图3B是表示第1实施方式所涉及的半导体装置中的载流子的流动的示意图。
图4是表示第1实施方式的变形例所涉及的半导体装置的示意剖视图。
图5A及图5B是表示第1实施方式的变形例所涉及的半导体装置中的载流子的流动的示意图。
图6是表示第1实施方式的另一个变形例所涉及的半导体装置的示意剖视图。
图7A及图7B是表示第1实施方式的另一个变形例所涉及的半导体装置中的载流子的流动的示意图。
图8是表示第2实施方式所涉及的半导体装置的示意剖视图。
图9A及图9B是表示第2实施方式所涉及的半导体装置中的载流子的流动的示意图。
图10是表示第3实施方式所涉及的半导体装置的示意剖视图。
具体实施方式
以下，关于实施方式，参照附图进行说明。对附图中的同一部分，标注同一编号，从而其详细的说明适当省略，对不同的部分进行说明。另外，附图是示意性的或概念性的，各部分的厚度与宽度的关系、部分间的大小的比率等，不一定与现实中的相同。另外，即使在表示相同的部分的情况下，也存在根据附图而彼此的尺寸、比率不同地进行表示的情况。
并且，使用各图中所示的X轴、Y轴及Z轴，对各部分的配置及构成进行说明。X轴、Y轴、Z轴相互正交，分别表示X方向、Y方向、Z方向。另外，存在将Z方向作为上方，并将其相反向作为下方进行说明的情况。
(第1实施方式)
图1是表示第1实施方式所涉及的半导体装置1的示意剖视图。半导体装置1例如是PIN二极管，与IGBT(Insulated Gate bipolar Transistor)、MOSFET(Metal OxideSemiconductor Field Effect Transistor)等一起使用，构成功率转换器等。
如图1所示，半导体装置1具备半导体部10、阳极电极20及阴极电极30。半导体装置1是纵式元件，阴极电极30配置在与阳极电极20对置的位置。半导体部10设置在阳极电极20与阴极电极30之间。
半导体部10包括n型半导体层11、p型阳极层13、n型阴极层15及p型半导体层17。p型阳极层13设置在n型半导体层11与阳极电极20之间。n型阴极层15设置在n型半导体层11与阴极电极30之间。
p型半导体层17选择性地设置在n型半导体层11中。p型半导体层17配置在与p型阳极层13分离的位置。
阳极电极20与p型阳极层13电连接。另外，阴极电极30与n型阴极层15电连接。这里，所谓的“电连接”，表示直接接触的情况和隔着其他的导电层而接触的情况这两者。在以下的记载中也是同样的。
阳极电极20具有贯穿p型阳极层13地在朝向阴极电极30的方向(即Z方向的反向，以下，－Z方向)上延伸的延伸部21。延伸部21被设置为与p型半导体层17相连。另外，延伸部21包括位于p型阳极层13与p型半导体层17之间的接触部CP。接触部CP与n型半导体层11接触。
n型半导体层11及n型阴极层15例如是n型硅层。n型阴极层15包括比n型半导体层11中包括的n型杂质高浓度的n型杂质。n型阴极层15可以与n型半导体层11设置为一体。即，在n型半导体层11的背面侧，例如可以使用离子注入来导入高浓度的n型杂质。p型阳极层13例如通过对n型半导体层11离子注入p型杂质而形成。
阳极电极20的延伸部21通过在具有贯穿p型阳极层13的深度的槽TR的内部埋入金属层而形成。延伸部21至少在与n型半导体层11接触的部分包括相对于n型半导体层11肖特基接触的金属。延伸部21既可以是与阳极电极20的主体相同的材料，也可以使用不同的材料形成。延伸部21例如至少在与n型半导体层11接触的部分包括铝(Al)、钽(Ta)、银(Ag)、钼(Mo)、钨(W)、钴(Co)、铬(Cr)、钌(Ru)、金(Au)、钯(Pd)、镍(Ni)、白金(Pt)中的某一种。
p型半导体层17例如通过对槽TR的底面离子注入p型杂质而形成。p型半导体层17既可以与p型阳极层13同时形成，也可以通过另一个工序形成。p型半导体层17例如设置为与埋入于槽TR的金属层(即，延伸部21)接触。
图2A及图2B是表示第1实施方式所涉及的半导体装置1的示意俯视图。图2A及图2B例如对半导体装置1的上表面进行表示，示出了X－Y平面中的延伸部21的配置。另外，这里所示的延伸部21的配置是例示，实施方式并不限定于这些。
如图2A所示，阳极电极20的延伸部21在Y方向上延伸。另外，延伸部21设置有多个，且在X方向上排列配置。
如图2B所示，延伸部21例如可以设置为圆柱状。多个延伸部21例如在X方向及Y方向上排列，且相互隔开而配置。
图3A及图3B是表示第1实施方式所涉及的半导体装置1的n型半导体层11中的载流子的流动的示意图。图3A表示使半导体装置1向正向偏置的情况(导通状态)。图3B表示使半导体装置1的偏置从正向向反向(截止状态)切换的过渡期间的载流子的流动。
在图3A所示的导通状态，n型半导体层11中的电子向p型阳极层13的方向流动。另一方面，从p型阳极层13向n型半导体层11注入空穴，n型半导体层11中的电子的量与空穴的量平衡。
从n型半导体层11向阳极电极20流动的电子的路径例如有，经由n型半导体层11与p型阳极层13之间的pn结的路径、及经由阳极电极20的延伸部21中的接触部CP的路径。并且，关于妨碍电子的流动的电势，经由接触部CP的肖特基结的路径，比经由pn结的路径低。因此，n型半导体层11中的电子主要经由接触部CP向阳极电极20流动。
图3B表示从导通状态向截止状态的过渡期间中的载流子的流动。n型半导体层11中的电子经由n型阴极层15向阴极电极30排出。另一方面，空穴的排出路径，有经由p型阳极层13向阳极电极20排出的路径及经由位于n型半导体层11中的p型半导体层17及延伸部21向阳极电极20排出的路径。在该例中，n型半导体层11中的空穴中的多数经由p型半导体层17及延伸部21而排出。
在半导体装置1的导通状态下，n型半导体层11中的电子经由延伸部21的接触部CP而向阳极电极20流动。为此，与不具有延伸部21的构造相比，电子快速地向阳极电极20流动。因此，n型半导体层11中的电子量降低，与其平衡的空穴的量也变少。即，在半导体装置1中，导通状态的n型半导体层11中的载流子量降低。
另一方面，在达到截止状态的过渡期间，n型半导体层11中的空穴经由p型半导体层17向阳极电极20排出。为此，与不设置p型半导体层17的构造相比，空穴快速地向阳极电极20排出。
例如，从导通状态向截止状态的过渡期间的长度，依赖于空穴的排出时间。因此，在半导体装置1中，通过设置p型半导体层17来促进空穴的排出，而缩短过渡期间。进而，在半导体装置1中，能够减少导通状态的n型半导体层11中的载流子量。由此，能够进一步缩短载流子的排出所需要的时间。其结果，从n型半导体层11排出载流子的过渡期间得以缩短，能够降低开关损失。
图4是表示第1实施方式的变形例所涉及的半导体装置2的示意剖视图。在半导体装置2中，p型阳极层13具有例如被设置于在X方向上相邻的延伸部21之间的突出部19。
突出部19包括比n型半导体层11的n型杂质高浓度的p型杂质，并在从p型阳极层13朝向阴极电极30的方向(－Z方向)上延伸。突出部19的前端形成为，例如位于与Z方向上的p型半导体层17的下端的水平大致相同的水平。
并且，在突出部19与阳极电极20之间可以设置p+型接触层14。p+型接触层14选择性地设置在p型阳极层13与阳极电极20之间，包括比p型阳极层13的p型杂质高浓度的p型杂质。p+型接触层14与阳极电极20电连接。
图5A及图5B是表示第1实施方式的变形例所涉及的半导体装置2的n型半导体层11中的载流子的流动的示意图。图5A表示使半导体装置2正向地偏置的情况(导通状态)。图5B表示将半导体装置2的偏置从正向向反向(截止状态)切换的过渡期间中的载流子的流动。在半导体装置2中，阳极电极20中的延伸部21的X方向的间隔，例如比图1所示的半导体装置1中的延伸部21的X方向的间隔宽。
在图5A所示的导通状态，n型半导体层11中的电子主要经由延伸部21的接触部CP向阳极电极20流动。在该例中，延伸部21的X方向的间隔较宽，因此与半导体装置1相比，经由接触部CP向阳极电极20流动的电子变少。其结果，n型半导体层11中的电子的量增加，为了与其平衡，从p型阳极层13注入的空穴的量也增加。
图5B表示从导通状态向截止状态的过渡期间中的载流子的流动。n型半导体层11中的空穴，经由p型半导体层17及延伸部21向阳极电极20排出，并且经由p型阳极层13的突出部19向阳极电极20排出。此时，通过设置p+型接触层14，从p型阳极层13向阳极电极20的空穴的移动变得顺畅。由此，能够提高雪崩耐量。
在半导体装置2中，在导通状态下，n型半导体层11中的载流子量增加，因此与半导体装置1相比，能够降低正向电压。即，与半导体装置1相比，开关损失增加，但能够降低正向电压。
在本实施方式中，例如，能够通过改变阳极电极20的延伸部21的X方向的间隔，来控制正向电压和开关损失。例如，通过缩窄延伸部21的X方向的间隔，能够降低开关损失。另一方面，在加宽延伸部21的X方向的间隔时，正向电压得以降低。为此，能够通过适当调整延伸部21的X方向的间隔，来实现所期望的正向电压及开关特性。
另外，在半导体装置1及2中，在关断时，经由p型半导体层17及延伸部21，从n型半导体层11迅速地排出空穴。为此，在半导体装置1及2中，与不设置延伸部21的构造相比，能够提高雪崩耐量。另一方面，半导体装置1的雪崩耐量依赖于延伸部21的X方向的间隔，随着延伸部21的X方向的间隔变宽，雪崩耐量降低。因此，在半导体装置2中，能够通过在X方向上相邻的延伸部21之间设置p型阳极层13的突出部19，来促进空穴的排出，并防止雪崩耐量的降低。
图6是表示第1实施方式的另一个变形例所涉及的半导体装置3的示意剖视图。在半导体装置3中，在n型半导体层11的内部未设置p型半导体层17。即，阳极电极20的延伸部21一端位于n型半导体层11中。另外，延伸部21的位于n型半导体层11中的部分与n型半导体层11肖特基接触。
图7A及图7B是表示半导体装置3的n型半导体层11中的载流子的流动的示意图。图7A表示将半导体装置3正向地偏置的情况(导通状态)。图7B表示将半导体装置3的偏置从正向向反向(截止状态)切换的过渡期间中的载流子的流动。
在图7A所示的导通状态下，n型半导体层11中的电子主要经由延伸部21向阳极电极20流动。n型半导体层11中的电子经由延伸部21高效地向阳极电极20流动。为此，n型半导体层11中的电子的量减少，为了与其平衡，从p型阳极层13注入的空穴的量也减少。
图7B表示从导通状态向截止状态的过渡期间中的载流子的流动。n型半导体层11中的空穴经由延伸部21迅速地向阳极电极20排出。
在半导体装置3中，n型半导体层11中的载流子量降低，并且，n型半导体层11中的空穴经由延伸部21迅速地向阳极电极20排出。为此，能够缩短从导通状态向截止状态的关断时的过渡期间，并能够使开关损失进一步降低。
(第2实施方式)
图8是表示第2实施方式所涉及的半导体装置4的示意剖视图。如图8所示，半导体装置4包括位于p型半导体层17中的金属层23。金属层23设置为，与阳极电极20的延伸部21相连。金属层23例如设置为与n型半导体层11不接触。
金属层23设置为，与p型半导体层17肖特基接触。例如，金属层23，至少在与p型半导体层17接触的部分，包括具有比延伸部21中的与n型半导体层11接触的部分中所包括的金属的功函数小的功函数的金属。金属层23例如至少在与p型半导体层17接触的部分包括钛(Ti)、钽(Ta)及钼(Mo)中的某一种。
图9A及图9B是表示第2实施方式所涉及的半导体装置4的n型半导体层11中的载流子的流动的示意图。图9A表示将半导体装置4正向地偏置的情况(导通状态)。图9B表示将半导体装置4的偏置从正向向反向(截止状态)切换的过渡期间中的载流子的流动。
在图9A所示的导通状态下，n型半导体层11中的电子经由延伸部21的接触部CP向阳极电极20流动。为此，能够降低n型半导体层11中的电子量。与此相对应，从p型阳极层13向n型半导体层11注入的空穴的量也降低。进而，通过在金属层23与p型半导体层17之间形成的肖特基结，抑制从p型半导体层17向n型半导体层11的空穴注入。
图9B表示从导通状态向截止状态的过渡期间中的载流子的流动。n型半导体层11中的空穴主要经由p型阳极层13向阳极电极20排出。经由p型半导体层17向阳极电极20排出的空穴的量，通过金属层23而降低。另外，n型半导体层11中的电子经由n型阴极层15向阴极电极30排出。
在半导体装置4中，通过降低导通状态中的n型半导体层11中的载流子量，能够降低从导通状态向截止状态转移的过渡期间中的开关损失。另外，能够通过抑制从p型半导体层17向n型半导体层11的空穴注入来避免电流集中，能够提高半导体装置4的耐压。
(第3实施方式)
图10是表示第3实施方式所涉及的半导体装置5的示意剖视图。半导体装置5例如是IGBT，包括作为IGBT发挥功能的部分(IGBT区域)及作为FRD(Fast Recovery Diode)发挥功能的部分(FRD区域)。
如图10所示，半导体装置5具备半导体部50、发射极电极60、集电极电极70及栅极电极80。半导体部50设置在发射极电极60与集电极电极70之间。栅极电极80配置在IGBT区域，例如设置于在半导体部50的发射极电极60侧的表面设置的栅极沟道GT的内部。栅极电极80例如设置有多个，并沿着半导体部50的表面而配置。
另外，栅极电极80例如可以构成为，包括沿着半导体部50的表面而配置的多个部分。即，栅极电极80可以是通过未图示的部分相连的一体的电极。
半导体部50包括n型基底层51、p型基底层53、n型发射极层55、p型接触层56、n型缓冲层57及p型集电极层59。
p型基底层53设置在n型基底层51与发射极电极60之间。n型发射极层55选择性地设置在p型基底层53与发射极电极60之间。p型接触层56选择性地设置在p型基底层53与发射极电极60之间。n型发射极层55及p型接触层56沿着半导体部50的表面排列而配置。
n型发射极层55及p型接触层56配置于IGBT区域，并设置于在沿着半导体部50的表面的方向上相邻的栅极电极80之间。p型接触层56包括比p型基底层53的p型杂质高浓度的p型杂质。
发射极电极60覆盖半导体部50的表面，并与n型发射极层55及p型接触层56接触。发射极电极60经由n型发射极层55及p型接触层56而与p型基底层53电连接。
栅极电极80配置为隔着栅极绝缘膜83而与n型基底层51、p型基底层53及n型发射极层55相对。另外，栅极电极80通过层间绝缘膜85而与发射极电极60电绝缘。
发射极电极60具有设置于FRD区域的延伸部61。延伸部61贯穿p型基底层53地在朝向集电极电极70的方向(－Z方向)上延伸。
半导体部50还包括在n型基底层51中设置的p型半导体层63。p型半导体层63在FRD区域中配置在与p型基底层53分离的位置。
发射极电极60的延伸部61设置为与p型半导体层63相连。延伸部61在p型基底层53与p型半导体层63之间包括与n型基底层51接触的接触部CP。延伸部61在接触部CP包括与n型基底层51肖特基接触的材料。
n型缓冲层57设置在n型基底层51与集电极电极70之间。n型缓冲层57包括比n型基底层51的n型杂质高浓度的n型杂质。n型缓冲层57设置为，例如在FRD区域与集电极电极70接触。另外，在n型缓冲层57与集电极电极70之间，可以设置n+型接触层58。n+型接触层58包括比n型缓冲层57的n型杂质高浓度的n型杂质，并与集电极电极70电连接。
p型集电极层59在IGBT区域设置于n型缓冲层57与集电极电极70之间。p型集电极层59包括比p型基底层53的p型杂质高浓度的p型杂质。p型集电极层59设置为，例如与集电极电极70接触。
本实施方式所涉及的半导体装置5，能够在FRD部从导通状态向截止状态切换的过渡期间，将n型基底层51中的空穴经由p型半导体层63及延伸部61向发射极电极60排出。由此，能够降低半导体装置5中的开关损失。
这里，以包括图1所示的构造的IGBT为例进行了说明，但实施方式并不限定于此。例如，可以应用图4、图6及图8所示的构造，也能够与MOSFET组合。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子提示的，意图不是限定发明的范围。这些新的实施方式能够以其他各种各样的方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。这些实施方式及其变形，包含在发明的范围、主旨中，并且包含在权利要求书记载的发明及其等同的范围中。

Claims (15)

1.一种半导体装置，具备：
第1电极；
第2电极，配置在与上述第1电极对置的位置；以及
半导体部，设置在上述第1电极与上述第2电极之间，包括第1导电型的第1半导体层，
上述半导体部还包括：第2导电型的第2半导体层，设置在上述第1半导体层与上述第1电极之间；以及第2导电型的第3半导体层，选择性地设置在上述第1半导体层中，配置在与上述第2半导体层分离的位置，
上述第1电极具有延伸部，该延伸部与上述第2半导体层电连接，贯穿上述第2半导体层地在朝向上述第2电极的第1方向上延伸，并与上述第3半导体层连接。
2.根据权利要求1所述的半导体装置，其中，
上述第1电极与上述第2半导体层接触并电连接。
3.根据权利要求1所述的半导体装置，其中，
上述延伸部，在位于上述第2半导体层与上述第3半导体层之间的部分与上述第1半导体层肖特基连接。
4.根据权利要求1所述的半导体装置，其中，
上述半导体部还包括第1导电型的第4半导体层，该第1导电型的第4半导体层设置在上述第1半导体层与上述第2电极之间，包括比上述第1半导体层的第1导电型的杂质高浓度的第1导电型杂质。
5.根据权利要求4所述的半导体装置，其中，
上述第2电极与上述第4半导体层接触并电连接。
6.根据权利要求1所述的半导体装置，其中，
上述第1电极的上述延伸部包括位于上述第3半导体中的第1部分及与上述第1半导体层接触的第2部分，
上述第1部分包括第1金属，上述第2部分包括与上述第1金属相比功函数更大的第2金属。
7.根据权利要求6所述的半导体装置，其中，
上述第2部分与上述第1半导体层肖特基连接。
8.根据权利要求1所述的半导体装置，其中，
上述第1电极的上述延伸部及上述第3半导体层分别被设置有多个，
上述延伸部，在沿着上述第1半导体层与上述第2半导体层的边界的第2方向上排列，并分别与上述第3半导体层连接，
上述第2半导体层具有在上述第1方向上延伸的突出部，该突出部设置在被配置于在上述第2方向上相邻的位置的2个延伸部之间。
9.根据权利要求8所述的半导体装置，其中，
上述半导体部还包括第5半导体层，该第5半导体层选择性地设置在上述第1电极与上述第2半导体层之间，并包括比上述第2半导体层的第2导电型杂质高浓度的第2导电型的杂质，
上述第5半导体层位于上述第1电极与上述突出部之间。
10.根据权利要求9所述的半导体装置，其中，
上述第1电极与上述第5半导体层接触并电连接。
11.一种半导体装置，具备：
第1电极；
第2电极，配置在与上述第1电极对置的位置；以及
半导体部，设置在上述第1电极与上述第2电极之间，包括第1导电型的第1半导体层，
上述半导体部还包括设置在上述第1半导体层与上述第1电极之间的第2导电型的第2半导体层，
上述第1电极具有延伸部，该延伸部与上述第2半导体层电连接，并贯穿上述第2半导体层地在朝向上述第2电极的第1方向上延伸，
上述延伸部具有位于上述第1半导体层中的端部。
12.一种半导体装置，具备：
第1电极；
第2电极，配置在与上述第1电极对置的位置；
半导体部，设置在上述第1电极与上述第2电极之间，包括第1导电型的第1半导体层；以及
控制电极，设置在上述第1电极与上述半导体部之间，隔着第1绝缘膜而与上述半导体部电绝缘，并隔着第2绝缘膜而与上述第1电极电绝缘，
上述半导体部还包括：第2导电型的第2半导体层，选择性地设置在上述第1半导体层与上述第1电极之间；第2导电型的第3半导体层，选择性地设置在上述第1半导体层中，被配置在与上述第2半导体层分离的位置；以及第1导电型的第6半导体层，选择性地设置在上述第2半导体层与上述第1电极之间，
上述第1电极与上述第2半导体层及上述第6半导体层电连接，
上述控制电极隔着上述第1绝缘膜配置在与上述第1半导体层、上述第2半导体层的一部分及上述第6半导体层相对的位置，
上述第2半导体层位于上述第3半导体层与上述第1电极之间，
上述第1电极具有延伸部，该延伸部贯穿上述第2半导体层地在朝向上述第2电极的第1方向上延伸，并与上述第3半导体层连接，
在上述延伸部的附近未设置上述第6半导体层。
13.根据权利要求12所述的半导体装置，其中，
上述半导体部还具备第2导电型的第7半导体层，该第2导电型的第7半导体层选择性地设置在上述第1半导体层与上述第2电极之间，
上述第7半导体层位于上述第6半导体层与上述第2电极之间，
在上述第3半导体层与上述第2电极之间未设置上述第7半导体层。
14.根据权利要求13所述的半导体装置，其中，
上述半导体部还具备第1导电型的第8半导体层，该第1导电型的第8半导体层设置在上述第1半导体层与上述第2电极之间，并包括比上述第1半导体层的第1导电型杂质高浓度的第1导电型杂质，
上述第7半导体层位于上述第8半导体层与上述第2电极之间，并与上述第2电极电连接。
15.根据权利要求14所述的半导体装置，其中，
上述半导体部在未设置上述第7半导体层的部分还具备第1导电型的第9半导体层，该第1导电型的第9半导体层设置在上述第8半导体层与上述第2电极之间，并包括比上述第8半导体层的第1导电型杂质高浓度的第1导电型杂质，
上述第2电极与上述第9半导体层电连接。
CN201910022345.XA 2018-09-14 2019-01-10 半导体装置 Pending CN110911398A (zh)

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