CN110907803A

CN110907803A - Method for realizing 7816 interface communication synchronous test on ATE

Info

Publication number: CN110907803A
Application number: CN201911148824.2A
Authority: CN
Inventors: 姜京哲; 鲁小妹; 盛娜; 王慧
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2020-03-24

Abstract

The invention discloses a method for realizing 7816 interface communication synchronous test on ATE, which can realize synchronous test on asynchronous chips on ATE, thereby realizing the synchronous test of 7816 interface communication in mass production.

Description

Method for realizing 7816 interface communication synchronous test on ATE

Technical Field

The invention belongs to the field of mass production test of integrated circuit chips, and particularly relates to a method for realizing 7816 interface communication synchronous test on ATE in the mass production process.

Background

The 7816 interface is a communication interface commonly used in IC cards, and in the mass production test flow, the 7816 interface communication must be tested. In the test process, the ATE needs to simulate a card reader to test the 7816 interface, and in the face of instructions with short processing time, the ATE can realize synchronous test, but in the face of instructions with long processing time, the ATE synchronous test is difficult.

The difficulty of realizing 7816 interface communication synchronization test on ATE at present is the following 2 points:

1 due to the difference in internal clock frequencies of different chips, the time required to process the same instruction is different, which results in asynchronous responses from different chips. At present, most ATE provides a matching function and can synchronously test asynchronous responses, but the function requires that the time difference of the asynchronous responses is required to be within a range of 65536 clocks, and if the asynchronous time difference exceeds 65536 clocks, the ATE can be judged to be invalid for a chip which responds slowly, so that misdetection is caused. When facing to an instruction with a long processing time, the difference between the chips may exceed 65536 clock cycles, for example, the execution time of a certain instruction is 500ms, the difference between the internal clock frequencies of the chips is 5%, the clock frequency of the 7816 interface is 10MHz (100ns), and the difference between the chips is: (500ms 5%)/100 ns 250000 clocks, which exceeds the 65536 clock limit, ATE cannot perform synchronous testing, and this problem needs to be solved in mass production testing.

2 in the process of processing the instruction by the chip, if the instruction processing time is long, the chip may return NULL (0x60) before the processing is finished, so as to prompt that the card reader chip is still in the working process, the return is obtained by ATE, and the ATE determines that the chip is failed due to inconsistency with normal response data, which causes mistesting, and the occurrence of this situation needs to be avoided in mass production testing.

Disclosure of Invention

The invention aims to realize 7816 interface communication synchronous test on ATE, and the specific scheme is as follows:

1ATE sends instructions to each chip;

2ATE stop 7816 interface clock:

1) under the state that ATE stops 7816 interface clock, the interior of each chip can automatically process the received instruction, and prepare the response information, but will not send out response to the outside;

2) if the instruction processing time is long, the chip may return NULL (0x60) before the processing is finished, but in the state of stopping 7816 interface clock, the chip will not return NULL (0x60) to the outside; after the instruction processing is finished, the normal response refreshes 7816 the content of the sending register, NULL (0x60) is cleared, and only the normal response is reserved.

3, the time for stopping 7816 interface clock needs to be controlled, and the stopping time is ensured to be enough for all chips to process the instruction;

4ATE resumes 7816 interface clock, each chip sends out ready response, and the asynchronous condition between each chip is almost eliminated, so that ATE can perform synchronous test.

Drawings

FIG. 1 is a flow chart of a test method

FIG. 2 is a 2-chip simultaneous measurement waveform diagram using the method

FIG. 3 is a 2-chip simultaneous measurement waveform diagram without using the method

Detailed Description

The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings.

The expected time for processing a certain instruction by the chip is about 500ms, the internal clock frequency difference between the chips is 5%, the clock frequency of the 7816 interface is 10MHz (100ns), the difference of asynchronous response between the chips can reach ((500ms 5%)/100 ns) ═ 250000 clocks, and ATE cannot be directly tested synchronously, so that the asynchronous difference needs to be reduced by the method to realize synchronous testing, fig. 1 is a flow chart of the testing method, and the implementation method is as follows according to the flow chart:

1ATE sends instructions to 2 chips;

2ATE stops 7816 interface clock of 2 chips;

3, controlling the time for stopping 7816 interface clock:

the expected time for processing the instruction by the chip is about 500ms, the internal clock frequency difference between the chips is 5%, the time for stopping the 7816 interface clock is 500ms +500ms 5% 525ms, at least the 7816 interface clock is required to be stopped 525ms, so that 2 chips can be guaranteed to have enough time to process the instruction, and response information is prepared (0x 9000);

in the period of stopping the 7816 interface clock, if the chip generates NULL (0x60), the chip will not send out, after the chip processes the instruction, the content in the 7816 sending register will be refreshed, and the normal response information (0x9000) will replace the NULL (0x 60).

The 4ATE recovers 7816 interface clocks, 2 chips return ready responses, the responses of the 2 chips are basically synchronous and do not return NULL (0x60), and at this time, the ATE can perform synchronous testing on the responses of the 2 chips by using a "matching" function, as shown in fig. 2. Comparing fig. 2 and 3, it can be seen that using the present method, the asynchronous differences are substantially eliminated, allowing the ATE to perform synchronous testing.

Claims

1. A method for realizing 7816 interface communication synchronous test on ATE can realize parallel test for asynchronous chips on ATE, the method mainly includes following steps:

1) the ATE sends instructions to each tested chip;

2) stopping 7816 interface clock;

3) recovering 7816 interface clock;

4) and the ATE receives the response of each tested chip and performs synchronous test.

2. The method of claim 1, wherein: all chips which respond asynchronously can automatically process the received instruction in each chip and cannot send the response in the state of stopping 7816 interface clocks.

3. The method of claim 1, wherein: after all chips process the instructions, the 7816 interface clock is recovered, all chips output responses, the asynchronous condition among the chips is eliminated, and the ATE can carry out synchronous testing.