CN110879625B - CMOS voltage reference circuit with ultralow linear sensitivity - Google Patents

CMOS voltage reference circuit with ultralow linear sensitivity Download PDF

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CN110879625B
CN110879625B CN201911280123.4A CN201911280123A CN110879625B CN 110879625 B CN110879625 B CN 110879625B CN 201911280123 A CN201911280123 A CN 201911280123A CN 110879625 B CN110879625 B CN 110879625B
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nmos transistor
intrinsic
drain
voltage
intrinsic nmos
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CN110879625A (en
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吴建辉
吴志强
谢祖帅
周全才
瞿剑
李红
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Southeast University
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Abstract

The invention discloses a CMOS voltage reference circuit with ultra-low linear sensitivity, which comprises: a first intrinsic NMOS transistor M1, a second intrinsic NMOS transistor M2, and a standard NMOS transistor M3, wherein the input signal VDD is connected to the drain of the first intrinsic NMOS transistor M1, the gate of the first intrinsic NMOS transistor M1 is connected to the gate and drain of the standard NMOS transistor M3, respectively, and the drain of the standard NMOS transistor M3 is connected to the output reference voltage VREFConnected, and the source of the first intrinsic NMOS transistor M1 is connected to the drain of the second intrinsic NMOS transistor M2; the gate of the second intrinsic NMOS transistor M2 is connected to the ground signal GND, and the source of the second intrinsic NMOS transistor M2 is connected to the drain of the standard NMOS transistor M3 and the output reference voltage VREFConnecting; the source of the standard NMOS transistor M3 is connected to the ground signal GND. The invention can effectively reduce the linear sensitivity of the voltage reference, thereby inhibiting the influence of the power supply voltage on the voltage reference, and simultaneously reducing the chip area so as to save the circuit cost.

Description

CMOS voltage reference circuit with ultralow linear sensitivity
Technical Field
The invention relates to a CMOS voltage reference circuit with ultralow linear sensitivity, belonging to the technical field of voltage reference.
Background
Voltage reference modules are an important basic module in both analog and digital-analog hybrid circuits, and the voltage reference needs to provide a reference voltage that does not change with process, supply voltage, and temperature. With the development of high integration and low power consumption, the design of voltage reference is more strict. At low voltages, the design of voltage references has more difficulties.
The main voltage references can now be divided into bandgap reference voltages and CMOS reference voltages. The BJT device is required to be used in the band-gap reference voltage, and the band-gap reference circuit is difficult to work under the condition of low voltage due to the influence of the characteristics of the BJT device. Voltage reference circuits operating at low voltages therefore typically employ CMOS architectures. The most traditional CMOS voltage reference is a 2T reference source, and the main idea is that the current flowing through an intrinsic NMOS and a standard NMOS are equal, so that an expression of reference voltage is obtained, the expression of the reference voltage comprises a positive temperature coefficient term formed by the difference value of threshold voltages of two different types of tubes and a negative temperature term formed by adjusting the sizes of the tubes, and the reference voltage with zero temperature coefficient is obtained by adjusting the sizes of the tubes. However, because the drain of the intrinsic NMOS tube of the structure is directly connected with VDD, when VDD is found to change, the reference voltage also changes due to the channel length modulation effect, and the linear sensitivity of the structure is high.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a CMOS voltage reference circuit with ultralow linear sensitivity, wherein an intrinsic NMOS is connected in series with a drain of an original intrinsic NMOS to enable the drain of the original intrinsic NMOS to be in a low-resistance state, so that the influence of a channel modulation effect is reduced, and the linear sensitivity of the circuit is reduced.
The invention specifically adopts the following technical scheme to solve the technical problems:
an ultra-low linear sensitivity CMOS voltage reference circuit comprising: a first intrinsic NMOS transistor M1, a second intrinsic NMOS transistor M2, and a standard NMOS transistor M3, wherein the input signal VDD is connected to the drain of the first intrinsic NMOS transistor M1, the gate of the first intrinsic NMOS transistor M1 is connected to the gate and drain of the standard NMOS transistor M3, respectively, and the drain of the standard NMOS transistor M3 is connected to the output reference voltage VREFConnected, and the source of the first intrinsic NMOS transistor M1 is connected to the drain of the second intrinsic NMOS transistor M2; the gate of the second intrinsic NMOS transistor M2 is connected to the ground signal GND, and the source of the second intrinsic NMOS transistor M2 is connected to the drain of the standard NMOS transistor M3 and the output reference voltage VREFConnecting; the source of the standard NMOS transistor M3 is connected to the ground signal GND.
Further, as a preferred technical solution of the present invention: the first intrinsic NMOS transistor M1 and the second intrinsic NMOS transistor M2 are both intrinsic NMOS transistors with adjustable width-to-length ratios.
By adopting the technical scheme, the invention can produce the following technical effects:
the CMOS voltage reference circuit with ultra-low linear sensitivity provided by the invention has the advantages that the intrinsic NMOS tube is connected in series on the basis of the drain electrode of the traditional 2T CMOS voltage reference, so that the drain electrode is in a low-resistance state, the influence of the power supply voltage on the output voltage is reduced, meanwhile, a current mirror is not used in the circuit, the influence caused by mismatch of the current mirror is eliminated, the dynamic adjustment process is also realized through the added MOS tube, and because the adjustment loop of the circuit is simple, the circuit can work under a lower power supply voltage, and all the MOS tubes work in a sub-threshold region, so that the power consumption is reduced.
Therefore, the invention can realize lower linear sensitivity voltage reference and reduce the chip area so as to save the circuit cost; the invention also eliminates the problems that may be caused by the mismatch of the current mirrors. The circuit is used as a basic unit of an analog circuit, can realize a voltage reference with lower linear sensitivity, and can be applied to low-voltage circuits such as energy collection circuits.
Drawings
FIG. 1 is a topology diagram of an ultra low linear sensitivity CMOS voltage reference circuit of the present invention.
Fig. 2 is a graph of the linear sensitivity characteristic of a CMOS voltage reference implemented using the present invention.
Fig. 3 is a partial enlarged view of the linear sensitivity characteristic of a CMOS voltage reference implemented using the present invention.
Fig. 4 is a PSRR characteristic graph of a CMOS voltage reference implemented using the present invention.
Fig. 5 is a graph of the temperature characteristic of a CMOS voltage reference implemented using the present invention.
Detailed Description
The following describes embodiments of the present invention with reference to the drawings.
As shown in fig. 1, the present invention designs an ultra-low linear sensitivity CMOS voltage reference circuit, which includes: first intrinsic NMThe OS transistor M1, the second intrinsic NMOS transistor M2, the standard NMOS transistor M3, the circuit further comprises an input signal VDD and an output reference voltage VREF。
The input signal VDD of the CMOS voltage reference circuit is connected with the drain electrode of a first intrinsic NMOS tube M1, the grid electrode of the first intrinsic NMOS tube M1 is respectively connected with the grid electrode and the drain electrode of a standard NMOS tube M3, and the drain electrode of the standard NMOS tube M3 is connected with an output reference voltage VREFConnected, and the source of the first intrinsic NMOS transistor M1 is connected to the drain of the second intrinsic NMOS transistor M2; the gate of the second intrinsic NMOS transistor M2 is connected to the ground signal GND, and the source of the second intrinsic NMOS transistor M2 is connected to the drain of the standard NMOS transistor M3 and the output reference voltage VREFConnecting; the source of the standard NMOS transistor M3 is connected to the ground signal GND.
Further, the first intrinsic NMOS transistor M1 and the second intrinsic NMOS transistor M2 are both intrinsic NMOS transistors with adjustable width-to-length ratios. The low linear sensitivity CMOS voltage reference circuit provided by the invention can effectively reduce the linear sensitivity of the voltage reference, thereby inhibiting the influence of the power supply voltage on the voltage reference, reducing the layout area and saving the cost. The proposed circuit structure can be applied to low supply voltage applications such as energy harvesting.
The operation principle of the simulation method is described in detail below with reference to specific circuits and simulation results.
As shown in FIG. 1, the CMOS voltage reference circuit of the present invention mainly comprises two intrinsic NMOS transistors and one standard NMOS transistor, and all the transistors are operated in the sub-threshold region. Since the currents flowing through the first and second intrinsic NMOS transistors M1 and M2 are equal, the current formula of the subthreshold region is shown in formula (1):
Figure BDA0002316525150000031
where K ═ W/L denotes the width-to-length ratio of the tube, μ denotes the mobility of the transistor, CoxRepresenting the oxide capacitance per unit area, m represents the subthreshold slope factor, VTkT/q denotes the thermal voltage, where k, T and q are Boltzmann, respectivelyConstant, absolute temperature and base charge. VGSAnd VTHRespectively, the gate-source voltage and the threshold voltage of the transistor.
The current equality of the first intrinsic NMOS transistor M1 and the second intrinsic NMOS transistor M2 can be expressed as formula (2):
Figure BDA0002316525150000032
wherein K2，K3Respectively showing the width-length ratio of the second intrinsic NMOS transistor M2 and the standard NMOS transistor M3; mu.s2，μ3Respectively representing the mobility of the second intrinsic NMOS transistor M2 and the standard NMOS transistor M3; cox2，Cox3Respectively showing the oxide capacitance per unit area of the second intrinsic NMOS transistor M2 and the standard NMOS transistor M3; m is2，m3Respectively representing the sub-threshold slope factors of the second intrinsic NMOS transistor M2 and the standard NMOS transistor M3; vTH2，VTH3Respectively representing the threshold voltages of the second intrinsic NMOS transistor M2 and the standard NMOS transistor M3; vREFRepresenting the output reference voltage.
The output reference voltage V can be obtained by simplifying the formula (2)REFIs shown in equation (3):
Figure BDA0002316525150000033
wherein suppose Cox2＝Cox3，m＝m2＝m3。VREFIs positively correlated with temperature by adjusting K2And K3The second term can be made negatively temperature dependent, and the positive temperature coefficient term and the negative temperature term cancel each other out to obtain a zero temperature coefficient voltage reference. A first intrinsic NMOS transistor M1 is connected in series with the drain terminal of the second intrinsic NMOS transistor M2, by biasing the gate of the first intrinsic NMOS transistor M1 and outputting a reference voltage VREFThe first intrinsic NMOS transistor M1 is connected to operate in the saturation region, and the first intrinsic NMOS transistor M1 has a large current source impedance and has a power supply rejection effect on the point a. Standard of meritThe NMOS transistor M3 is diode-connected to low resistance state from point A to point VREFThe influence of the voltage reference circuit also has a certain inhibiting effect, and an ultra-low linear sensitivity CMOS voltage reference circuit can be obtained through double inhibition. And by connecting the gate of the first intrinsic NMOS transistor M1 with the output reference voltage VREFDirectly connected, the gate-drain parasitic capacitance of the first intrinsic NMOS transistor M1 will generate a zero pole pair VREFThere is a regulating effect to improve the power supply rejection ratio of the circuit. And meanwhile, the circuit eliminates the influence possibly brought by the mismatch of the current mirror. Since all transistors are operated in the subthreshold region, the invention can be operated at a power supply voltage as low as 0.3V.
Fig. 2 is a graph of the linear sensitivity characteristic of the CMOS voltage reference implemented by the present invention, and it is apparent from the graph that the voltage reference proposed by the present invention has lower linear sensitivity.
Fig. 3 is a partially enlarged view of a linear sensitivity characteristic curve of a CMOS voltage reference implemented by the present invention, where the linear sensitivity of the CMOS voltage reference used in the document published by 2012JSSC is 0.3%/V, the linear sensitivity of the CMOS voltage reference used in the document published by 2019JSSC is 0.079%/V, and the linear sensitivity of the CMOS voltage reference used in the present invention is 0.006%/V. Simulation results show that the CMOS voltage reference has lower linear sensitivity.
Fig. 4 is a PSRR characteristic graph of a CMOS voltage reference implemented by the present invention, in which the power supply rejection ratio at a frequency of 10Hz is 83.39dB, the power supply rejection ratio at a frequency of 1kHz is 76.91dB, and the power supply rejection ratio at a frequency of 1MHz is 71.66 dB. Simulation results show that the CMOS voltage reference has a high power supply rejection ratio, and can effectively suppress the influence of the power supply voltage on the output voltage.
FIG. 5 is a temperature characteristic curve diagram of a CMOS voltage reference implemented by the present invention, with a temperature drift coefficient of 128.6 ppm/deg.C, satisfying the required zero temperature coefficient reference voltage.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.

Claims (2)

1. An ultra-low linear sensitivity CMOS voltage reference circuit, comprising: a first intrinsic NMOS transistor M1, a second intrinsic NMOS transistor M2, and a standard NMOS transistor M3, wherein the input signal VDD is connected to the drain of the first intrinsic NMOS transistor M1, the gate of the first intrinsic NMOS transistor M1 is connected to the gate and drain of the standard NMOS transistor M3, respectively, and the drain of the standard NMOS transistor M3 is connected to the output reference voltage VREFConnected, and the source of the first intrinsic NMOS transistor M1 is connected to the drain of the second intrinsic NMOS transistor M2; the gate of the second intrinsic NMOS transistor M2 is connected to the ground signal GND, and the source of the second intrinsic NMOS transistor M2 is connected to the drain of the standard NMOS transistor M3 and the output reference voltage VREFConnecting; the source of the standard NMOS transistor M3 is connected to the ground signal GND.
2. The ultra-low linear sensitivity CMOS voltage reference circuit of claim 1, wherein: the first intrinsic NMOS transistor M1 and the second intrinsic NMOS transistor M2 are both intrinsic NMOS transistors with adjustable width-to-length ratios.
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JPS5781622A (en) * 1980-11-07 1982-05-21 Nec Corp Current source
US4859928A (en) * 1988-12-20 1989-08-22 Tektronix, Inc. CMOS comparator bias voltage generator

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JPS5781622A (en) * 1980-11-07 1982-05-21 Nec Corp Current source
US4859928A (en) * 1988-12-20 1989-08-22 Tektronix, Inc. CMOS comparator bias voltage generator

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A 0.12–0.4 V, Versatile 3-Transistor CMOS Voltage;Arthur Campos de Oliveira等;《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS》;20181130;第65卷(第11期);第3790-3798页 *
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