CN110875242A - 半导体装置及其形成方法 - Google Patents
半导体装置及其形成方法 Download PDFInfo
- Publication number
- CN110875242A CN110875242A CN201910742708.7A CN201910742708A CN110875242A CN 110875242 A CN110875242 A CN 110875242A CN 201910742708 A CN201910742708 A CN 201910742708A CN 110875242 A CN110875242 A CN 110875242A
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- Prior art keywords
- layer
- semiconductor device
- oxide layer
- barrier layer
- forming
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Abstract
一种半导体装置及其形成方法。用于形成结合衬垫结构的方法包括在半导体装置上形成互连结构,在互连结构上形成钝化层,经由钝化层形成至少一个开口,至少在开口中形成氧化层,及在氧化层上形成衬垫金属层。互连结构的一部分由至少一个开口而曝露。
Description
技术领域
本揭示涉及一种半导体装置及一种半导体装置的形成方法。
背景技术
一半导体装置包括一或多个导电金属层以作为金属互连。导电金属层经由介电材料与多个装置元件彼此耦接。导电金属层形成于彼此上方且定位于多个装置高度。此外,半导体装置包括作为衬垫结构的一部分的最上层或顶部金属层。因此,顶部金属层可电耦接焊料凸块或其他外部元件,以便实现与半导体装置的电连接。
发明内容
本揭示的一些实施例提供一种半导体装置的形成方法,其包括在半导体装置上形成互连结构;在互连结构上形成钝化层;形成穿过钝化层的至少一个开口,其中互连结构的一部分被此开口曝露;至少在开口中形成氧化层;及在氧化层上形成衬垫金属层。
本揭示的一些实施例提供一种半导体装置,其包括互连结构、第一钝化层、氧化层及衬垫金属层。互连结构具有导电部分。第一钝化层位于导电部分上,且其内具有开口。氧化层位于导电部分的一部分上方,且至少位于第一钝化层的开口中。衬垫金属层直接位于氧化层上,且电连接至导电部分。
本揭示的一些实施例提供一种半导体装置,其包括互连结构、阻障层、氧化层及衬垫金属层。互连结构具有导电部分。阻障层电连接至导电部分。氧化层在阻障层上。衬垫金属层在氧化层上。
附图说明
本揭示案的态样在结合附图阅读时从以下详细说明中得以最佳地理解。应注意,依据行业中的标准惯例,各种特征并非按比例绘制。事实上,为了论述明晰,各种特征的尺寸可任意增大或减小。
图1是绘示依据本揭示案的一些实施例的具有结合衬垫结构的半导体装置的示意图;
图2是绘示依据本揭示案的一些实施例的用于形成半导体装置的结合衬垫结构的方法的流程图;
图3-图11是绘示根据图2的方法的制造结合衬垫结构的多个阶段的横截面的示意图;
图12是绘示依据本揭示案的一些其他实施例的结合衬垫结构的示意图;
图13是绘示依据本揭示案的又一实施例的结合衬垫结构的示意图;
图14是绘示依据本揭示案的一些实施例的晶圆处理设备的示意图;
图15是绘示依据本揭示案的一些其他实施例的形成半导体装置的结合衬垫结构的方法的流程图。
【符号说明】
10 晶圆处理设备
12 FOUP
14 装载端口
16 负载锁定腔室
18 移送腔室
19 移送机器人
20 处理腔室
22 处理腔室
24 传递腔室
26 移送腔室
27 移送机器人
28 处理腔室
30 处理腔室
32 处理腔室
34 传递腔室
100 半导体装置
102 基板
103 晶体管
1040 介电层
1040-104N 介电层
1041 介电层
1042 介电层
104N 介电层
105 导电插头
1061 蚀刻停止层
1061-106N 蚀刻停止层
1062 蚀刻停止层
106N 蚀刻停止层
108 浅沟槽隔离
110 互连结构
1121 导电部分
1121-112N 导电部分
1122 导电部分
112N 导电部分
1141 导线
1141-114N 导线
1142 导线
114N 导线
1161 导电通孔
1161-116N 导电通孔
1162 导电通孔
116N 导电通孔
120 结合衬垫结构
130 第一钝化层
140 阻障层
150 氧化层
160 衬垫金属层
170 第二钝化层
212N 导电部分
220 结合衬垫结构
230 第一钝化层
240 阻障层
250 氧化层
260 衬垫金属层
270 第二钝化层
312N 导电部分
320 结合衬垫结构
330 第一钝化层
340 阻障层
350 氧化层
360 衬垫金属层
370 第二钝化层
1032 栅极结构
1034 源极/漏极区域
1036 通道区域
1042 凹槽
1302 第一层
1304 第二层
1402 顶表面
1404 顶表面
1502 顶表面
1702 第一层
1704 第二层
3402 第一层
3404 第二层
3406 第三层
M1 方法
M2 方法
S10 操作
S20 操作
S30 操作
S32 操作
S34 操作
S40 操作
S50 操作
S60 操作
S70 操作
具体实施方式
以下揭示案提供众多不同实施例或实例以用于实施本案提供标的的不同特征。下文描述元件及布置的特定实例以简化本揭示案的一些实施例。当然,此仅是实例,并非意欲限制。例如,下文描述中第一特征于第二特征上方或之上的形成可包括第一特征与第二特征直接接触而形成的实施例;及亦可包括第一特征与第二特征之间可能形成额外特征,以使得第一特征与第二特征可不直接接触的实施例。此外,本揭示案的一些实施例可在各种实例中重复元件符号及/或字母。此重复是以简单与明晰为目的,且其自身不规定本文论述的各种实施例及/或配置之间的关系。
而且,本案可能使用诸如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等等空间相对术语以便于描述,以描述一个元件或特征与另一(或更多个)元件或特征的关系,如附图中所示。除附图中绘示的定向之外,空间相对术语意欲包括元件在使用或操作中的不同定向。设备可能以其他方式定向(旋转90度或以其他定向),且本案所使用的空间相对描述词可由此进行同样理解。
如本文中所使用,“大约”、“约”、“大体上”或“近似”一般应意谓与给定值或范围相差在20%内、10%内,或5%内。本文给定的数值量是近似的,即意谓在无明确表述的情况下可推论术语“大约”、“约”、“大体上”或“近似”。
半导体装置中的结合衬垫结构可包括多个层,以共同实现与半导体装置的电连接。然而,结合衬垫结构制造期间的湿气及/或污染可触发晶须缺陷问题,此问题危害半导体装置的效能。此外,结合衬垫结构中内应力的局部化可为晶须缺陷问题的另一原因。晶须缺陷问题是结合衬垫结构的金属表面上可出现晶须状突出物,从而导致对半导体装置的短路及/或其他损坏的现象。此外,晶须缺陷问题亦可由于结合衬垫结构中存在的压缩应力而产生。因此,为竭力妥当解决上文提及的问题,依据本揭示案如下所述的多个实施例介绍了一种半导体装置及形成此半导体装置的方法。
参看图1,图1是绘示依据本揭示案的一些实施例的半导体装置100的示意图,此半导体装置具有结合衬垫结构120。在一些实施例中,半导体装置100可包括被动元件(例如,电阻器、电容器、感应器及保险丝)、主动元件(例如,P-通道场效晶体管(P-channel fieldeffect transistor;PFET)、N-通道场效晶体管(N-channel field effect transistor;NFET)、金属氧化物半导体场效晶体管(metal-oxide-semiconductor field effecttransistor;MOSFET)、互补金属氧化物半导体(complementary metal-oxide-semiconductor;CMOS)晶体管、高电压晶体管及高频晶体管)、其他适合的元件,及/或上述各者的组合。应注意,熟悉本领域技术者可理解,上文提及的实例仅提供用于说明的目的,且并非意谓以任何方式限制本揭示案的一些实施例。其他的电路***亦可基于各种设计而包含在半导体装置100中。
如图1所示,半导体装置100具有基板102。在一些实施例中,基板102可由硅、锗适合的第III-V族化合物材料(例如,砷化锗(GaA))、上述各者的组合等形成。在一些实施例中,基板102可包括绝缘体上硅(silicon on insulator;SOI)结构。详细而言,SOI结构可具有形成于绝缘体层上的诸如硅的半导体材料层。绝缘体层可包括埋入式氧化物(buriedoxide;BOX)层及/或氧化硅层。应注意,基板102可包括:诸如锗的另一元素半导体;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及GaInAsP,或上述各者的组合。此外,亦可采用其他类型的基板,如多层基板、梯度基板,或上述各者的组合。
在一些实施例中,如晶体管103的主动元件形成于基板102上。晶体管包括栅极结构1032、源极/漏极区域1034,及通道区域1036以放大或切换电子信号及电功率。在一些实施例中,浅沟槽隔离(shallow trench isolation;STI)108邻近于晶体管103以阻止晶体管103与邻近元件之间的电流泄漏。在一些实施例中,介电层1040经配置以作为间金属层围绕晶体管103,且可包括氧化物材料、极低介电常数介电质(extreme low k dielectric;ELK)、绝缘材料、上述各者的组合等。在一些实施例中,蚀刻停止层1061经配置在介电层1040上,且可包括碳化硅(silicon carbide;SiC)或其他适合的材料。SiC是可在高温下及/或高电压下稳定操作的材料,且因此适合于应用至半导体装置100。
在一些实施例中,半导体装置100的互连结构110可包括多个介电层1040、1041、1042……104N(1040-104N)、蚀刻停止层1061、1062……106N(1061-106N)、导电部分1121、1122……112N(1121-112N)、导线1141、1142……114N(1141-114N),及导电通孔1161、1162……116N(1161-116N)。导电部分1121-112N、导线1141-114N,及/或导电通孔1161-116N可经由介电层1040-104N及/或蚀刻停止层1061-106N路由,以在晶体管103与外部电子构件之间形成连接。例如,如图1所示,介电层1040、蚀刻停止层1061、介电层1041、蚀刻停止层1062、介电层1042、蚀刻停止层106N,及介电层104N以自下而上的序列经排列及堆叠。导电插头105经由介电层1040及/或蚀刻停止层1061路由以形成导电部分1121与栅极结构1032之间及/或导线1141与源极/漏极区域1034之间的连接。导电部分1121及导线1141可耦接至彼此。导电通孔1162可桥接导线1141与导线1142。如上文提及的类似结构配置亦可应用于导线1142、导电通孔116N、导线114N、导电部分1122,及导电部分112N。在一些实施例中,导电插头105、导线1141-114N,及导电通孔1161-116N亦可沿非线性路径排列,以在晶体管103与结合衬垫结构120之间形成连接。在一些实施例中,导电插头105、导线1141-114N、导电通孔1161-116N及导电部分1121-112N可包括基于金属的材料,例如铜(Cu),此等材料具有优良导电特性。
在一些实施例中,互连结构110可通过镶嵌制程、双镶嵌制程、上述两者的组合或类似者而形成。例如,沟槽蚀刻制程可经执行以形成多个沟槽。随后,类似于铜的金属材料可提供在沟槽中作为电传输介质。因此,互连结构110可形成为半导体装置100中积体电路的一部分。
在一些实施例中,第一钝化层130定位于互连结构110上。第一钝化层130可包括氧化物、氮化物、未掺杂硅玻璃(undoped silicate glass;USG)、上述各者的组合等。在一些实施例中,第二钝化层170定位于第一钝化层130上。第二钝化层170可包括氧化物、氮化物、未掺杂硅玻璃(undoped silicate glass;USG)、上述各者的组合等。第一钝化层130及/或第二钝化层170经配置以保护下层元件免受外界环境的腐蚀、刮划,及/或损害。在一些实施例中,第一钝化层130可包括多层结构,如第一层1302及第二层1304。例如,第一层1302可包括氮化硅(silicon nitride;SiN)及第二层1304可包括未掺杂硅玻璃(undoped silicateglass;USG)。在一些实施例中,第二钝化层170可包括多层结构,如第一层1702及第二层1704。例如,第一层1702可包括未掺杂硅玻璃(undoped silicate glass;USG)及第二层1704可包括氮化硅(silicon nitride;SiN)。应注意,第一钝化层130及第二钝化层170的结构配置是实例,且并非意欲限制。
在一些实施例中,结合衬垫结构120经由第一钝化层130及第二钝化层170而配置,以使得半导体装置100可经由结合衬垫结构120结合并连接至外部电子构件。更特定而言,结合衬垫结构120(通过矩形虚线强调)可为堆叠结构,此结构包括导电部分112N、第一钝化层130、阻障层140、氧化层150、衬垫金属层160,及第二钝化层170。由于氧化层150可分隔阻障层140与衬垫金属层160,因此可阻隔并防止由阻障层140产生的污染及/或湿气在衬垫金属层160上产生负面影响,诸如在金属层160上产生晶须缺陷。应注意,结合衬垫结构120中的上文提及的元件的结构配置可基于各种设计而调整。此外,下文将介绍关于结合衬垫结构120的更详细的描述。
参看图2,图2是绘示依据本揭示案的一些实施例的用于形成结合衬垫结构120的方法M1的流程图。更特定而言,图2绘示用于制造半导体装置100中所含的结合衬垫结构120的一示例性实施例。方法M1可包括半导体装置100的制造制程中的相应部分。应注意,下文介绍的每一方法仅为实例,且并非意欲限制本揭示案的一些实施例中超出专利申请范围中明确所述范围以外的内容。可在每一方法之前、期间及之后提供额外操作。描述的一些操作可在额外的制造制程实施例中被替换、消除,或移动。此外,为了明晰且易于解释,附图的一些元件已简化。
图3至图10是绘示根据图2的方法M1制造半导体装置100中的结合衬垫结构120的多个阶段的横截面示意图。更特定而言,下文将结合图3至图11中绘示的横截面,引述图2中的操作S10至S70,以便共同描述制造细节及结合衬垫结构120的结构。
参看图3。提供介电层104N。更特定而言,介电层104N是结合衬垫结构120的中间结构。应注意,为了明晰且易于解释本揭示案的一些实施例,半导体装置100的一部分被特别地绘示。
在一些实施例中,结合衬垫结构120的介电层104N可包括整块硅、掺杂硅、未掺杂硅、介电材料、其他适合的元素,或上述各者的组合。此外,结合衬垫结构120的介电层104N可为金属间介电(inter-metal dielectric;IMD)层。在一些实施例中,IMD层可由磷硅酸盐玻璃(phosphosilicate glass;PSG)、硼磷硅酸盐玻璃(borophosphosilicate glass;BPSG)、氟硅酸盐玻璃(fluorosilicate glass;FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、低介电常数介电材料、上述各者的化合物、上述各者的合成物、上述各者的组合等经由任何适合方法(例如旋涂涂布、化学气相沉积(chemical vapor deposition;CVD)、电浆增强CVD(plasma-enhanced CVD;PECVD)、上述各者的组合等)而制成。
参看图4。凹槽1042(或沟槽)形成于介电层104N中。凹槽1042可通过任何适合的蚀刻制程而形成,如湿式蚀刻、干式蚀刻、上述各者的组合等。在一些实施例中,氢氧化四甲铵(TMAH)用于各向异性湿式蚀刻制程。在一些实施例中,干式蚀刻制程是通过蚀刻气体而实施,此蚀刻气体包含O2、Cl2、HBr、He、NF3、CO2、CxHyFz、Ar、N2、H2、上述各者的组合等。在一些实施例中,凹槽1042具有倾斜侧壁。在一些实施例中,介电层104N的凹槽1042可通过任何适合的制程而形成,如镶嵌制程、双镶嵌制程、上述各者的组合等,以便基于各种设计而形成具有所欲形状的沟槽。在一些实施例中,另一凹槽(图4中未绘示)形成于介电层104N中以用于形成导线114N。亦即,凹槽1042及用于形成导线114N的凹槽可在同一蚀刻制程中形成。
参看图5。互连结构110的导电部分112N形成于凹槽1042中。根据上文针对图1提及的描述,导电部分112N可经由介电层104N路由以连接导线114N,以使得互连结构110的导电部分112N、导线114N,及导电通孔116N可成为外部电子构件与半导体装置100中的如晶体管103的元件之间的电连接的一部分。导电材料112N可包括导电材料,如铜、铝、钨、上述各者的组合等。在一些实施例中,互连结构110的导电部分112N可通过任何适合的制程而形成,如镶嵌制程、双镶嵌制程、上述各者的组合等,以便利用导电材料填充凹槽1042。在一些实施例中,导线114N可随着导电部分112N而形成。
在一些实施例中,半导体装置100的导电部分112N(及导线114N)可进一步在导电部分112N与介电层104N之间包括一或更多个阻障层或粘附层,以便防止由于从导电部分112N至介电层104N中的金属扩散而发生金属污染。此外,阻障层或粘附层可包括钛、氮化钛、钽、氮化钽、上述各者的组合等,且可通过使用化学气相沉积(chemical vapor deposition;CVD)、物理气相沉积(physical vapor deposition;PVD)、原子层沉积(atomic layerdeposition;ALD),及上述各者的组合等而形成。
在一些实施例中,导电部分112N(及导线114N)可通过于图4的结构上方沉积导电材料而形成,此导电材料可填充凹槽1042(及用于形成导线114N的凹槽)且亦可覆盖介电层104N。随后,可实施平坦化操作以利用介电层104N的顶表面来平坦化导电材料的顶表面,以形成导电部分112N(及导线114N)。而且,平坦化操作可包括使用化学机械研磨(chemicalmechanical polishing;CMP)制程。因此,如图5所示,导电部分112N的顶表面可与介电层104N的顶表面共面。
应注意,方法M1可始于操作S10,此操作包括在半导体装置100的基板102上形成互连结构110。另外,执行结合衬垫结构120的制造制程,如图3至图5中所绘示,以使得互连结构110的导电部分112N可作为中间结构形成于介电层104N中,且被介电层104N曝露。
参看图6。方法M1可继续进行操作S20,此操作包括在互连结构110上形成第一钝化层130。更特定而言,第一钝化层130形成于导电部分112N及介电层104N上。第一钝化层130可包括氧化物、氮化物、介电材料、上述各者的组合等。第一钝化层130可具有硬质非反应性特性,此特性保护下层元件免受外界环境的腐蚀、刮划,及/或损害。
在一些实施例中,如图1中所示,第一钝化层130可包括多层结构,如第一层1302及第二层1304,如图1所示。例如,第一层1302可包括氮化硅(SiN),而第二层1304可包括未掺杂硅酸盐玻璃(undoped silicate glass;USG),反之亦然。多层结构可经由不同的沉积制程、其他适合的制程等逐层形成。因此,第一钝化层130的配置可基于各种设计而调整,例如第一钝化层130的材料可基于此钝化层下方的元件材料而选择,以使得此钝化层的保护效果可得以改良。
参看图7。方法M1可继续进行操作S30,此操作包括在形成穿过第一钝化层130的至少一个开口1302。更特定而言,第一钝化层130可经图案化及/或蚀刻以在此钝化层中形成开口1302,以使得开口1302可曝露导电部分112N的顶表面的一部分。在一些实施例中,可选择性实施至少一个蚀刻制程,如湿式蚀刻、光化学蚀刻、干式蚀刻、电浆蚀刻,或上述各者的组合,以产生具有定向或各向异性结构的开口1302。例如,如图7所示,开口1302可具有弯曲及/或向下收敛的侧壁。在一些实施例中,开口1302可对准导电部分112N的顶表面的中心,以使得结合衬垫结构120可经配置以对称于导电部分112N的顶表面的法线。在一些其他实施例中,开口1302可不对准导电部分112N的顶表面的中心。只要开口1302曝露导电部分112N,则实施例即符合本揭示案的一些实施例范畴。应注意,开口1302可作为接触开口、通孔等。
参看图8。方法M1可继续进行操作S40,此操作包括经由开口1302在互连结构110的导电部分112N上沉积阻障层140。更特定而言,阻障层140是沉积在图7的结构上方,且特定而言,阻障层140经由开口1302沉积在导电部分112N的一部分上。在一些实施例中,阻障层140可包括基于钽(Ta)的材料,如钽、氮化钽(TaN)、上述各者的组合等。在一些实施例中,阻障层140可通过至少一个沉积制程而形成,该制程诸如物理气相沉积(physical vapordeposition;PVD)、原子层沉积、化学气相沉积、电浆增强原子层沉积、分子束磊晶、离子束辅助沉积、上述各者的组合等。如图8所示,阻障层140可具有厚度h1且可覆盖导电部分112N及第一钝化层130,以密封曝露的导电部分112N。因此,阻障层140可保护导电部分112N免遭外界损害,及/或防止导电部分112N与随后将形成于其上的任何元件之间发生相互扩散。
参看图9。方法M1可继续进行操作S50,此操作包括氧化阻障层140的顶表面1402,如图8所示,以在阻障层140上形成氧化层150。更特定而言,如图9所示,氧化层150通过使用至少一个氧化制程而立即形成于阻障层140的顶表面1404上方。在一些实施例中,氧化层150可包括金属氧化物。氧化层150及阻障层140包括同一金属。若阻障层140由氮化钽制成,则氧化层150可包括基于钽(Ta)的材料、TaxOy、上述各者的组合等。在一些实施例中,氧化层150可能不含氮。或者,氧化层150的氮浓度低于氧化层150的氧浓度。此外,因为基于钽的材料可包括其内具有细小间隔或孔的多孔结构,因此氧化层150可捕获由阻障层140产生的湿气及/或污染,且亦防止结合衬垫结构120中的内应力的局部化。因此,结合衬垫结构120的可能的晶须缺陷问题可得以减缓。
在一些实施例中,氧化制程包含将阻障层140的顶表面1402曝露于氧化剂气体达一时段。此外,可提供氧化剂气体以覆盖及氧化阻障层140的顶表面1402。氧化剂气体可包括氮气及氧气。氮气大体上为惰性,以使得可防止氮与阻障层140之间相互作用。经由调整氮与氧的流量比,可适当控制阻障层140的氧化以形成具有所欲结构及/或特性的氧化层150。在一些实施例中,提供至阻障层140的氮气与氧气的流量比范围可在约1/1000与约1000/1之间。例如,当氮流率为约1标准立方厘米每分钟(sccm)时,氧流率将为约1000sccm,反之亦然。若氧化制程流量比超出上文提及的范围,则氧化层150可能产生非所欲结构及/或特性,且该非所欲结构及/或特性不利地影响半导体装置100的效能。
另一方面,在一些实施例中,氧化制程时段的范围可在约10秒与约600秒之间。若时段大于约600秒,则氧化层150将过于厚,且不利地影响电传输。换言之,结合衬垫结构120的接触电阻可能增大。相反,若时段小于约10秒,则氧化层150将过于薄,而无法提供足够结构强度及/或不足以抵御晶须缺陷问题。
此外,在一些实施例中,可在约25℃(或室温)与约100℃之间的范围的温度下实施氧化制程。若温度高于约100℃,则氧化层150的接触电阻可能增大。相反,若温度低于约25℃,则氧化层150可能产生非所欲结构,且该结构不利地影响半导体装置100的效能。
因此,氧化层150的厚度h3可基于各种设计而可控,例如在约(埃)与约的范围中。若厚度h3大于氧化层150将过于厚,且不利地影响电传输。相反,若厚度h3小于约则氧化层150将过于薄,而无法提供足够结构强度及/或不足以抵御晶须缺陷问题。
在一些实施例中,由于审慎且可控的氧化制程,氧化层150的厚度可基于各种设计而调整。更特定言之,氧化制程可将阻障层140的顶部转化为氧化层150。亦即,氧化层150的形成可涉及消耗阻障层140的一部分。此外,在氧化制程期间,针对图8中的阻障层140,阻障层140的顶部可从其顶表面1402向下转化,而氧化层150的一部分可从其顶表面1402向上形成。换言之,氧化层150可从阻障层140的顶表面1402起形成,如图8中所示。
例如,图8中的阻障层140的厚度可标记为h1,图9中的阻障层140的厚度可标记为h2,且图9中的氧化层150的厚度可标记为h3。当氧化制程可从阻障层140的顶表面1402起消耗阻障层140时,厚度h1将大于厚度h2。由于阻障层140的消耗,图8中的阻障层140的顶表面1402可向下转化至图9中的阻障层140的顶表面1404。此外,当氧化层150的一部分可从阻障层140的顶表面1402起向上形成时,厚度h2及厚度h3之和将大于厚度h1。此外,在一些实施例中,厚度h3可小于厚度h2。
依据上文提及的关于阻障层140及氧化层150的描述,应理解氧化层150可从阻障层140的顶部直接转化,且亦可同时从阻障层140的顶表面1402形成。因此,氧化层150可与阻障层140共形,例如,氧化层150的顶表面1502可共形于阻障层140的顶表面1404。
另一方面,因为氧化层150是通过氧化阻障层140的顶部而形成,氧化层150成分可大体上与阻障层140相同。在一些实施例中,氧化层150的钽基材料可大体上与阻障层140相同。此外,由于氧化剂气体连续提供达一时段,正在生长的氧化层150的顶部可比其底部曝露于更多氧化剂气体,以使得氧化层150的氧浓度可在离开阻障层140的氧化层150的侧面上达到峰值,亦即,在邻近于衬垫金属层160的氧化层150侧面,此衬垫金属层随后形成于氧化层150上。亦即,氧化层150的氧浓度可向下降低。应注意,上文提及的浓度是定义为混合物(例如,氧化层150)中一组分(例如,氧)的实体数值除以混合物体积所得的数值浓度。
参看图10。方法M1可继续进行操作S60,此操作包括在氧化层150上形成衬垫金属层160。更特定言之,衬垫金属层160可包括铝(Al)基材料、铜(Cu)基材料、上述各者的组合物等,以便实现向半导体装置100的电连接。在一些实施例中,衬垫金属层160可通过上文提及的沉积制程中至少一者而形成。由于如上所述阻障层140及氧化层150的配置,导电部分112N与衬垫金属层160之间的相互扩散可被阻止。另一方面,如上文所论述,氧化层150可具有多孔结构以包含由阻障层140产生的湿气及/或污染。此外,多孔结构亦可充当缓冲物以减轻阻障层140及衬垫金属层160之间内应力的局部化。因此,衬垫金属层160上的可能的晶须缺陷问题可减轻。
在一些实施例中,在衬垫金属层160形成之后,可实施至少一个蚀刻制程以图案化阻障层140、氧化层150,及衬垫金属层160。在一些实施例中,第一钝化层130亦可经蚀刻。经由至少一个蚀刻制程,可实现针对结合衬垫结构120的所欲结构配置。
参看图11。方法M1可继续进行操作S70,此操作包括在衬垫金属层160及第一钝化层130上形成第二钝化层170。更特定言之,第二钝化层170可形成于第一钝化层130、阻障层140、氧化层150,及衬垫金属层160上。例如,第二钝化层170可通过上文提及的沉积制程中至少一者而形成。第二钝化层170可包括氧化物、氮化物、介电材料,上述各者的组合等。因此,第二钝化层170可保护下层元件免受外界环境的腐蚀、刮划,及/或损坏。
在一些实施例中,第二钝化层170可包括多层结构,如第一层1702及第二层1704,如图1所示。例如,第一层1702可包括未掺杂硅酸盐玻璃(undoped silicate glass;USG)及第二层1704可包括氮化硅(SiN)。多层结构可经由不同沉积制程、其他适合的制程等逐层形成。因此,第二钝化层170的保护效果可增大。
在一些实施例中,可随后对图11中的结构实施化学机械研磨(chemicalmechanical polishing;CMP)制程,以使得衬垫金属层160可曝露,如图1中所示,且预备好进行外部电子构件的结合及/或接触。此外,根据不同结合及/或接触条件,可对图1中结构实施类似于蚀刻制程的额外制程,以便可随后在衬垫金属层160上实现所欲形状,例如沟槽,以提升结合及/或接触。
在一些实施例中,覆盖层可进一步形成于曝露的衬垫金属层160上,以提供平滑表面以用于外部电子构件的结合及/或接触。在一些实施例中,覆盖层可包括具有优良导电特性的金属材料,如纯铝、铝基合金、任何适合的金属材料,及上述各者的组合。应注意,铝基合金可为纯铝与以下金属材料中至少一者的组合,如:钯(Pd)、镍(Ni)、金(Au)、铂(Pt)、钌(Ru)、铑(Rh)、铱(Ir)、铈(Ce)及钼(Mo)。
参看图12,其绘示依据本揭示案的一些其他实施例的结合衬垫结构220的示意图。由于图12的一些元件类似于图11的彼等相应元件,下文将不再重复彼等类似元件的描述。如图12中所示,导电部分212N形成有矩形横截面。第一钝化层230具有垂直侧壁,此等侧壁之间形成有开口。类似地,阻障层240、氧化层250、衬垫金属层260,及第二钝化层270可基于各种设计,通过上述任何适合的制程依序形成于导电部分212N及第一钝化层230上。
参看图13,其绘示依据本揭示案的又一实施例的结合衬垫结构320的示意图。由于图13的一些元件类似于图12的彼等相应元件,下文将不再重复彼等类似元件的描述。类似地,阻障层340、氧化层350、衬垫金属层360,及第二钝化层370可基于各种设计,通过上述任何适合的制程依序形成于导电部分312N及第一钝化层330上。在一些实施例中,当衬垫金属层360及其上层元件被图案化时,第一钝化层330未经蚀刻,以使得其顶表面可具有均匀高度。
在一些实施例中,阻障层340可包括多层结构。如图13所示,阻障层340可包括三个相应的层。而且,第一层3402、第二层3404,及第三层3406可以自下而上的顺序排列。阻障层340的多层结构的每一层可分别通过上文提及的沉积制程中的至少一个制程形成。在一些实施例中,第一层3402可为金属层(例如,钽层),第二层3404可为金属氮化物层(例如,氮化钽层),且第三层3406可为金属氮化物层(例如,氮化钽层)。
另外地,第一层3402的厚度可标记为T1,第二层3404的厚度可标记为T2,且第三层3406的厚度可标记为T3。在一些实施例中,厚度T3大于厚度T2。在一些实施例中,厚度T2大于厚度T1。应注意,多层结构中每一层的厚度可基于各种设计而通过调整沉积制程的沉积参数来控制。例如,第二层3404可通过范围在约400瓦与约600瓦(例如,500瓦)之间的沉积功率而形成,以使得第二层的厚度T2的范围可介于约与约之间(例如,)。又例如,第三层3406可通过范围在约5000瓦与约7000瓦(例如,6000瓦)之间的沉积功率而形成,以使得第三层的厚度T3的范围可介于约与约之间(例如,)。因此,第二层3404可充当缓冲层以保护下层元件及/或结构在其他元件(例如,第三层3406)形成于其上期间免受腐蚀、刮划,及/或损害。
在一些实施例中,当第二层3404及第三层3406皆由氮化钽制成时,第二层及第三层的至少一者可进一步包括其他类似于金属的材料,此等材料将配备不同特性以用于应对一些特定条件。在一些实施例中,阻障层340可包括金属氮化物及/或金属,而不含氧化物。因此,由于多层结构的配置,阻障层340的保护效果可进一步增强。
另外地,氧化层350可通过氧化阻障层340的第三层3406而形成。因此,氧化层350及第三层3406可包括相同金属。氧化层350的厚度可标记为T4,且具有厚度T1、T2、T3及T4之中的最小值。
参看图14,其绘示依据本揭示案的一些实施例的晶圆处理设备10的示意图。在一些实施例中,可在晶圆处理设备10中实施图2的操作S40、S50,及/或S60。更特定而言,晶圆处理设备10可包括多个前开式晶圆传送盒(front opening unified pod;FOUP)12、装载端口14、负载锁定腔室16、多个处理腔室20、22、28、30、32、通过腔室24、34、移送腔室18、26、移送机器人19、27,以及其他元件,如电源及真空泵。晶圆处理设备10的特征细节将描述于下。
在一些实施例中,每一前开式晶圆传送盒(front opening unified pod;FOUP)12中可包含多个晶圆。FOUP 12可在半导体制造设备(fabrication plant;FAB)中传送。当FOUP被传送至FAB中的晶圆处理设备10中时,FOUP可被装载及连接至装载端口14。装载端口14连接至负载锁定腔室16。负载锁定腔室16连接至移送腔室18。通过腔室24、34分别连接在移送腔室18、26之间。处理腔室20、22可连接至移送腔室18。处理腔室28、30、32可连接至移送腔室26。移送腔室18、26分别配备移送机器人19、27以在前述的晶圆处理设备10的元件之间传送晶圆。
在一些实施例中,处理腔室20、22、28、30、32用以分别实施各种半导体制造程序。例如,处理腔室20可为脱气腔室,处理腔室22可为预清洁腔室,处理腔室28、32可为沉积腔室,且处理腔室30可为氧化腔室。此外,如图14所示的无符号的处理腔室可为前述腔室的备用腔室,或基于各种设计而被分配以实施额外的半导体制造程序,例如快速热制程(rapidthermal process;RTP)、化学气相沉积(chemical vapor deposition;CVD)、物理气相沉积(physical vapor deposition;PVD),及离子化金属电浆(ionized metal plasma;IMP)制程。在一些实施例中,通过腔室24、34亦可用以在半导体制造程序之间冷却晶圆。
参看图15,其绘示依据本揭示案的一些实施例的用于形成半导体装置100的结合衬垫结构120的方法M2的流程图。由于如图2中所示的方法M1的一些操作类似于如图14中所示的方法M2的对应操作,下文将不再重复彼等类似操作的描述。出于说明的目的,参考如图14中所示的晶圆处理设备10来共同描述方法M2的细节,如下所述。
在一些实施例中,对半导体基板依序执行操作S10-S30,以使得可提供具有如图7中所示的结构的未完工半导体装置。未完工的半导体装置可依序包含在FOUP 12中,运送至晶圆处理设备10,在装载端口14卸载,并移送至负载锁定腔室16内以准备执行以下制造程序。例如,真空泵可将负载锁定腔室16抽真空以防止外界污染进入晶圆处理设备10。
在一些实施例中,操作S32包括使未完工的半导体装置脱气。更特定而言,移送机器人19可将未完工的半导体装置(在此情况下是图7中的晶圆)从负载锁定腔室16移至处理腔室20以用于实施脱气制程。在脱气制程期间,晶圆可经加热以活化晶圆上的剩余杂质。随后,可应用真空泵以将活化杂质排出至外界。在一些实施例中,如氢气(H2)等反应性气体可进一步被提供至晶圆,以移除及/或防止非所欲氧化层在晶圆上的形成。在一些实施例中,脱气制程是针对具有或没有第一钝化层130的导电部分112N。
在一些实施例中,操作S34包括预清洁未完工的半导体装置。更特定而言,在脱气制程之后,移送机器人19可将晶圆从处理腔室20移至处理腔室22,以用于实施预清洁制程。执行预清洁制程以移除晶圆上非所欲的层、材料,及物件。在一些实施例中,预清洁制程可包括溅射蚀刻制程、远端电浆清洁(remote plasma cleaning;RPC)制程、上述各者的组合等。在一些实施例中,预清洁制程是针对具有或没有第一钝化层130的导电部分112N。
在一些实施例中,在预清洁制程之后,晶圆可从处理腔室22逐一移至通过腔室24、移送腔室26,及处理腔室28。随后,如上文所论述的多种阻障层可形成于处理腔室28中,经由操作S40。
在一些实施例中,可在处理腔室28中原位执行操作S50,亦即氧化制程,以在阻障层上形成氧化层。在形成阻障层之后,向处理腔室28提供氧源。在一些其他实施例中,在处理腔室28、30中分别实施操作S40、S50。详细而言,晶圆可在真空条件下从处理腔室28中移至处理腔室30。随后,可在处理腔室30中执行操作S50。
在一些实施例中,在氧化制程之后,操作S60可在处理腔室32中执行以在氧化层上形成衬垫金属层。此外,晶圆可逐一移动至移送腔室26、通过腔室34、移送腔室18、负载锁定腔室16、装载端口14,及FOUP 12。因此,操作S60、S70及其他适合制程可经执行以形成多种结合衬垫结构,如上文所论述。
基于上文提及的描述,本揭示案的一些实施例可提供各种优势。详细而言,结合衬垫结构的阻障层可经历氧化制程以从阻障层的顶表面形成氧化层。此外,氧化制程可经操纵以提供基于各种设计而具有可控厚度的氧化层。氧化层可捕获由阻障层产生的湿气及/或污染,亦防止内应力在结合衬垫结构中局部化。因此,结合衬垫结构的可能的晶须缺陷问题可得以减缓。
在一些实施例中,半导体装置的形成方法包括在半导体装置上形成互连结构,在互连结构上形成钝化层,经由钝化层形成至少一个开口,至少在开口中形成氧化层,及在氧化层上形成衬垫金属层。互连结构的一部分由至少一开口曝露。在一些实施例中,半导体装置的形成方法进一步包括经由沉积制程,至少在开口中沉积阻障层,及氧化层经由氧化制程形成于阻障层上方。在一些实施例中,沉积阻障层包括在钝化层的一部分上沉积阻障层,同时经由至少一个开口在互连结构上沉积阻障层。在一些实施例中,形成氧化层包括:曝露阻障层的顶表面至氧化剂气体达一时段;及氧化阻障层,其中阻障层的一部分转化为氧化层。在一些实施例中,时段范围在约10秒与约600秒之间。在一些实施例中,氧化剂气体包括氮及氧,且氮对氧的流量比范围在约1/1000与约1000/1之间。在一些实施例中,沉积制程及氧化制程在同一腔室中实施。在一些实施例中,沉积制程及氧化制程是在不同腔室中分别实施。在一些实施例中,形成氧化层,以使得阻障层的厚度减小。在一些实施例中,形成氧化层是在范围约25℃与约100℃之间的温度下实施的。在一些实施例中,半导体装置的形成方法进一步包括在形成氧化层之前,先使半导体装置脱气。在一些实施例中,形成半导体装置的方法进一步包括在使半导体装置脱气后,预清洁半导体装置。
在一些实施例中,半导体装置包括具有导电部分的互连结构、位于导电部分上且其内具有开口的第一钝化层、位于导电部分的一部分上方且至少位于第一钝化层的开口中的氧化层,及直接位于氧化层上且电连接至导电部分的衬垫金属层。在一些实施例中,氧化层的氧浓度向下降低。在一些实施例中,氧化层夹在衬垫金属层与导电部分之间。在一些实施例中,半导体装置进一步包括位于第一钝化层上方且接触氧化层及衬垫金属层的第二钝化层。在一些实施例中,氧化层的一部分夹在第二钝化层与第一钝化层之间。
在一些实施例中,半导体装置包括具有导电部分的互连结构、电连接至导电部分的阻障层、位于阻障层上的氧化层,及氧化层上的衬垫金属层。在一些实施例中,氧化层的厚度范围在约与约之间。在一些实施例中,氧化层及阻障层包括同一金属。
前述内容介绍数个实施例的特征,以使得熟悉此项技术者可理解本揭示案的态样。彼等熟悉此项技术者应理解,其可将本揭示案的一些实施例用作设计或修饰其他制程与结构的基础,以实现与本案介绍的实施例相同的目的及/或获得相同的优势。彼等熟悉此项技术者亦应认识到,此种同等构成不脱离本揭示案的一些实施例的精神与范畴,且可在本案中进行各种变更、替换,及改动,而不脱离本揭示案的一些实施例的精神及范畴。
Claims (10)
1.一种半导体装置的形成方法,其特征在于,包括:
在一半导体装置上形成一互连结构;
在该互连结构上形成一钝化层;
形成穿过该钝化层的至少一个开口,其中该互连结构的一部分被该至少一个开口曝露;
至少在该开口中形成一氧化层;及
在该氧化层上形成一衬垫金属层。
2.根据权利要求1所述的半导体装置的形成方法,进一步包括:
经由一沉积制程,至少在该开口中沉积一阻障层,及该氧化层经由一氧化制程形成于该阻障层上方。
3.根据权利要求2所述的半导体装置的形成方法,其中沉积该阻障层包括:
在该钝化层的一部分上沉积该阻障层,同时经由该至少一个开口在该互连结构上沉积该阻障层。
4.根据权利要求2所述的半导体装置的形成方法,其中形成该氧化层包括:
曝露该阻障层的一顶表面至一氧化剂气体达一时段;及
氧化该阻障层,其中该阻障层的一部分转化为该氧化层。
5.根据权利要求2所述的半导体装置的形成方法,其中形成该氧化层,以使得该阻障层的一厚度减小。
6.根据权利要求1所述的半导体装置的形成方法,进一步包括:
在形成该氧化层之前,先使该半导体装置脱气。
7.一种半导体装置,其特征在于,包括:
一互连结构,具有一导电部分;
一第一钝化层,位于该导电部分上,且其内具有一开口;
一氧化层,位于该导电部分的一部分上方,且至少位于该第一钝化层的该开口中;及
一衬垫金属层,直接位于该氧化层上,且电连接至该导电部分。
8.根据权利要求7所述的半导体装置,其中该氧化层的氧浓度向下降低。
9.一种半导体装置,其特征在于,包括:
一互连结构,具有一导电部分;
一阻障层,电连接至该导电部分;
一氧化层,在该阻障层上;及
一衬垫金属层,在该氧化层上。
10.根据权利要求9所述的半导体装置,其中该氧化层及该阻障层包括同一金属。
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