CN110855978A - Method for testing PLL (phase locked loop) stability of HDMI (high-definition multimedia interface) through SOC (system on chip) - Google Patents
Method for testing PLL (phase locked loop) stability of HDMI (high-definition multimedia interface) through SOC (system on chip) Download PDFInfo
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- CN110855978A CN110855978A CN201911045886.0A CN201911045886A CN110855978A CN 110855978 A CN110855978 A CN 110855978A CN 201911045886 A CN201911045886 A CN 201911045886A CN 110855978 A CN110855978 A CN 110855978A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2843—In-circuit-testing
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention provides a method for testing PLL (phase locked loop) stability of an HDMI (high-definition multimedia interface) through an SOC (system on chip), wherein the SOC controls HDMI signal output, and the method comprises the following steps: s1: acquiring a nominal frequency value A Hz of a reference clock crystal of the SOC; s2: measuring the actual frequency value of a reference clock crystal of the SOC to be B Hz; s3: calculating the frequency deviation of the reference clock crystal of the SOC to be C PPM through [ (B-A)/A ]; s4: measuring the actual frequency value of an HDMI signal output by a reference clock crystal of the SOC after the reference clock crystal passes through the PLL, wherein the actual frequency value is D Hz; s5: acquiring an output nominal frequency value E Hz of the HDMI signal set by the SOC; s6: calculating the frequency deviation of the HDMI signal to be F PPM through [ (D-E)/E ]; the PLL stability of the HDMI can be judged according to the absolute value of the difference value of the F PPM and the C PPM.
Description
Technical Field
The invention relates to the field of HDMI videos, in particular to a method for testing the PLL stability of an HDMI through an SOC.
Background
A Phase-Locked Loop (PLL) occupies a significant role in SOC (System On chip), and particularly, whether the PLL of a High Definition Multimedia Interface (HDMI) is stable or not determines whether the HDMI signal can be normally output in the SOC; in the prior art, the jitter of an HDMI output signal is measured by an oscilloscope, the PLL stability of the HDMI is obtained according to the jitter of the HDMI output signal, an active probe is required for measurement by the oscilloscope, and the oscilloscope and the active probe are expensive; therefore, a method for testing the PLL stability of HDMI with simple operation and low cost is urgently needed.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method for testing the PLL stability of HDMI through SOC, which is low in cost and simple in operation.
The invention is realized by the following technical scheme:
the invention provides a method for testing the PLL stability of an HDMI through an SOC (system on chip), wherein the SOC controls the signal output of the HDMI, and the method for testing the PLL stability of the HDMI through the SOC comprises the following steps:
s1: acquiring a nominal frequency value A Hz of a reference clock crystal of the SOC;
s2: measuring the actual frequency value of a reference clock crystal of the SOC to be B Hz;
s3: calculating the frequency deviation of the reference clock crystal of the SOC to be C PPM through [ (B-A)/A ];
s4: measuring the actual frequency value of an HDMI signal output by a reference clock crystal of the SOC after the reference clock crystal passes through the PLL, wherein the actual frequency value is D Hz;
s5: acquiring an output nominal frequency value E Hz of the HDMI signal set by the SOC;
s6: and calculating the frequency deviation of the HDMI signal to be F PPM through [ (D-E)/E ].
Furthermore, when the absolute value of the difference between the F PPM and the C PPM is less than 5PPM, the PLL of the HDMI is stable.
Further, in step S2, B is measured by a frequency meter.
Further, in step S4, D is measured by the protocol analyzer.
The invention has the beneficial effects that:
the method for testing the PLL stability of the HDMI through the SOC provided by the invention can test the PLL stability of the HDMI without an oscilloscope and an active probe, and has the advantages of low cost and simple operation.
Drawings
Fig. 1 is a schematic diagram illustrating steps of a method for testing PLL stability of HDMI via SOC according to the present invention.
Detailed Description
In order to more clearly and completely explain the technical scheme of the invention, the invention is further explained with reference to the attached drawings.
Referring to fig. 1, the present invention provides a method for testing PLL stability of HDMI via SOC, where the SOC controls HDMI signal output, and the method for testing PLL stability of HDMI via SOC includes the following steps:
s1: acquiring a nominal frequency value A Hz of a reference clock crystal of the SOC;
s2: measuring the actual frequency value of a reference clock crystal of the SOC to be B Hz;
s3: calculating the frequency deviation of the reference clock crystal of the SOC to be C PPM through [ (B-A)/A ];
s4: measuring the actual frequency value of an HDMI signal output by a reference clock crystal of the SOC after the reference clock crystal passes through the PLL, wherein the actual frequency value is D Hz;
s5: acquiring an output nominal frequency value E Hz of the HDMI signal set by the SOC;
s6: and calculating the frequency deviation of the HDMI signal to be F PPM through [ (D-E)/E ].
In the present embodiment, the overall SOC is: system On Chip, Chip level System; HDMI is collectively referred to as: high Definition Multimedia Interface, High Definition Multimedia Interface; the PLL is known as: phase locked loop; hz is known as: hertz; the PPM is fully called: parts per million; calculating C PPM and F PPM through steps S1 to S6, and obtaining the PLL stability of the HDMI according to the absolute value of the difference value of the C PPM and the F PPM; the nominal frequency value of the reference clock crystal of the SOC is the basic parameter of the reference clock crystal and can be obtained from the factory parameters of the reference clock crystal.
Furthermore, when the absolute value of the difference between the F PPM and the C PPM is less than 5PPM, the PLL of the HDMI is stable.
In the embodiment, when the absolute value of the difference between the F PPM and the C PPM is less than 5PPM, it indicates that the PLL of the HDMI is stable; when the absolute value of the difference value between the F PPM and the C PPM is more than or equal to 5PPM, the PLL of the HDMI is unstable.
Further, in step S2, B is measured by a frequency meter.
In the present embodiment, the types of the frequency meter are: HC-F1000L; the value of B is measured by a frequency meter.
Further, in step S4, D is measured by the protocol analyzer.
In this embodiment, the model of the protocol analyzer is: quantumdata 980; the value of D is measured by a protocol analyzer.
Of course, the present invention may have other embodiments, and based on the embodiments, those skilled in the art can obtain other embodiments without any creative effort, and all of them are within the protection scope of the present invention.
Claims (4)
1. A method for testing PLL stability of HDMI through SOC, the SOC controls HDMI signal output, the method for testing PLL stability of HDMI through SOC comprises the following steps:
s1: acquiring a nominal frequency value A Hz of a reference clock crystal of the SOC;
s2: measuring the actual frequency value of a reference clock crystal of the SOC to be B Hz;
s3: calculating the frequency deviation of the reference clock crystal of the SOC to be C PPM through [ (B-A)/A ];
s4: measuring the actual frequency value of an HDMI signal output by a reference clock crystal of the SOC after the reference clock crystal passes through the PLL, wherein the actual frequency value is D Hz;
s5: acquiring an output nominal frequency value E Hz of the HDMI signal set by the SOC;
s6: and calculating the frequency deviation of the HDMI signal to be F PPM through [ (D-E)/E ].
2. The method for testing PLL stability of HDMI through SOC as recited in claim 1, wherein when the absolute value of the difference between F PPM and C PPM is less than 5PPM, it indicates that the PLL of HDMI is stable.
3. The method for testing PLL stability of HDMI through SOC according to claim 1, wherein in step S2, B is measured by a frequency meter.
4. The method for testing PLL stability of HDMI through SOC according to claim 1, wherein D is measured by a protocol analyzer in step S4.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911045886.0A CN110855978B (en) | 2019-10-30 | 2019-10-30 | Method for testing PLL (phase locked loop) stability of HDMI (high-definition multimedia interface) through SOC (system on chip) |
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| CN201911045886.0A CN110855978B (en) | 2019-10-30 | 2019-10-30 | Method for testing PLL (phase locked loop) stability of HDMI (high-definition multimedia interface) through SOC (system on chip) |
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| CN110855978A true CN110855978A (en) | 2020-02-28 |
| CN110855978B CN110855978B (en) | 2021-12-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050259505A1 (en) * | 2004-05-18 | 2005-11-24 | Broadcom Corporation | System and method for maintaining device operation during clock signal adjustments |
| CN102185561A (en) * | 2011-01-26 | 2011-09-14 | 意法·爱立信半导体（北京）有限公司 | Frequency deviation adjusting method and frequency deviation adjusting device used during startup of terminal |
| CN105807205A (en) * | 2016-03-11 | 2016-07-27 | 福州瑞芯微电子股份有限公司 | PLL automatic test circuit and test method |
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2019
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050259505A1 (en) * | 2004-05-18 | 2005-11-24 | Broadcom Corporation | System and method for maintaining device operation during clock signal adjustments |
| CN102185561A (en) * | 2011-01-26 | 2011-09-14 | 意法·爱立信半导体（北京）有限公司 | Frequency deviation adjusting method and frequency deviation adjusting device used during startup of terminal |
| CN105807205A (en) * | 2016-03-11 | 2016-07-27 | 福州瑞芯微电子股份有限公司 | PLL automatic test circuit and test method |
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| CN110855978B (en) | 2021-12-21 |
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