CN110808684B - Multi-mode BOOST converter applied to thermoelectric energy acquisition - Google Patents

Multi-mode BOOST converter applied to thermoelectric energy acquisition Download PDF

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CN110808684B
CN110808684B CN201910935324.7A CN201910935324A CN110808684B CN 110808684 B CN110808684 B CN 110808684B CN 201910935324 A CN201910935324 A CN 201910935324A CN 110808684 B CN110808684 B CN 110808684B
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CN110808684A (en
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刘帘曦
邢奕赫
黄超进
田宇渊
朱樟明
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a multi-mode BOOST converter applied to thermoelectric energy acquisition, which comprises: a thermoelectric generator TEG (1); a BOOST power stage sub-circuit (2) electrically connected to the thermoelectric generator TEG (1); a detection sub-circuit (3) electrically connected to the BOOST power stage sub-circuit (2); a sampling and mode selection sub-circuit (4) electrically connected to the BOOST power stage sub-circuit (2); a maximum power point tracking sub-circuit (5) electrically connected to the BOOST power stage sub-circuit (2); a logic and gate drive sub-circuit (6) electrically connecting the sampling and mode selection sub-circuit (4), the detection sub-circuit (3), the maximum power point tracking sub-circuit (5) and the BOOST power stage sub-circuit (2). The multi-mode BOOST converter provided by the invention adopts a mode of mixing three working modes of a discontinuous conduction mode, a critical conduction mode and a continuous conduction mode, and selects a proper working mode according to different input voltages, thereby reducing the circuit loss to the greatest extent and improving the conversion efficiency.

Description

Multi-mode BOOST converter applied to thermoelectric energy acquisition
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a multi-mode BOOST converter applied to thermoelectric energy acquisition.
Background
In the fields of ultra-low power wireless sensor networks (WBANs), portable devices, and the like, the environmental energy acquisition circuits are increasingly widely applied, and can provide power supply voltage to supply power to a subsequent load circuit. There are many types of environmental energy available, such as radio frequency energy, piezoelectric energy, photovoltaic energy, and thermal energy, among which the thermal energy density is relatively stable and large, and is well suited for wearable applications. Thermoelectric generators (TEG) are commonly used to convert thermal energy into electrical voltage in thermal energy collection. When the ambient temperature difference is low, the open circuit voltage taken by a thermoelectric generator (TEG) may be as low as tens of millivolts. Therefore, for thermoelectric energy harvesting, the key technology is the design of the TEG interface circuit, i.e. the BOOST (BOOST) converter, which needs to BOOST voltages as low as tens of millivolts above 1V.
Currently, the BOOST converter mainly has three predetermined operation modes, which are a discontinuous conduction mode, a critical conduction mode and a continuous conduction mode.
However, the conventional BOOST converter can only perform voltage conversion in a predetermined operation mode during operation, and cannot adjust the operation mode in good time when the input voltage range is large, so that the conversion efficiency is low and the circuit loss is large.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a multi-mode BOOST converter applied to thermoelectric energy harvesting. The technical problem to be solved by the invention is realized by the following technical scheme:
a multi-mode BOOST converter for thermoelectric energy harvesting, comprising:
a thermoelectric generator TEG for converting thermal energy into a first electrical signal;
the BOOST power level sub-circuit is electrically connected with the thermoelectric generator TEG and is used for processing the first electric signal to obtain a second electric signal;
the detection sub-circuit is electrically connected with the BOOST power level sub-circuit and is used for detecting the second electric signal to obtain a third electric signal;
the sampling and mode selection sub-circuit is electrically connected with the BOOST power level sub-circuit and is used for generating a fourth electric signal according to the open-circuit voltage;
the maximum power point tracking sub-circuit is electrically connected with the BOOST power level sub-circuit and is used for generating a fifth electric signal according to the open-circuit voltage and the real-time voltage;
and the logic and grid electrode driving sub-circuit is electrically connected with the sampling and mode selecting sub-circuit, the detecting sub-circuit, the maximum power point tracking sub-circuit and the BOOST power level sub-circuit and is used for selecting different modes according to the fourth electric signal and generating a first logic signal according to the third electric signal and the fifth electric signal so as to control the BOOST power level sub-circuit to process the first electric signal.
In one embodiment of the invention, the BOOST power stageThe circuit comprises: input capacitance CINInductor L, first NMOS tube MN1The first PMOS transistor MP1A load capacitor CLA first diode D1A second diode D2(ii) a Wherein,
the first diode D1And the second diode D2Are sequentially connected between a power supply end VDD and a ground end GND in series;
the load capacitor CLIs connected between a power supply end VDD and a ground end GND in series;
the first PMOS tube MP1The inductor L and the thermoelectric generator TEG1 are sequentially connected in series between a power supply end VDD and a ground end GND;
the input capacitor CINA node V formed by connecting the inductor L and the thermoelectric generator TEG in seriesINAnd the ground end GND;
the first NMOS tube MN1Is connected in series with the first PMOS tube MP1A node SW end formed by connecting the inductor L in series is connected between the ground end GND;
the first PMOS tube MP1The grid is electrically connected with the output end of the logic and grid driving sub-circuit;
the first NMOS tube MN1The gate is electrically connected to the logic and gate drive sub-circuit 6.
In one embodiment of the invention, the detection sub-circuit 4 comprises: a first switch S1, a second switch S2, a first resistor R1, a first comparator COMP 1; wherein,
the first switch S1 is connected in series between the node SW terminal of the BOOST power stage sub-circuit and the positive input terminal of the first comparator COMP 1;
the second switch S2 and the first resistor R1 are sequentially connected in series between the SW terminal of the BOOST power stage sub-circuit and the positive input terminal of the first comparator COMP 1;
the reverse input end of the first comparator COMP1 is electrically connected with a power supply end VDD, and the output end is electrically connected with the input end of the logic and gate driving sub-circuit.
In one embodiment of the invention, the maximum power isThe point tracking sub-circuit includes: discontinuous conduction mode conduction time control circuit TON_DCMControl, voltage division circuit and second comparator COMP25BIT counter 5BIT, discontinuous conduction mode period length control circuit TSW_DCMControl, critical conduction mode and continuous conduction mode conduction time Control circuit TON_CRM&CCMControl; wherein the voltage dividing circuit and the second comparator COMP2Is sequentially connected in series with a node V formed by connecting the inductor L and the thermoelectric generator TEG1 in seriesINAnd the 5-BIT counter 5 BIT;
the 5-BIT counter 5BIT is respectively and electrically connected with the discontinuous conduction mode period length control circuit TSW_DCMControl and critical conduction mode and continuous conduction mode conduction time Control circuit TON_CRM&CCM Control；
The discontinuous conduction mode period length control circuit TSW_DCMControl and critical conduction mode and continuous conduction mode conduction time Control circuit TON_CRM&CCMThe output end of the Control is respectively and electrically connected with the input end of the logic and grid electrode driving sub-circuit;
the discontinuous conduction mode conduction time control circuit TON_DCMControl is connected in series with the open-circuit voltage V of the thermoelectric generatorSAnd the logic and gate drive sub-circuit input terminal.
In an embodiment of the present invention, the discontinuous conduction mode conduction time control circuit TON_DCMThe Control includes: operational amplifier OA, third NMOS tube MN3And the fourth NMOS tube MN4The fifth NMOS transistor MN5A second PMOS transistor MP2And the third PMOS transistor MP3And the fourth PMOS transistor MP4The fifth PMOS transistor MP5A second resistor R2A first capacitor C1A third comparator COMP3(ii) a Wherein,
the positive input of the operational amplifier OA is electrically connected to the open-circuit voltage V of the thermoelectric generator TEG1SThe reverse input end is electrically connected with the third NMOS tube MN3And the second resistor R2The output end of the node formed by serial connection is electrically connected with the third NMOS tube MN3A gate electrode of (1);
the fourth PMOS tube MP4The second PMOS tube MP2The third NMOS tube MN3And the second resistor R2Are sequentially connected between a power supply end VDD and a ground end GND in series;
the fifth PMOS tube MP5The third PMOS tube MP3And the fourth NMOS tube MN4And the fifth NMOS tube MN5Are connected in series between a power supply end VDD and a ground end GND in sequence;
the first capacitor C1Is connected in series with the third PMOS tube MP3And the fifth NMOS tube MP5The nodes formed by the serial connection are connected with a ground end GND;
the third PMOS tube MP3And the first capacitor C1Node formed by concatenation c1 electrically connecting said third comparator COMP3The inverting input terminal of (1);
the third comparator COMP3Is electrically connected with a reference voltage end VREFThe output end of the logic and grid drive sub-circuit is electrically connected with the input end of the logic and grid drive sub-circuit;
the second PMOS tube MP2The grid electrode of the NMOS transistor is electrically connected with the third NMOS transistor MN3A drain electrode of (1);
the fourth PMOS tube MP4The grid electrode of the second PMOS tube M is electrically connected with the second PMOS tube MP2A source electrode of (a);
the second PMOS tube MP2The grid electrode of the PMOS transistor is electrically connected with the third PMOS transistor MP3A gate electrode of (1);
the fourth PMOS tube MP4The grid electrode of the PMOS transistor is electrically connected with the fifth PMOS transistor MP5A gate electrode of (1);
the fourth NMOS tube MN4The grid of the grid is electrically connected with an enabling end VEN;
the fifth NMOS tube MN5The gate of the logic and gate drive sub-circuit is electrically connected with the output end of the logic and gate drive sub-circuit.
In one embodiment of the present invention, the voltage dividing circuit 51 includes: third switch S3And the fourthSwitch S4The fifth switch S5A second capacitor C2A third capacitor C3(ii) a Wherein,
the third switch S3Connected in series to said second comparator COMP2Between the forward input end and the reverse input end;
the second capacitor C2Connected in series to said second comparator COMP2Between the inverting input terminal and the ground terminal GND;
the fourth switch S4And the third capacitor C3Are sequentially connected in series with the second comparator COMP2Between the inverting input terminal and the ground terminal GND;
the fifth switch S5Is connected in series with the fourth switch S4And the third capacitor C3The nodes formed by the series connection are connected with the ground terminal GND.
In an embodiment of the present invention, the discontinuous conduction mode period length control circuit TSW_DCMThe Control includes: sixth NMOS transistor MN6And a seventh NMOS transistor MN7And the eighth NMOS transistor MN8And a ninth NMOS transistor MN9The tenth NMOS transistor MN10Eleventh NMOS transistor MN11Sixth PMOS transistor MP6Seventh PMOS transistor MP7Eighth PMOS transistor MP8Ninth PMOS transistor MP9Tenth PMOS transistor MP10And a sixth switch group S6iAnd a seventh switch group S7iThe eighth switch group S8iAnd a ninth switch group S9iThe tenth switch group S10iAnd a fourth capacitor group C4iThe fifth capacitor group C5iAnd a sixth capacitor group C6iAnd a seventh capacitor group C7iAnd the eighth capacitor bank C8iAnd a ninth capacitor bank C9iI is 1,2, 3; wherein,
the sixth NMOS tube MN6Connected in series to a bias current IbiasAnd the ground end GND;
the sixth PMOS tube MP6And the seventh NMOS tube MN7Are sequentially connected between a power supply end VDD and a ground end GND in series;
the seventh PMOS tube MP7And the eighth NMOS tube MN8Are sequentially connected between a power supply end VDD and a ground end GND in series;
the eighth PMOS tube MP8And the ninth NMOS tube MN9Are sequentially connected between a power supply end VDD and a ground end GND in series;
the ninth PMOS tube MP9And the tenth NMOS transistor MN10Are sequentially connected between a power supply end VDD and a ground end GND in series;
the tenth PMOS tube MP10And the eleventh NMOS tube MN11Sequentially connected between a power supply terminal VDD and a ground terminal GND in series, and a common terminal thereof is used as an output terminal VTSWConnecting the logic and gate drive subcircuit 6;
the seventh NMOS tube MN7The grid electrode of the NMOS transistor is electrically connected with the sixth NMOS transistor MN6A gate and a drain;
the seventh PMOS tube MP7The eighth PMOS tube MP8The ninth PMOS transistor MP9The tenth PMOS tube MP10The grid electrodes of the PMOS tubes are respectively and electrically connected with the sixth PMOS tube MP6A gate and a drain;
the ninth NMOS tube MN9Is electrically connected with the eighth NMOS tube MN8The drain forms a node VC1；
The tenth NMOS transistor MN10The grid electrode of the NMOS transistor is electrically connected with the ninth NMOS transistor MN9The drain forms a node VC2；
The eighth NMOS tube MN8The grid of the NMOS transistor is electrically connected with the eleventh NMOS transistor MN11Is electrically connected with the tenth NMOS tube MN10The drain forms a node VC3；
The fourth capacitor bank C4iConnected in series to a node VCii is between 1,2,3 and the ground end GND;
the sixth switch group S6iAnd the fifth capacitor group C5iAre sequentially connected in series with a node VCi(i ═ 1,2,3) to ground GND;
the seventh switch group S7iAnd the sixth capacitor group C6iAre sequentially connected in series with a node VCi(i ═ 1,2,3) to ground GND;
the eighth switch group S8iAnd the seventh capacitor bank C7iAre sequentially connected in series with a node VCi(i ═ 1,2,3) to ground GND;
the ninth switch group S9iAnd the eighth capacitor bank C8iAre sequentially connected in series with a node VCi(i ═ 1,2,3) to ground GND;
the tenth switch group S10iAnd the ninth capacitor bank C9iAre sequentially connected in series with a node VCi( i 1,2,3) to ground GND.
In an embodiment of the present invention, the critical conduction mode and continuous conduction mode conduction time control circuit TON_CRM&CCMThe Control includes: bias current source IbiasInverter INV and twelfth NMOS transistor MN12Thirteenth NMOS transistor MN13The eleventh switch S11And a twelfth switch S12And a thirteenth switch S13And a fourteenth switch S14The fifteenth switch S15A tenth capacitor C10An eleventh capacitor C11And a twelfth capacitor C12A thirteenth capacitor C13And a fourteenth capacitor C14A fifteenth capacitor C15A fourth comparator COMP4(ii) a Wherein,
the bias current source IbiasAnd the twelfth NMOS tube MN12And the thirteenth NMOS tube MN13Are connected in series between a power supply end VDD and a ground end GND in sequence;
the tenth capacitor C10Is connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the eleventh switch S11And the eleventh capacitor C11Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the twelfth switch S12And the twelfth capacitor C12Are sequentially connected in series with the bias current source IbiasAnd said firstTwelve NMOS tubes MN12The nodes formed by the serial connection are connected with a ground end GND;
the thirteenth switch S13And the thirteenth capacitor C13Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the fourteenth switch S14And the fourteenth capacitance C14Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the fifteenth switch S15And the fifteenth capacitor C15Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the fourth comparator COMP4The positive input end is electrically connected with a reference voltage end VREFThe reverse phase input end is electrically connected with the bias current source IbiasAnd the twelfth NMOS tube MN12The output end of the node is electrically connected with the input end of the logic and grid electrode driving sub-circuit;
the inverter INV is connected in series with the enable terminal VEN and the twelfth NMOS tube MN12Between the grids;
the thirteenth NMOS tube MN13The gate is electrically connected to the output of the logic and gate drive sub-circuit 5.
In one embodiment of the present invention, the sampling and mode selection sub-circuit comprises: fifth comparator COMP5And a sixth comparator COMP6(ii) a Wherein,
the fifth comparator COMP5The inverting input ends of the first and second comparators are respectively electrically connected to the sixth comparator COMP6A node V formed by connecting the positive input end with the inductor L and the thermoelectric generator TEG in seriesIN；
The fifth comparator COMP5The positive input end is electrically connected with a first reference voltage end VREF1；
The sixth comparator COMP6The reverse input end is electrically connected with a second reference voltage end VREF2；
The fifth comparator COMP5And said sixth comparator COMP6The output ends are respectively and electrically connected with the input ends of the logic and grid electrode driving sub-circuits.
The invention has the beneficial effects that:
1. the multi-mode BOOST converter applied to thermoelectric energy acquisition provided by the invention adopts a mode of mixing three working modes of a discontinuous conduction mode, a critical conduction mode and a continuous conduction mode, wherein the discontinuous conduction mode with the minimum switching loss is adopted when the ultralow input voltage is 10mV to 40mV, the critical conduction mode is adopted for transition when the input voltage is 40mV to 100mV, and the continuous conduction mode with the minimum conduction loss is adopted when the input voltage is 100mV to 500mV, so that the circuit loss is reduced to the maximum extent, and the conversion efficiency is improved;
2. the multi-mode BOOST converter provided by the invention adopts the designed high-precision offset calibration comparator to replace a traditional zero-crossing comparator, so that the robustness of the circuit is improved;
3. the multi-mode BOOST converter provided by the invention can multiplex the offset calibration comparator in different working modes, thereby reducing the circuit scale and complexity;
4. the maximum power point tracking efficiency of the multi-mode BOOST converter provided by the invention can reach 95% in all working modes, and the peak efficiency of the multi-mode BOOST converter is 92.7% (V) in a continuous conduction modeS280mV), the efficiency can reach 32.8% when the discontinuous conduction mode is input with 10 mV.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a multi-mode BOOST converter applied to thermoelectric energy harvesting according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another structure of a multi-mode BOOST converter applied to thermoelectric energy harvesting according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a detection sub-circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a maximum power point tracking sub-circuit according to an embodiment of the present invention;
FIG. 5 is a discontinuous conduction mode conduction time control circuit T according to an embodiment of the present inventionON_DCMA schematic of the structure of Control;
FIG. 6 shows a discontinuous conduction mode cycle length control circuit T according to an embodiment of the present inventionSW_DCMA schematic of the structure of Control;
FIG. 7 is a diagram of a critical conduction mode and continuous conduction mode conduction time control circuit T according to an embodiment of the present inventionON_CRM&CCMA schematic of the structure of Control;
FIG. 8 is a waveform diagram illustrating a continuous conduction mode simulation according to an embodiment of the present invention;
fig. 9 is a discontinuous conduction mode simulation waveform diagram according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a multi-mode BOOST converter applied to thermoelectric energy harvesting according to an embodiment of the present invention, including:
a thermoelectric generator TEG1 for converting thermal energy into a first electrical signal;
the BOOST power stage sub-circuit 2 is electrically connected with the thermoelectric generator TEG1 and is used for processing the first electric signal to obtain a second electric signal;
the detection sub-circuit 3 is electrically connected with the BOOST power level sub-circuit 2 and is used for detecting the second electric signal to obtain a third electric signal;
the sampling and mode selection sub-circuit 4 is electrically connected with the BOOST power level sub-circuit 2 and is used for generating a fourth electric signal according to the open-circuit voltage;
the maximum power point tracking sub-circuit 5 is electrically connected with the BOOST power level sub-circuit 2 and is used for generating a fifth electric signal according to the open-circuit voltage and the real-time voltage;
and the logic and gate driving sub-circuit 6 is electrically connected to the sampling and mode selecting sub-circuit 4, the detecting sub-circuit 3, the maximum power point tracking sub-circuit 5 and the BOOST power stage sub-circuit 2, and is configured to select different modes according to the fourth electrical signal and generate a first logic signal according to the third electrical signal and the fifth electrical signal so as to control a processing process of the BOOST power stage sub-circuit 2 on the first electrical signal.
Referring to fig. 2, fig. 2 is a schematic diagram of another structure of a multi-mode BOOST converter applied to thermoelectric energy harvesting according to an embodiment of the present invention;
in the present embodiment, the thermoelectric generator TEG includes a voltage source Vs and a source resistor Rs, which are mainly used for energy conversion between thermal energy and electric energy. The thermoelectric generator TEG converts the thermal energy into voltage, that is, the first electrical signal is output to the BOOST power stage sub-circuit, and the BOOST power stage sub-circuit performs boosting processing on the first electrical signal.
In this embodiment, the BOOST power stage sub-circuit includes: sampling capacitor CINInductor L, first NMOS tube MN1The first PMOS transistor MP1A load capacitor CLA first diode D1A second diode D2(ii) a Wherein,
first diode D1And a second diode D2Are sequentially connected between a power supply end VDD and a ground end GND in series;
load capacitance CLIs connected between a power supply end VDD and a ground end GND in series;
first PMOS transistor MP1The inductor L and the thermoelectric generator TEG are sequentially connected in series between a power supply end VDD and a ground end GND;
sampling capacitor CINIs connected in series with a node V formed by connecting an inductor L and a thermoelectric generator TEG in seriesINAnd the ground end GND;
first NMOS transistor MN1Is connected in series with a first PMOS tube MP1A node SW formed by connecting the inductor L in series is connected with a ground end GND;
first PMOS transistor MP1The grid is electrically connected with the output end of the logic and grid driving sub-circuit;
first NMOS transistor MN1The grid is electrically connected with the output end of the logic and grid driving sub-circuit.
In this embodiment, the BOOST power stage sub-circuit is mainly used to implement the BOOST function. The BOOST principle of the BOOST converter is described as follows: the operation process of the BOOST converter can be divided into a charging process and a discharging process. Under the charging process, the first NMOS tube MN1Conducting the first PMOS transistor MP1Turning off, the current flows through the inductor L and the first NMOS transistor MN1As the charging process continues, the current on the inductor L increases linearly and stores energy, wherein the inductor current is the second electrical signal in this embodiment; under the discharge process, the first NMOS tube MN1Turn off, first PMOS transistor MP1When the inductor L is conducted, the current on the inductor L does not suddenly change to zero and flows through the first PMOS tube MP1And to a load capacitor CLAnd charging is carried out, so that the effect of boosting is achieved.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a detection sub-circuit according to an embodiment of the invention; in this embodiment, the detection sub-circuit, that is, the inductor current valley detection sub-circuit, includes: first switch S1A second switch S2A first resistor R1A first comparator COMP1(ii) a Wherein,
first switch S1Connected in series with the SW terminal of the BOOST power stage sub-circuit and the first comparator COMP1Between the positive input ends;
a second switch S2And a first resistor R1Sequentially connected in series with the SW terminal of the BOOST power stage sub-circuit and the first comparator COMP1Between the positive input ends;
first comparator COMP1The reverse input end is electrically connected with a power supply end VDD, and the output end is electrically connected with the input end of the logic and grid driving sub-circuit.
In this embodiment, the detection sub-circuit is mainly used to detect the current valley of the SW node in the BOOST power stage sub-circuit, i.e. the second electrical signal, compare it with the power source terminal VDD potential, output the comparison result, i.e. the third signal, to the logic and gate driving sub-circuit, and the output of the logic and gate driving sub-circuit, i.e. the first logic signal, controls the first logic signalPMOS tube MP1When the potential difference between the node SW and the power supply terminal VDD is zero, that is, the current flowing through the inductor L is zero, the first PMOS transistor M is turned offP1Thereby improving efficiency.
In the present embodiment, the first comparator COMP1Compared with the traditional zero-crossing comparator, the high-precision offset calibration comparator improves the robustness of the circuit. In addition, the first comparator COMP is used in three operation modes, i.e., discontinuous conduction mode, critical conduction mode and continuous conduction mode1The multiplexing of (a) reduces the size and complexity of the circuit.
In this embodiment, the sampling and mode selection sub-circuit includes: fifth comparator COMP5A sixth comparator COMP6(ii) a Wherein,
fifth comparator COMP5The inverting input terminals are respectively and electrically connected with a sixth comparator COMP6Node V formed by connecting forward input end, inductor L and thermoelectric generator TEG in seriesIN；
Fifth comparator COMP5The positive input end is electrically connected with a first reference voltage end VREF1；
Sixth comparator COMP6The reverse input end is electrically connected with a second reference voltage end VREF2；
Fifth comparator COMP5And a sixth comparator COMP6The output ends are respectively and electrically connected with the input ends of the logic and grid electrode driving sub-circuits.
In the embodiment, the first reference voltage is 40mV, the second reference voltage is 100mV, and the sampling and mode selection sub-circuit collects the open-circuit voltage V of the TEGSAnd a fifth comparator COMP540mV reference voltage V at positive input endREF1And a sixth comparator COMP6100mV reference voltage V at inverting input terminalREF2And comparing, and outputting a comparison result, namely a fourth electric signal to the logic and grid driving sub-circuit, wherein the logic and grid driving sub-circuit controls the starting of a corresponding circuit to finish the selection of three working modes, namely a discontinuous conduction mode, a critical conduction mode and a continuous conduction mode. When surpassingWhen the low input is 10mV to 40mV, a discontinuous conduction mode with the minimum switching loss is adopted, the input is transited by adopting a critical conduction mode when 40mV to 100mV, and the continuous conduction mode with the minimum conduction loss is adopted when 100mV to 500mV, so that the circuit loss is reduced to the maximum extent by a mixed mode of three working modes, and the conversion efficiency is improved.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a maximum power point tracking sub-circuit according to an embodiment of the present invention; in this embodiment, the maximum power point tracking sub-circuit 5 includes: discontinuous conduction mode conduction time control circuit TON_DCMControl, voltage divider circuit 51, second comparator COMP25BIT counter 5BIT, discontinuous conduction mode period length control circuit TSW_DCMControl, critical conduction mode and continuous conduction mode conduction time Control circuit TON_CRM&CCMControl; wherein, the voltage dividing circuit 51 and the second comparator COMP2Is sequentially connected in series with a node V formed by serially connecting the inductor L and the thermoelectric generator TEGINAnd the 5-BIT counter 5 BIT;
the 5-BIT counter 5BIT is respectively and electrically connected with the discontinuous conduction mode period length control circuit TSW_DCMControl and critical conduction mode and continuous conduction mode conduction time Control circuit TON_CRM&CCM Control；
The discontinuous conduction mode period length control circuit TSW_DCMControl and critical conduction mode and continuous conduction mode conduction time Control circuit TON_CRM&CCMThe output end of the Control is respectively and electrically connected with the input end of the logic and grid driving sub-circuit 6;
the discontinuous conduction mode conduction time control circuit TON_DCMControl is connected in series with the open-circuit voltage V of the thermoelectric generatorSAnd between the logic and gate drive sub-circuit inputs.
In this embodiment, the maximum power point tracking sub-circuit mainly functions to divide the open-circuit voltage of the thermoelectric generator TEG, compare the divided voltage with the real-time output voltage, and further adjust the output voltage, so that the thermoelectric energy obtaining device always outputs the maximum power.
Referring to fig. 5, fig. 5 is a circuit for controlling the on-time of the discontinuous conduction mode according to an embodiment of the present inventionON_DCMA schematic of the structure of Control; in this embodiment, the on-time control circuit T in discontinuous conduction modeON_DCMThe Control includes: operational amplifier OA, third NMOS tube MN3And the fourth NMOS tube MN4The fifth NMOS transistor MN5A second PMOS transistor MP2And the third PMOS transistor MP3And the fourth PMOS transistor MP4The fifth PMOS transistor MP5A second resistor R2A first capacitor C1A third comparator COMP3(ii) a Wherein,
the positive input of the operational amplifier OA is electrically connected to the open-circuit voltage V of the thermoelectric generator TEG1SThe reverse input end is electrically connected with the third NMOS tube MN3And the second resistor R2The output end of the node formed by serial connection is electrically connected with the third NMOS tube MN3A gate electrode of (1);
the fourth PMOS tube MP4The second PMOS tube MP2The third NMOS tube MN3And the second resistor R2Are sequentially connected between a power supply end VDD and a ground end GND in series;
the fifth PMOS tube MP5The third PMOS tube MP3And the fourth NMOS tube MN4And the fifth NMOS tube MN5Are connected in series between a power supply end VDD and a ground end GND in sequence;
the first capacitor C1Is connected in series with the third PMOS tube MP3And the fifth NMOS tube MP5The nodes formed by the serial connection are connected with a ground end GND;
the third PMOS tube MP3And the first capacitor C1Node formed by concatenation c1 electrically connecting said third comparator COMP3The inverting input terminal of (1);
the third comparator COMP3Is electrically connected with a reference voltage end VREFThe output end of the logic and grid drive sub-circuit is electrically connected with the input end of the logic and grid drive sub-circuit;
the second PMOS tube MP2The grid electrode of the NMOS transistor is electrically connected with the third NMOS transistor MN3A drain electrode of (1);
the fourth PMOS tube MP4The grid electrode of the second PMOS tube M is electrically connected with the second PMOS tube MP2A source electrode of (a);
the second PMOS tube MP2The grid electrode of the PMOS transistor is electrically connected with the third PMOS transistor MP3A gate electrode of (1);
the fourth PMOS tube MP4The grid electrode of the PMOS transistor is electrically connected with the fifth PMOS transistor MP5A gate electrode of (1);
the fourth NMOS tube MN4The grid of the grid is electrically connected with an enabling end VEN;
the fifth NMOS tube MN5The gate of the logic and gate drive sub-circuit is electrically connected with the output end of the logic and gate drive sub-circuit.
In this embodiment, the on-time control circuit T in discontinuous conduction modeON_DCMThe Control is mainly used for controlling the first NMOS transistor M in the discontinuous conduction modeN1The on-time of (c). The discontinuous conduction mode conduction time control circuit T will be described in detailON_DCMControl principle: in discontinuous conduction mode, the conduction time TON_DCMUsing a constant peak current control mode, i.e. peak current IpeakConstant, at this time, the on-time TON_DCMTEG open circuit voltage V only with thermoelectric generatorSIn inverse proportion. Assuming that the period starts, the third comparator COMP3The output is high level, the fourth NMOS tube MN4And a fifth NMOS transistor MN5Are all in an off state, an open circuit voltage VSIncrease, then give the first capacitance C1Bias current of charge IbiasIncreasing, then the Node c1 is charged to a reference voltage VREFBecomes short, thereby causing the third comparator COMP3The output high level time is shortened, thereby controlling the conduction time TON_DCMWhen the next period starts, the logic and grid drive sub-circuit outputs high level to make the fifth NMOS tube MN5Is turned on to make the third comparator COMP3The output returns to a high level.
Referring to FIG. 2, in the present embodiment, the components are shownThe voltage circuit 51 includes: third switch S3And a fourth switch S4The fifth switch S5A second capacitor C2A third capacitor C3(ii) a Wherein,
the third switch S3Connected in series to said second comparator COMP2Between the forward input end and the reverse input end;
the second capacitor C2Connected in series to said second comparator COMP2Between the inverting input terminal and the ground terminal GND;
the fourth switch S4And the third capacitor C3Are sequentially connected in series with the second comparator COMP2Between the inverting input terminal and the ground terminal GND;
the fifth switch S5Is connected in series with the fourth switch S4And the third capacitor C3The nodes formed by the series connection are connected with the ground terminal GND.
In the present embodiment, the voltage divider circuit is mainly used to divide the open-circuit voltage V of the thermoelectric generator TEGSIs divided into VS/2。
Referring to fig. 6, fig. 6 is a circuit for controlling the discontinuous conduction mode cycle length T according to an embodiment of the present inventionSW_DCMA schematic of the structure of Control; in this embodiment, the discontinuous conduction mode cycle length control circuit TSW_DCMThe Control includes: sixth NMOS transistor MN6And a seventh NMOS transistor MN7And the eighth NMOS transistor MN8And a ninth NMOS transistor MN9The tenth NMOS transistor MN10Eleventh NMOS transistor MN11Sixth PMOS transistor MP6Seventh PMOS transistor MP7Eighth PMOS transistor MP8Ninth PMOS transistor MP9Tenth PMOS transistor MP10And a sixth switch group S6iAnd a seventh switch group S7iThe eighth switch group S8iAnd a ninth switch group S9iThe tenth switch group S10iAnd a fourth capacitor group C4iThe fifth capacitor group C5iAnd a sixth capacitor group C6iAnd a seventh capacitor group C7iAnd the eighth capacitor bank C8iAnd a ninth capacitor bank C9iI is 1,2, 3; wherein,
the sixth mentionedNMOS tube MN6Connected in series to a bias current IbiasAnd the ground end GND;
the sixth PMOS tube MP6And the seventh NMOS tube MN7Are sequentially connected between a power supply end VDD and a ground end GND in series;
the seventh PMOS tube MP7And the eighth NMOS tube MN8Are sequentially connected between a power supply end VDD and a ground end GND in series;
the eighth PMOS tube MP8And the ninth NMOS tube MN9Are sequentially connected between a power supply end VDD and a ground end GND in series;
the ninth PMOS tube MP9And the tenth NMOS transistor MN10Are sequentially connected between a power supply end VDD and a ground end GND in series;
the tenth PMOS tube MP10And the eleventh NMOS tube MN11Sequentially connected between a power supply terminal VDD and a ground terminal GND in series, and a common terminal thereof is used as an output terminal VTSWConnecting the logic and gate drive subcircuit 6;
the seventh NMOS tube MN7The grid electrode of the NMOS transistor is electrically connected with the sixth NMOS transistor MN6A gate and a drain;
the seventh PMOS tube MP7The eighth PMOS tube MP8The ninth PMOS transistor MP9The tenth PMOS tube MP10The grid electrodes of the PMOS tubes are respectively and electrically connected with the sixth PMOS tube MP6A gate and a drain;
the ninth NMOS tube MN9Is electrically connected with the eighth NMOS tube MN8The drain forms a node VC1；
The tenth NMOS transistor MN10The grid electrode of the NMOS transistor is electrically connected with the ninth NMOS transistor MN9The drain forms a node VC2；
The eighth NMOS tube MN8The grid of the NMOS transistor is electrically connected with the eleventh NMOS transistor MN11Is electrically connected with the tenth NMOS tube MN10The drain forms a node VC3；
The fourth capacitor bank C4iConnected in series to a node VCii is between 1,2,3 and the ground end GND;
the above-mentionedSixth switch group S6iAnd the fifth capacitor group C5iAre sequentially connected in series with a node VCi(i ═ 1,2,3) to ground GND;
the seventh switch group S7iAnd the sixth capacitor group C6iAre sequentially connected in series with a node VCi(i ═ 1,2,3) to ground GND;
the eighth switch group S8iAnd the seventh capacitor bank C7iAre sequentially connected in series with a node VCi(i ═ 1,2,3) to ground GND;
the ninth switch group S9iAnd the eighth capacitor bank C8iAre sequentially connected in series with a node VCi(i ═ 1,2,3) to ground GND;
the tenth switch group S10iAnd the ninth capacitor bank C9iAre sequentially connected in series with a node VCi( i 1,2,3) to ground GND.
In this embodiment, the discontinuous conduction mode cycle length control circuit TSW_DCMControl is mainly used to Control the length of the discontinuous conduction mode period. The discontinuous conduction mode cycle length control circuit T will be described in detailSW_DCMControl principle: voltage-dividing circuit voltage-dividing thermoelectric generator open-circuit voltage VSAnd maintain VSAnd/2, comparing the real-time output voltage with the comparator, and if the output voltage is less than VSAnd/2, adding 1 to the 5BIT counter 5BIT count so as to control the discontinuous conduction mode cycle length control circuit TSW_DCMThe switch in the programmable capacitor array in Control is opened, so that the number of parallel capacitors of the programmable capacitor array is increased, and VC1、VC2、VC3And the capacitance at the node is increased, so that the output period of the oscillator is increased, and the control of the period length by the discontinuous conduction mode period length control circuit is realized.
Referring to fig. 7, fig. 7 is a circuit for controlling the on-time of the critical conduction mode and the continuous conduction mode according to the embodiment of the inventionON_CRM&CCMA schematic of the structure of Control; in this embodiment, the on-time control circuit T for the critical conduction mode and the continuous conduction modeON_CRM&CCMThe Control includes: bias current source IbiasInverter INV and twelfth NMOS transistor MN12Thirteenth NMOS transistor MN13The eleventh switch S11And a twelfth switch S12And a thirteenth switch S13And a fourteenth switch S14The fifteenth switch S15A tenth capacitor C10An eleventh capacitor C11And a twelfth capacitor C12A thirteenth capacitor C13And a fourteenth capacitor C14A fifteenth capacitor C15A fourth comparator COMP4(ii) a Wherein,
the bias current source IbiasAnd the twelfth NMOS tube MN12And the thirteenth NMOS tube MN13Are connected in series between a power supply end VDD and a ground end GND in sequence;
the tenth capacitor C10Is connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the eleventh switch S11And the eleventh capacitor C11Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the twelfth switch S12And the twelfth capacitor C12Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the thirteenth switch S13And the thirteenth capacitor C13Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the fourteenth switch S14And the fourteenth capacitance C14Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the fifteenth switch S15And the fifteenth capacitor C15Are sequentially connected in series with the bias current source IbiasAnd the twelfth NMOS tube MN12The nodes formed by the serial connection are connected with a ground end GND;
the fourth comparator COMP4The positive input end is electrically connected with a reference voltage end VREFThe reverse phase input end is electrically connected with the bias current source IbiasAnd the twelfth NMOS tube MN12The output end of the node is electrically connected with the input end of the logic and grid electrode driving sub-circuit;
the inverter INV is connected in series with the enable terminal VEN and the twelfth NMOS tube MN12Between the grids;
the thirteenth NMOS tube MN13The gate is electrically connected to the output of the logic and gate drive sub-circuit 5.
In the present embodiment, the on-time control circuit T in the critical conduction mode and the continuous conduction modeON_CRM&CCMThe Control is mainly used for controlling the first NMOS transistor M in the critical conduction mode and the continuous conduction modeN1The on-time of (c). The critical conduction mode and continuous conduction mode conduction time control circuit T will be described in detailON_CRM&CCMControl principle: assuming that the period starts, the fourth comparator COMP4The output is high level, the twelfth NMOS tube MN12And thirteenth NMOS tube MN13Are all in an off state. The voltage division circuit divides the open-circuit voltage of the thermoelectric generator and keeps VSAnd/2, comparing the real-time output voltage with the comparator, and if the output voltage is less than VSAnd/2, adding 1 to the 5BIT counter 5BIT count so as to control the conduction time control circuit T in the critical conduction mode and the continuous conduction modeON_CRM&CCMThe switch in the programmable capacitor array in the Control is opened, so that the number of the parallel capacitors of the programmable capacitor array is increased, and then the Node c2 is charged to a reference voltage VREFBecomes long, thereby causing the fourth comparator COMP4The output high level time is increased to control the on-time TON_CRM&CCMWhen the next period starts, the logic and gate driving sub-circuit outputs high level to make the thirteenth NMOS transistor MN13Is conducted to further enableFour comparators COMP4The output returns to a high level.
In this embodiment, after the logic and gate driving sub-circuit controls the corresponding circuit to turn on and complete the selection of the discontinuous conduction mode, the critical conduction mode and the continuous conduction mode, the maximum power point tracking sub-circuit mainly functions to divide the open-circuit voltage of the thermoelectric generator TEG, compare the divided voltage with the real-time output voltage, and output the comparison result, i.e., the fifth electrical signal, to the logic and gate driving sub-circuit, and the logic and gate driving sub-circuit adjusts the output voltage accordingly, so that the thermoelectric energy obtaining device always outputs the maximum power.
Example two
The beneficial effects of the present invention are further explained by simulation tests.
Referring to fig. 8, fig. 8 is a waveform diagram of simulation of continuous conduction mode according to an embodiment of the present invention; wherein, the simulation curve shows from top to bottom: the first curve VIN is the input voltage, the second curve VDD is the output voltage, the third curve L0 is the current flowing through the inductor L, and the fourth curve D2 is the current flowing through the second diode D2The load current of (1); maximum power point tracking efficiency eta in continuous conduction modeMPPT_CCMComprises the following steps:
Figure BDA0002221404750000211
in this embodiment, VS280mV, data in the alternative graph is available, maximum power point tracking efficiency η in continuous conduction modeMPPT_CCMThe content was 97.5%.
In addition, the conversion efficiency η in the continuous conduction modeCCMComprises the following steps:
Figure BDA0002221404750000221
the data in the alternative map is available, the conversion efficiency eta in the continuous conduction modeCCMThe content was 92.7%.
Referring to fig. 9, fig. 9 is a waveform diagram of a discontinuous conduction mode simulation according to an embodiment of the present invention; wherein, the simulation curve shows from top to bottom: the first curve VIN is the input voltage, the second curve VDD is the output voltage, the third curve L0 is the current flowing through the inductor L, and the fourth curve D2 is the current flowing through the second diode D2The load current of (1); maximum power point tracking efficiency eta in discontinuous conduction modeMPPT_DCMComprises the following steps:
Figure BDA0002221404750000222
in this embodiment, VS10mV, the data in the graph can be obtained, and the maximum power point tracking efficiency eta is under the discontinuous conduction modeMPPT_DCMThe content was 97.1%.
In addition, the conversion efficiency η in the discontinuous conduction modeDCMComprises the following steps:
Figure BDA0002221404750000223
the conversion efficiency eta in discontinuous conduction mode is obtained by substituting the data in the graphDCMThe content was 32.8%.
Therefore, the maximum power point tracking efficiency of the multi-mode BOOST converter applied to thermal energy acquisition can reach more than 95% in all working modes, and the peak efficiency of the multi-mode BOOST converter in the continuous conduction mode is 92.7% (V)S280mV), the efficiency can reach 32.8% when the discontinuous conduction mode is input with 10 mV.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (8)

1. A multi-mode BOOST converter for thermoelectric energy harvesting, comprising:
a thermoelectric generator TEG (1) for converting thermal energy into a first electrical signal;
the BOOST power level sub-circuit (2) is electrically connected with the thermoelectric generator TEG (1) and is used for processing the first electric signal to obtain a second electric signal;
the detection sub-circuit (3) is electrically connected with the BOOST power level sub-circuit (2) and is used for detecting the second electric signal to obtain a third electric signal;
the sampling and mode selection sub-circuit (4) is electrically connected with the BOOST power level sub-circuit (2) and is used for generating a fourth electric signal according to the open-circuit voltage;
the maximum power point tracking sub-circuit (5) is electrically connected with the BOOST power level sub-circuit (2) and is used for generating a fifth electric signal according to the open-circuit voltage and the real-time voltage; wherein the maximum power point tracking sub-circuit (5) comprises: discontinuous conduction mode conduction time control circuit (T)ON_DCMControl), a voltage division circuit (51), a second Comparator (COMP)2) 5BIT counter (5BIT), discontinuous conduction mode cycle length control circuit (T)SW_DCMControl), critical conduction mode and continuous conduction mode conduction time Control circuit (T)ON_CRM&CCMControl); wherein,
the voltage dividing circuit (51) and the second Comparator (COMP)2) Is sequentially connected in series with a node (V) formed by connecting an inductor (L) and the thermoelectric generator TEG (1) in seriesIN) And said 5-BIT counter (5 BIT);
the 5-BIT counter (5BIT) is respectively electrically connected with the discontinuous conduction mode period length control circuit (T)SW_DCMControl) and the critical conduction mode and continuous conduction mode conduction time Control circuit (T)ON_CRM&CCM Control)；
The discontinuous conduction mode period length control circuit (T)SW_DCMControl) and a critical conduction mode and continuous conduction mode conduction time Control circuit (T)ON_CRM&CCMControl) is respectively and electrically connected with the input end of the logic and grid drive sub-circuit (6);
said discontinuous conduction mode conduction time control circuit (T)ON_DCMControl) connected in series to the open-circuit voltage (V) of the thermoelectric generatorS) And the input end of the logic and grid drive sub-circuit;
and the logic and grid electrode driving sub-circuit (6) is electrically connected with the sampling and mode selecting sub-circuit (4), the detecting sub-circuit (3), the maximum power point tracking sub-circuit (5) and the BOOST power level sub-circuit (2) and is used for selecting different modes according to the fourth electric signal and generating a first logic signal according to the third electric signal and the fifth electric signal so as to control the BOOST power level sub-circuit (2) to process the first electric signal.
2. A multi-mode BOOST converter according to claim 1, characterised in that said BOOST power stage sub-circuit (2) comprises: input capacitance (C)IN) The inductor (L) and the first NMOS tube (M)N1) A first PMOS transistor (M)P1) Load capacitance (C)L) A first diode (D)1) A second diode (D)2) (ii) a Wherein,
the first diode (D)1) And the second diode (D)2) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;
the load capacitance (C)L) Is connected between a power supply end (VDD) and a ground end (GND) in series;
the first PMOS tube (M)P1) The inductor (L) and the thermoelectric generator TEG (1) are sequentially connected in series between a power supply end (VDD) and a ground end (GND);
the input capacitance (C)IN) A node (V) formed by the inductor (L) and the thermoelectric generator (TEG) in series connectionIN) And the ground terminal (GND);
the first NMOS transistor (M)N1) Is connected in series with the first PMOS tube (M)P1) A node (SW) end formed by connecting the inductor (L) in series is connected between a ground end (GND);
the first PMOS tube (M)P1) The grid is electrically connected with the output end of the logic and grid driving sub-circuit;
the first NMOS transistor (M)N1) The grid is electrically connected with the output end of the logic and grid driving sub-circuit (6).
3. A multi-mode BOOST converter according to claim 1, characterized in that said detection sub-circuit (3) comprises: a first switch (S1), a second switch (S2), a first resistor (R1), a first comparator (COMP 1); wherein,
the first switch (S1) is connected in series between a node (SW) terminal of the BOOST power stage sub-circuit and a positive input terminal of the first comparator (COMP 1);
the second switch (S2) and the first resistor (R1) are sequentially connected in series between a node (SW) end of the BOOST power stage sub-circuit and a positive input end of the first comparator (COMP 1);
the reverse input end of the first comparator (COMP1) is electrically connected with a power supply end (VDD), and the output end of the first comparator is electrically connected with the input end of the logic and gate drive sub-circuit (6).
4. A multi-mode BOOST converter according to claim 1, characterized in that said discontinuous conduction mode conduction time control circuit (Tp)ON_DCMControl) includes: operational Amplifier (OA), third NMOS transistor (M)N3) And the fourth NMOS transistor (M)N4) And the fifth NMOS transistor (M)N5) And a second PMOS transistor (M)P2) And the third PMOS tube (M)P3) And the fourth PMOS tube (M)P4) And the fifth PMOS tube (M)P5) A second resistor (R)2) A first capacitor (C)1) A third Comparator (COMP)3) (ii) a Wherein,
the positive input of the Operational Amplifier (OA) is electrically connected to the open-circuit voltage (V) of the thermoelectric generator TEG (1)S) And the reverse input end is electrically connected with the third NMOS tube (M)N3) And the second resistance (R)2) A node formed by series connection, and the output end is electrically connected with the third NMOS tube (M)N3) A gate electrode of (1);
the fourth PMOS tube (M)P4) The second PMOS tube (M)P2) The third NMOS tube (M)N3) And the second resistor (R)2) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;
the fourth NMOS transistor (M)N4) And the fifth NMOS transistor (M)N5) After being connected in parallel with the third PMOS tube (M)P3) The fifth PMOS tube (M)P5) Are sequentially connected between a grounding end (GND) and a power end (VDD) in series;
the first capacitor (C)1) Is connected in series with the third PMOS tube (M)P3) And the fifth NMOS transistor (M)P5) Between the node formed by series connection and the grounding end (GND);
the third PMOS tube (M)P3) And said first capacitance (C)1) Nodes formed in seriesc1) Electrically connecting the third Comparator (COMP)3) The inverting input terminal of (1);
said third Comparator (COMP)3) Is electrically connected to the reference voltage terminal (V)REF) The output end of the logic and grid drive sub-circuit is electrically connected with the input end of the logic and grid drive sub-circuit;
the second PMOS tube (M)P2) Is electrically connected with the third NMOS tube (M)N3) A drain electrode of (1);
the fourth PMOS tube (M)P4) Is electrically connected with the second PMOS tube (M)P2) A source electrode of (a);
the second PMOS tube (M)P2) Is electrically connected with the third PMOS tube (M)P3) A gate electrode of (1);
the fourth PMOS tube (M)P4) Is electrically connected with the fifth PMOS tube (M)P5) A gate electrode of (1);
the fourth NMOS transistor (M)N4) Is electrically connected with the enable terminal (VEN);
the fifth NMOS transistor (M)N5) Is electrically connected to the output of the logic and gate drive sub-circuit (6).
5. A multi-mode BOOST converter according to claim 1, characterised in that said voltage divider circuit (51) comprises: third switch (S)3) And a fourth switch (S)4) And a fifth switch (S)5) A second capacitor (C)2) A third capacitor (C)3) (ii) a Wherein,
the third switch (S)3) Connected in series to said second Comparator (COMP)2) Between the forward input end and the reverse input end;
the second capacitance (C)2) Connected in series to said second Comparator (COMP)2) Between the inverting input terminal and the ground terminal (GND);
the fourth switch (S)4) And said third capacitance (C)3) Are sequentially connected in series to the second Comparator (COMP)2) Between the inverting input terminal and the ground terminal (GND);
the fifth switch (S)5) Is connected in series to the fourth switch (S)4) And said third capacitance (C)3) The nodes formed by the series connection are connected with a ground terminal (GND).
6. A multi-mode BOOST converter according to claim 1, characterized in that said discontinuous conduction mode period length control circuit (Tp)SW_DCMControl) includes: sixth NMOS transistor (M)N6) And the seventh NMOS transistor (M)N7) And the eighth NMOS transistor (M)N8) And the ninth NMOS tube (M)N9) And the tenth NMOS transistor (M)N10) And the eleventh NMOS tube (M)N11) And the sixth PMOS tube (M)P6) And the seventh PMOS tube (M)P7) And the eighth PMOS tube (M)P8) And the ninth PMOS tube (M)P9) Tenth PMOS tube (M)P10) And a sixth switch group S6iAnd a seventh switch group S7iThe eighth switch group S8iAnd a ninth switch group S9iThe tenth switch group S10iAnd a fourth capacitor group C4iThe fifth capacitor group C5iAnd a sixth capacitor group C6iAnd a seventh capacitor group C7iAnd the eighth capacitor bank C8iAnd a ninth capacitor bank C9iI =1,2, 3; wherein,
the sixth NMOS transistor (M)N6) Connected in series to a bias current (I)bias) And the ground terminal (GND);
the sixth PMOS tube (M)P6) And the seventh NMOS transistor (M)N7) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;
the seventh PMOS tube (M)P7) Andthe eighth NMOS transistor (M)N8) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;
the eighth PMOS tube (M)P8) And the ninth NMOS transistor (M)N9) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;
the ninth PMOS tube (M)P9) And the tenth NMOS transistor (M)N10) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;
the tenth PMOS tube (M)P10) And the eleventh NMOS transistor (M)N11) Sequentially connected in series between a power supply terminal (VDD) and a ground terminal (GND), with a common terminal thereof as an output terminal VTSWConnecting the logic and gate drive subcircuit (6);
the seventh NMOS transistor (M)N7) Is electrically connected with the sixth NMOS tube (M)N6) A gate and a drain;
the seventh PMOS tube (M)P7) The eighth PMOS tube (M)P8) The ninth PMOS tube (M)P9) The tenth PMOS tube (M)P10) The grid electrodes of the first and second PMOS tubes are respectively and electrically connected with the sixth PMOS tube (M)P6) A gate and a drain;
the ninth NMOS transistor (M)N9) Is electrically connected with the eighth NMOS tube (M)N8) The drain forms a node VC1；
The tenth NMOS transistor (M)N10) Is electrically connected with the ninth NMOS tube (M)N9) The drain forms a node VC2；
The eighth NMOS transistor (M)N8) Is electrically connected with the eleventh NMOS tube (M)N11) And the tenth NMOS transistor (M)N10) Drain electrode to form node VC3；
The fourth capacitor bank C4iConnected in series to a node VCiI =1,2,3 with Ground (GND);
the sixth switch group S6iAnd the fifth capacitor group C5iAre sequentially connected in series with a node VCiI =1,2,3 with Ground (GND);
the seventh switch group S7iAnd the sixth capacitor group C6iAre sequentially connected in series with a node VCiI =1,2,3 with Ground (GND);
the eighth switch group S8iAnd the seventh capacitor bank C7iAre sequentially connected in series with a node VCiI =1,2,3 with Ground (GND);
the ninth switch group S9iAnd the eighth capacitor bank C8iAre sequentially connected in series with a node VCiI =1,2,3 with Ground (GND);
the tenth switch group S10iAnd the ninth capacitor bank C9iAre sequentially connected in series with a node VCiAnd Ground (GND), i =1,2, 3.
7. A multi-mode BOOST converter according to claim 1, characterized in that said critical conduction mode and continuous conduction mode conduction time control circuit (T)ON_CRM&CCMControl) includes: bias current source (I)bias) Inverter (INV) and twelfth NMOS transistor (M)N12) Thirteenth NMOS transistor (M)N13) And an eleventh switch (S)11) And a twelfth switch (S)12) And a thirteenth switch (S)13) And a fourteenth switch (S)14) And a fifteenth switch (S)15) A tenth capacitor (C)10) An eleventh capacitor (C)11) A twelfth capacitor (C)12) A thirteenth capacitor (C)13) A fourteenth capacitor (C)14) A fifteenth capacitor (C)15) A fourth Comparator (COMP)4) (ii) a Wherein,
the bias current source (I)bias) And the twelfth NMOS tube (M)N12) And the thirteenth NMOS tube (M)N13) Are connected in series between a power supply terminal (VDD) and a ground terminal (GND) in sequence;
the tenth capacitance (C)10) Is connected in series to the bias current source (I)bias) And the twelfth NMOS tube (M)N12) Between the node formed by series connection and the grounding end (GND);
the eleventh switch (S)11) And the eleventh capacitance (C)11) Are sequentially connected in series with the bias current source (I)bias) And the twelfth NMOS tube (M)N12) Sections formed by series connectionA point and a Ground (GND);
the twelfth switch (S)12) And the twelfth capacitance (C)12) Are sequentially connected in series with the bias current source (I)bias) And the twelfth NMOS tube (M)N12) Between the node formed by series connection and the grounding end (GND);
the thirteenth switch (S)13) And the thirteenth capacitor (C)13) Are sequentially connected in series with the bias current source (I)bias) And the twelfth NMOS tube (M)N12) Between the node formed by series connection and the grounding end (GND);
the fourteenth switch (S)14) And the fourteenth capacitance (C)14) Are sequentially connected in series with the bias current source (I)bias) And the twelfth NMOS tube (M)N12) Between the node formed by series connection and the grounding end (GND);
the fifteenth switch (S)15) And the fifteenth capacitance (C)15) Are sequentially connected in series with the bias current source (I)bias) And the twelfth NMOS tube (M)N12) Between the node formed by series connection and the grounding end (GND);
said fourth Comparator (COMP)4) The positive input end is electrically connected with a reference voltage end (V)REF) The reverse phase input end is electrically connected with the bias current source (I)bias) And the twelfth NMOS tube (M)N12) The output end of the node is electrically connected with the input end of the logic and grid electrode driving sub-circuit (6);
the Inverter (INV) is connected in series to an enable terminal (VEN) and the twelfth NMOS tube (M)N12) Between the grids;
the thirteenth NMOS transistor (M)N13) The grid is electrically connected with the output end of the logic and grid driving sub-circuit (5).
8. The multi-mode BOOST converter according to claim 1, wherein said sampling and mode selection sub-circuit comprises: fifth Comparator (COMP)5) And a sixth Comparator (COMP)6) (ii) a Wherein,
said fifth Comparator (COMP)5) The inverting input terminals are respectively electrically connected withSixth Comparator (COMP)6) A node (V) formed by connecting the positive input end with the inductor (L) and the thermoelectric generator TEG (1) in seriesIN)；
Said fifth Comparator (COMP)5) The positive input end is electrically connected with a first reference voltage end (V)REF1)；
Said sixth Comparator (COMP)6) The reverse input terminal is electrically connected with the second reference voltage terminal (V)REF2)；
Said fifth Comparator (COMP)5) And said sixth Comparator (COMP)6) The output ends are respectively and electrically connected with the input ends of the logic and grid electrode driving sub-circuits (6).
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