CN108092502B - The wide loading range adjusting and voltage-reduction switch capacitor DC-DC converter of double mode - Google Patents
The wide loading range adjusting and voltage-reduction switch capacitor DC-DC converter of double mode Download PDFInfo
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- CN108092502B CN108092502B CN201711448968.0A CN201711448968A CN108092502B CN 108092502 B CN108092502 B CN 108092502B CN 201711448968 A CN201711448968 A CN 201711448968A CN 108092502 B CN108092502 B CN 108092502B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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Abstract
The present invention relates to a kind of wide loading range adjusting and voltage-reduction switch capacitor DC-DC converter of double mode, which includes: clock coding drive sub-circuits 11；Switching capacity power sub-circuit 12 is electrically connected the clock coding drive sub-circuits 11；Feedback control sub-circuit 13 is electrically connected the Capacitance Power sub-circuit 12 and exports feedback signal to clock coding drive sub-circuits 11.The wide loading range adjusting and voltage-reduction switch capacitor DC-DC converter of double mode provided by the invention, using the operating mode of two kinds of output voltage management of PFM and Burst, under PFM operating mode, the variation of load adjusts VCO switching frequency by error amplifier EA output signal, two-phase disjoint signals Φ 1 and Φ 2 are generated as switched capacitor array to stabilize the output voltage, guarantees output voltage precision；Stablize the output voltage of underloading by the operating mode of interval in Burst operating mode, so that the load current range of converter at light load is effectively increased, in addition, also improving reaction time and the transfer efficiency of load jump.
Description
Technical field
The invention belongs to microelectronics technology, in particular to a kind of wide loading range adjusting and voltage-reduction switch capacitor of double mode
DC-DC converter.
Background technique
Can portable device complexity requirement of the promotion to power management it is higher and higher, high performance equipment requirement power supply
Energy density is high, and chip area is small, power consumption is lower.Switching Power Supply has high-efficient, small in size and light-weight etc. various excellent
Gesture becomes most widely used power supply.Wherein, switching capacity DC-DC converter is compared to switched inductors type DC-DC converter
It is easily integrated, while saving for inductance also reduces electromagnetic crosstalk to the influence of circuit bring.
But switching capacity DC-DC converter is larger there are output voltage range and unstable and output loading range compared with
The problems such as low, to greatly limit the popularization and application of switching capacity DC-DC converter.
Therefore, how to design a kind of switching capacity DC-DC converter haveing excellent performance just becomes of crucial importance.
Summary of the invention
In order to solve the above-mentioned technical problem, the switching capacity DC-DC that the present invention proposes a kind of wide loading range, has excellent performance
Converter.
Specifically, An embodiment provides a kind of wide loading range adjusting and voltage-reduction switch capacitor DC- of double mode
DC converter.The DC-DC converter 10 includes:
Clock encodes drive sub-circuits 11；
Switching capacity power sub-circuit 12, electrical connection clock encode drive sub-circuits 11；
Feedback control sub-circuit 13 is electrically connected Capacitance Power sub-circuit 12 and exports feedback signal to clock coding driving
Circuit 11.
In one embodiment of the invention, feedback control sub-circuit 13 includes: the first operational transconductance amplifier OTA1, mends
Repay capacitor CC, compensation resistance RC, voltage controlled oscillator VCO, non-overlapping clock generating unit；Wherein,
First operational transconductance amplifier OTA1, voltage controlled oscillator VCO and non-overlapping clock generating unit are sequentially connected in series in opening
Close the output end V of Capacitance Power sub-circuit 12OUTBetween the input terminal of clock coding drive sub-circuits 11；
The output end of the inverting input terminal electrical connection switching capacity power sub-circuit 12 of first operational transconductance amplifier OTA1
VOUT, non-inverting input terminal be electrically connected the first reference voltage end VREF；
Compensate resistance RCWith compensating electric capacity CCIt is sequentially connected in series in the output end and ground terminal of the first operational transconductance amplifier OTA1
Between GND.
In one embodiment of the invention, the first operational transconductance amplifier OTA1 includes: the first PMOS tube MP1, second
PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7、
8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube
MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th
NMOS tube MN9, the tenth NMOS tube MN10, electric current sink ISS, first switch S1And second switch S2；Wherein,
Second PMOS tube MP2, the 4th PMOS tube MP4, the 8th PMOS tube MP8, the 6th NMOS tube MN6And the second NMOS tube MN2According to
It is secondary to be serially connected between power end VDD and ground terminal GND；
First PMOS tube MP1, third PMOS tube MP3, the 7th PMOS tube MP7, the 5th NMOS tube MN5And the first NMOS tube MN1According to
It is secondary to be serially connected between power end VDD and ground terminal GND；
6th PMOS tube MP6, the tenth PMOS tube MP10, the 8th NMOS tube MN8And the 4th NMOS tube MN4It is sequentially connected in series in second
PMOS tube MP2Drain electrode and ground terminal GND between；
5th PMOS tube MP5, the 9th PMOS tube MP9, the 7th NMOS tube MN7And third NMOS tube MN3It is sequentially connected in series in first
PMOS tube MP1Drain electrode and ground terminal GND between；
9th NMOS tube MN9I is sunk with electric currentSSIt is sequentially connected in series in the second PMOS tube MP2Drain electrode and ground terminal GND between；
Tenth NMOS tube MN10It is electrically connected to the first PMOS tube MP1Drain electrode and the 9th NMOS tube MN9Source electrode between；
First PMOS tube MP1Grid be electrically connected the second PMOS tube MP2Grid；
Third PMOS tube MP3Grid be electrically connected the 4th PMOS tube MP4Grid；
7th PMOS tube MP7Grid be electrically connected the 8th PMOS tube MP8Grid；
5th NMOS tube MN5Grid be electrically connected the 6th NMOS tube MN6Grid；
First NMOS tube MN1Grid and the second NMOS tube MN2Grid be electrically connected the 7th PMOS tube MP7Drain electrode；
5th PMOS tube MP5Grid be electrically connected the 6th PMOS tube MP6Grid；
9th PMOS tube MP9Grid be electrically connected the tenth PMOS tube MP10Grid；
7th NMOS tube MN7Grid be electrically connected the 8th NMOS tube MN8Grid；
Third NMOS tube MN3Grid and the 4th NMOS tube MN4Grid be electrically connected the 9th PMOS tube MP9Drain electrode；
9th NMOS tube MN9Grid as the first operational transconductance amplifier OTA1 non-inverting input terminal electrical connection switch electricity
Hold the output end of power sub-circuit 12；
Tenth PMOS tube MP10Grid opened respectively through first as the inverting input terminal of the first operational transconductance amplifier OTA1
Close S1With second switch S2It is electrically connected the first reference voltage end VREF1With the second reference voltage end VREF2；
8th PMOS tube MP8With the 6th NMOS tube MN6The node formed is concatenated as the first operational transconductance amplifier OTA1's
First output end；
Tenth PMOS tube MP10With the 8th NMOS tube MN8The node formed is concatenated as the first operational transconductance amplifier OTA1's
Second output terminal.
In one embodiment of the invention, voltage controlled oscillator VCO includes: the 11st NMOS tube MN11, the 12nd NMOS tube
MN12, the 11st PMOS tube MP11, the 12nd PMOS tube MP12, the first current source IBIAS, the second operational transconductance amplifier OTA2, electricity
Hinder RS, third switch S3, the 4th switch S4, the 5th switch S5, the 6th switch S6, first capacitor C1, the second capacitor C2, first compare
Device CMP and the first d type flip flop D1；Wherein,
11st NMOS tube MN11With the first current source IBIASIt is sequentially connected in series between power end VDD and ground terminal GND；
12nd PMOS tube MP12, the 12nd NMOS tube MN12And resistance RSIt is sequentially connected in series in power end VDD and ground terminal GND
Between；
The non-inverting input terminal of second operational transconductance amplifier OTA2 is electrically connected the 11st NMOS tube MN11Source electrode, reverse phase it is defeated
Enter the 12nd NMOS tube M of end electrical connectionN12Source electrode, output end be electrically connected the 12nd NMOS tube MN12Grid；
5th switch S5With first capacitor C1After parallel connection with third switch S3And the 11st PMOS tube MP11It is sequentially connected in series in connecing
Between ground terminal GND and power end VDD；
6th switch S6With the second capacitor C2After parallel connection with the 4th switch S4It is sequentially connected in series in ground terminal GND and the 11st
PMOS tube MP11Drain electrode between；
The non-inverting input terminal of first comparator CMP is electrically connected third reference voltage end VREF3, inverting input terminal electrical connection the
11 PMOS tube MP11Drain electrode；
The output end of the input end of clock Clk electrical connection first comparator CMP of first d type flip flop D1, the first d type flip flop D1
D input terminal be connected with Q output；
11st NMOS tube MN11Grid as voltage controlled oscillator VCO input terminal be electrically connected the first operational transconductance amplification
The output end of device OTA1；
The Q output of first d type flip flop D1 is defeated as electrical connection clock coding 11 voltage controlled oscillator VCO of drive sub-circuits
Outlet is electrically connected clock and encodes drive sub-circuits 11.
In one embodiment of the invention, the second operational transconductance amplifier OTA2 includes: the 13rd PMOS tube MP13,
14 PMOS tube MP14, the 15th PMOS tube MP15, the 16th PMOS tube MP16, the 13rd NMOS tube MN13, the 14th NMOS tube
MN14, the 15th NMOS tube MN15, the 16th NMOS tube MN16, electric current sink ISSAnd third capacitor CC1；Wherein,
13rd PMOS tube MP13With the 13rd NMOS tube MN13It is sequentially connected in series between power end VDD and ground terminal GND；
14th PMOS tube MP14With the 16th NMOS tube MN16It is sequentially connected in series between power end VDD and ground terminal GND；
Electric current sinks ISS, the 15th PMOS tube MP15And the 14th NMOS tube MN14It is sequentially connected in series in power end VDD and ground terminal
Between GND；
16th PMOS tube MP16With the 15th NMOS tube MN15It is sequentially connected in series and sinks I in electric currentSSBetween ground terminal GND；
Third capacitor CC1It is electrically connected to the 14th PMOS tube MP14With the 16th NMOS tube MN16It concatenates the node formed and connects
Between ground terminal GND；
13rd PMOS tube MP13Grid with drain electrode be connected and be electrically connected the 14th PMOS tube MP14Grid；
14th NMOS tube MN14Grid with drain electrode be connected and be electrically connected the 13rd NMOS tube MN13Grid；
15th NMOS tube MN15Grid with drain electrode be connected and be electrically connected the 16th NMOS tube MN16Grid；
16th PMOS tube MP16Grid as the second operational transconductance amplifier OTA2 non-inverting input terminal be electrically connected the tenth
One NMOS tube MN11Source electrode；
15th PMOS tube MP15Grid as the second operational transconductance amplifier OTA2 inverting input terminal be electrically connected the tenth
Two NMOS tube MN12Source electrode；
14th PMOS tube MP14With the 16th NMOS tube MN16The node formed is concatenated as the second operational transconductance amplifier
The output end of OTA2 is electrically connected the 12nd NMOS tube MN12Grid.
In one embodiment of the invention, non-overlapping clock generating unit includes: the first phase inverter INV1, the second reverse phase
Device INV2, third phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the 7th phase inverter
INV7, the first NAND gate NAND1And the second NAND gate NAND2；Wherein,
First NAND gate NAND1, the second phase inverter INV2, third phase inverter INV3And the 4th phase inverter INV4It is successively serial
Electrical connection；
First phase inverter INV1, the second NAND gate NAND2, the 5th phase inverter INV5, hex inverter INV6And the 7th reverse phase
Device INV7Successively serial electrical connection；
Second NAND gate NAND2The second input terminal be electrically connected to third phase inverter INV3With the 4th phase inverter INV4Concatenation
At the node of formation；
First NAND gate NAND1The second input terminal be electrically connected to hex inverter INV6With the 7th phase inverter INV7Concatenation
At the node of formation；
First phase inverter INV1Input terminal and the first NAND gate NAND1First input end be connected and as it is non-overlapping when
The input terminal that clock generates unit is electrically connected the output end of the first d type flip flop D1；
4th phase inverter INV4Output end and the 7th phase inverter INV7Output end generated respectively as non-overlapping clock it is single
The first output end and second output terminal of member.
Compared with prior art, the present invention at least has the advantages that
The wide loading range adjusting and voltage-reduction switch capacitor DC-DC converter of double mode provided by the invention, using pulse frequency tune
Try the Working mould of (Pulse Frequency Munition, abbreviation PFM) PFM and suspend mode (Burst) two kinds of output voltage management
Formula, under PFM operating mode, the variation of load adjusts VCO switching frequency by error amplifier EA output signal, generates two-phase
Disjoint signals Φ 1 and Φ 2 is stabilized the output voltage as switched capacitor array, guarantees output voltage precision；It works in Burst
Mode stablizes the output voltage of underloading by a kind of operating mode of interval, to effectively increase the load of converter at light load
Current range, and compared with PFM at light load, greatly promote reaction time and the transfer efficiency of load jump.
Detailed description of the invention
Below in conjunction with attached drawing, specific embodiments of the present invention will be described in detail.
Fig. 1 is a kind of wide loading range adjusting and voltage-reduction switch capacitor DC-DC converter of double mode provided in an embodiment of the present invention
Structural schematic diagram；
Fig. 2 is a kind of structural schematic diagram of feedback control sub-circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of first operational transconductance amplifier OTA1 provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of voltage controlled oscillator VCO provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram of second operational transconductance amplifier OTA2 provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram of non-overlapping clock generating unit provided in an embodiment of the present invention；
Fig. 7 is a kind of structure of control circuit of the DC-DC converter provided in an embodiment of the present invention under PFM operating mode
Schematic diagram；
Fig. 8 is a kind of knot of control circuit of the DC-DC converter provided in an embodiment of the present invention under Burst operating mode
Structure schematic diagram；
Fig. 9 is a kind of input-output wave shape of the DC-DC converter provided in an embodiment of the present invention under Burst operating mode
Figure；
Figure 10 is a kind of simulation waveform of the DC-DC converter provided in an embodiment of the present invention under PFM mode；
Figure 11 is a kind of simulation waveform of the DC-DC converter provided in an embodiment of the present invention under Burst mode；
A kind of Figure 12 DC-DC converter provided in an embodiment of the present invention mutually switches in PFM mode and Burst mode
Simulation waveform；
Figure 13 is a kind of property of the DC-DC converter provided in an embodiment of the present invention in PFM mode at light load and Burst mode
It can contrast schematic diagram；
Figure 14 is a kind of turn of the DC-DC converter provided in an embodiment of the present invention in PFM mode at light load and Burst mode
Change efficiency comparative's schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention is described in further details with reference to the accompanying drawing.
Embodiment one
Referring to Figure 1, Fig. 1 is a kind of wide loading range adjusting and voltage-reduction switch capacitor of double mode provided in an embodiment of the present invention
The structural schematic diagram of DC-DC converter.The DC-DC converter 10 includes:
Clock encodes drive sub-circuits 11；
Switching capacity power sub-circuit 12, electrical connection clock encode drive sub-circuits 11；
Feedback control sub-circuit 13 is electrically connected Capacitance Power sub-circuit 12 and exports feedback signal to clock coding driving
Circuit 11.
Further, Fig. 2 is referred to, Fig. 2 is that a kind of structure of feedback control sub-circuit provided in an embodiment of the present invention is shown
It is intended to.The feedback control sub-circuit 13 includes: the first operational transconductance amplifier OTA1, compensating electric capacity CC, compensation resistance RC, it is voltage-controlled
Oscillator VCO, non-overlapping clock generating unit；Wherein,
First operational transconductance amplifier OTA1, voltage controlled oscillator VCO and non-overlapping clock generating unit are sequentially connected in series in opening
Close the output end V of Capacitance Power sub-circuit 12OUTBetween the input terminal of clock coding drive sub-circuits 11；
The output end of the inverting input terminal electrical connection switching capacity power sub-circuit 12 of first operational transconductance amplifier OTA1
VOUT, non-inverting input terminal be electrically connected the first reference voltage end VREF；
Compensate resistance RCWith compensating electric capacity CCIt is sequentially connected in series in the output end and ground terminal of the first operational transconductance amplifier OTA1
Between GND.
Further, Fig. 3 is referred to, Fig. 3 is a kind of first operational transconductance amplifier OTA1 provided in an embodiment of the present invention
Structural schematic diagram；First operational transconductance amplifier OTA1 includes: the first PMOS tube MP1, the second PMOS tube MP2, the 3rd PMOS
Pipe MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th
PMOS tube MP9, the tenth PMOS tube MP10, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4、
5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube
MN10, electric current sink ISS, first switch S1And second switch S2；Wherein,
Second PMOS tube MP2, the 4th PMOS tube MP4, the 8th PMOS tube MP8, the 6th NMOS tube MN6And the second NMOS tube MN2According to
It is secondary to be serially connected between power end VDD and ground terminal GND；
First PMOS tube MP1, third PMOS tube MP3, the 7th PMOS tube MP7, the 5th NMOS tube MN5And the first NMOS tube MN1According to
It is secondary to be serially connected between power end VDD and ground terminal GND；
6th PMOS tube MP6, the tenth PMOS tube MP10, the 8th NMOS tube MN8And the 4th NMOS tube MN4It is sequentially connected in series in second
PMOS tube MP2Drain electrode and ground terminal GND between；
5th PMOS tube MP5, the 9th PMOS tube MP9, the 7th NMOS tube MN7And third NMOS tube MN3It is sequentially connected in series in first
PMOS tube MP1Drain electrode and ground terminal GND between；
9th NMOS tube MN9I is sunk with electric currentSSIt is sequentially connected in series in the second PMOS tube MP2Drain electrode and ground terminal GND between；
Tenth NMOS tube MN10It is electrically connected to the first PMOS tube MP1Drain electrode and the 9th NMOS tube MN9Source electrode between；
First PMOS tube MP1Grid be electrically connected the second PMOS tube MP2Grid；
Third PMOS tube MP3Grid be electrically connected the 4th PMOS tube MP4Grid；
7th PMOS tube MP7Grid be electrically connected the 8th PMOS tube MP8Grid；
5th NMOS tube MN5Grid be electrically connected the 6th NMOS tube MN6Grid；
First NMOS tube MN1Grid and the second NMOS tube MN2Grid be electrically connected the 7th PMOS tube MP7Drain electrode；
5th PMOS tube MP5Grid be electrically connected the 6th PMOS tube MP6Grid；
9th PMOS tube MP9Grid be electrically connected the tenth PMOS tube MP10Grid；
7th NMOS tube MN7Grid be electrically connected the 8th NMOS tube MN8Grid；
Third NMOS tube MN3Grid and the 4th NMOS tube MN4Grid be electrically connected the 9th PMOS tube MP9Drain electrode；
9th NMOS tube MN9Grid as the first operational transconductance amplifier OTA1 non-inverting input terminal electrical connection switch electricity
Hold the output end of power sub-circuit 12；
Tenth PMOS tube MP10Grid opened respectively through first as the inverting input terminal of the first operational transconductance amplifier OTA1
Close S1With second switch S2It is electrically connected the first reference voltage end VREF1With the second reference voltage end VREF2；
8th PMOS tube MP8With the 6th NMOS tube MN6The node formed is concatenated as the first operational transconductance amplifier OTA1's
First output end；
Tenth PMOS tube MP10With the 8th NMOS tube MN8The node formed is concatenated as the first operational transconductance amplifier OTA1's
Second output terminal.
Further, Fig. 4 is referred to, Fig. 4 is a kind of structural representation of voltage controlled oscillator VCO provided in an embodiment of the present invention
Figure；The voltage controlled oscillator VCO includes: the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 11st PMOS tube MP11, the 12nd
PMOS tube MP12, the first current source IBIAS, the second operational transconductance amplifier OTA2, resistance RS, third switch S3, the 4th switch S4、
5th switch S5, the 6th switch S6, first capacitor C1, the second capacitor C2, first comparator CMP and the first d type flip flop D1；Wherein,
11st NMOS tube MN11With the first current source IBIASIt is sequentially connected in series between power end VDD and ground terminal GND；
12nd PMOS tube MP12, the 12nd NMOS tube MN12And resistance RSIt is sequentially connected in series in power end VDD and ground terminal GND
Between；
The non-inverting input terminal of second operational transconductance amplifier OTA2 is electrically connected the 11st NMOS tube MN11Source electrode, reverse phase it is defeated
Enter the 12nd NMOS tube M of end electrical connectionN12Source electrode, output end be electrically connected the 12nd NMOS tube MN12Grid；
5th switch S5With first capacitor C1After parallel connection with third switch S3And the 11st PMOS tube MP11It is sequentially connected in series in connecing
Between ground terminal GND and power end VDD；
6th switch S6With the second capacitor C2After parallel connection with the 4th switch S4It is sequentially connected in series in ground terminal GND and the 11st
PMOS tube MP11Drain electrode between；
The non-inverting input terminal of first comparator CMP is electrically connected third reference voltage end VREF3, inverting input terminal electrical connection the
11 PMOS tube MP11Drain electrode；
The output end of the input end of clock Clk electrical connection first comparator CMP of first d type flip flop D1, the first d type flip flop D1
D input terminal withOutput end is connected；
11st NMOS tube MN11Grid as voltage controlled oscillator VCO input terminal be electrically connected the first operational transconductance amplification
The output end of device OTA1；
The Q output of first d type flip flop D1 is defeated as electrical connection clock coding 11 voltage controlled oscillator VCO of drive sub-circuits
Outlet is electrically connected clock and encodes drive sub-circuits 11.
Wherein, the 11st NMOS tube MN11, the first current source IBIAS, the second operational transconductance amplifier OTA2, the 12nd PMOS
Pipe MP12, the 12nd NMOS tube MN12And resistance RSConstitute current generating circuit.
Further, Fig. 5 is referred to, Fig. 5 is a kind of second operational transconductance amplifier OTA2 provided in an embodiment of the present invention
Structural schematic diagram；Second operational transconductance amplifier OTA2 includes: the 13rd PMOS tube MP13, the 14th PMOS tube MP14, the tenth
Five PMOS tube MP15, the 16th PMOS tube MP16, the 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th NMOS tube MN15、
16th NMOS tube MN16, electric current sink ISSAnd third capacitor CC1；Wherein,
13rd PMOS tube MP13With the 13rd NMOS tube MN13It is sequentially connected in series between power end VDD and ground terminal GND；
14th PMOS tube MP14With the 16th NMOS tube MN16It is sequentially connected in series between power end VDD and ground terminal GND；
Electric current sinks ISS, the 15th PMOS tube MP15And the 14th NMOS tube MN14It is sequentially connected in series in power end VDD and ground terminal
Between GND；
16th PMOS tube MP16With the 15th NMOS tube MN15It is sequentially connected in series and sinks I in electric currentSSBetween ground terminal GND；
Third capacitor CC1It is electrically connected to the 14th PMOS tube MP14With the 16th NMOS tube MN16It concatenates the node formed and connects
Between ground terminal GND；
13rd PMOS tube MP13Grid with drain electrode be connected and be electrically connected the 14th PMOS tube MP14Grid；
14th NMOS tube MN14Grid with drain electrode be connected and be electrically connected the 13rd NMOS tube MN13Grid；
15th NMOS tube MN15Grid with drain electrode be connected and be electrically connected the 16th NMOS tube MN16Grid；
16th PMOS tube MP16Grid as the second operational transconductance amplifier OTA2 non-inverting input terminal be electrically connected the tenth
One NMOS tube MN11Source electrode；
15th PMOS tube MP15Grid as the second operational transconductance amplifier OTA2 inverting input terminal be electrically connected the tenth
Two NMOS tube MN12Source electrode；
14th PMOS tube MP14With the 16th NMOS tube MN16The node formed is concatenated as the second operational transconductance amplifier
The output end of OTA2 is electrically connected the 12nd NMOS tube MN12Grid.
Further, Fig. 6 is referred to, Fig. 6 is a kind of knot of non-overlapping clock generating unit provided in an embodiment of the present invention
Structure schematic diagram；The non-overlapping clock generating unit includes: the first phase inverter INV1, the second phase inverter INV2, third phase inverter
INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the 7th phase inverter INV7, the first NAND gate
NAND1And the second NAND gate NAND2；Wherein,
First NAND gate NAND1, the second phase inverter INV2, third phase inverter INV3And the 4th phase inverter INV4It is successively serial
Electrical connection；
First phase inverter INV1, the second NAND gate NAND2, the 5th phase inverter INV5, hex inverter INV6And the 7th reverse phase
Device INV7Successively serial electrical connection；
Second NAND gate NAND2The second input terminal be electrically connected to third phase inverter INV3With the 4th phase inverter INV4Concatenation
At the node of formation；
First NAND gate NAND1The second input terminal be electrically connected to hex inverter INV6With the 7th phase inverter INV7Concatenation
At the node of formation；
First phase inverter INV1Input terminal and the first NAND gate NAND1First input end be connected and as it is non-overlapping when
The input terminal that clock generates unit is electrically connected the output end of the first d type flip flop D1；
4th phase inverter INV4Output end and the 7th phase inverter INV7Output end generated respectively as non-overlapping clock it is single
The first output end and second output terminal of member export two-phase disjoint signals Φ 1 and Φ 2 respectively.
The wide loading range adjusting and voltage-reduction switch capacitor DC-DC converter of double mode provided in this embodiment, using PFM and
The operating mode of two kinds of output voltage management of Burst, under PFM operating mode, the variation of load is defeated by error amplifier EA
Signal Regulation VCO switching frequency out generates two-phase disjoint signals Φ 1 and Φ 2 as switched capacitor array to stablize output electricity
Pressure guarantees output voltage precision；Stablize the output electricity of underloading by a kind of operating mode of interval in Burst operating mode
Pressure, to effectively increase the load current range of converter at light load, and compared with PFM at light load, greatly promotes load
The reaction time of jump and transfer efficiency.
Embodiment two
In the present solution, clock coding drive sub-circuits 11 are used for power tube driving, switching capacity power sub-circuit 12
For carrying out charge conversion.Clock encodes drive sub-circuits 11 and switching capacity power sub-circuit 12 is not innovation of the invention
Point, is no longer described in detail here, below emphasis the working principle and implementation of feedback control sub-circuit are retouched
It states.
Specifically, referring again to Fig. 3, first switch S1It is controlled it by first control signal RST, second opens
Close S2Pass through second control signalIt controls it.
Wherein, as first control signal RST=1, the first reference voltage VREF1Access, third PMOS tube MP3With the 4th
PMOS tube MP4Conducting, the 5th PMOS tube MP5With the 6th PMOS tube MP6Shutdown, the first operational transconductance amplifier OTA1 are put as error
Big device uses, at this point, the DC-DC converter works under PFM mode；Specifically, referring to Fig. 7, Fig. 7 is the embodiment of the present invention
A kind of structural schematic diagram of control circuit of the DC-DC converter provided under PFM operating mode, wherein error amplifier EA
By the first PMOS tube M in Fig. 3P1, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 7th PMOS tube MP7、
8th PMOS tube MP8, the first NMOS tube MN1, the second NMOS tube MN2, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 9th NMOS tube
MN9, the tenth NMOS tube MN10, electric current sink ISS, first switch S1And second switch S2It constitutes.
As first control signal RST=0, the second reference voltage VREF2Access, third PMOS tube MP3With the 4th PMOS tube
MP4Shutdown, the 5th PMOS tube MP5With the 6th PMOS tube MP6Conducting, the first operational transconductance amplifier OTA1 are used as comparator,
At this point, the DC-DC converter works under Burst mode；Specifically, referring to Fig. 8, Fig. 8 is provided in an embodiment of the present invention
A kind of structural schematic diagram of the control circuit of DC-DC converter under Burst operating mode；The control circuit includes: the second ratio
Compared with device VCMP, the second current source IREF, third current source IOUT, the 17th PMOS tube MP17, the 17th PMOS tube MP17, the 17th
NMOS tube MN17, the 18th NMOS tube MN18, the 19th NMOS tube MN19, the 8th phase inverter INV8, the 9th phase inverter INV9, first or
Door OR1, second or door OR2, rest-set flip-flop, the second d type flip flop D2And third d type flip flop D3；Wherein,
Second current source IREFWith the 17th NMOS tube MN17It is sequentially connected in series between power end VDD and ground terminal GND；
Third current source IOUTWith the 18th NMOS tube MN18It is sequentially connected in series between power end VDD and ground terminal GND；
17th PMOS tube MP17With the 19th NMOS tube MN19It is sequentially connected in series between power end VDD and ground terminal GND；
17th NMOS tube MN17Grid, the 18th NMOS tube MN18Grid and the 19th NMOS tube MN19Grid phase
Even and it is electrically connected the 17th NMOS tube MN17Drain electrode；
17th PMOS tube MP17Grid be electrically connected the 18th NMOS tube MN18Drain electrode；
Wherein, the second current source IREF, the 17th NMOS tube MN17, third current source IOUT, the 18th NMOS tube MN18, the tenth
Seven PMOS tube MP17And the 19th NMOS tube MN19Form switching frequency detection circuit, the 17th NMOS tube MN17With the 19th NMOS
Pipe MN19Concatenate output end of the node formed as switching frequency detection circuit；
The non-inverting input terminal of second comparator VCMP and the second reference voltage end VREF2Connection, the second comparator VCMP's is anti-
Phase input terminal is connect with the output end of switching capacity power sub-circuit 12, the output end and the 8th phase inverter of the second comparator VCMP
INV8Input terminal connection；First or door OR1First input end and the 8th phase inverter INV8Output end connection, first or door
OR1The second input terminal and rest-set flip-flop Q output connect, first or door OR1Output end and rest-set flip-flop S input terminal
Connection；With regard to phase inverter INV9Input terminal connect with the output end of switching frequency detection circuit；Second or door OR2It is first defeated
Enter end and the 9th phase inverter INV9Output end connection, second or door OR2The second input terminal and third d type flip flop D3Q output
End connection, second or door OR2Output end and rest-set flip-flop R input connect；The clock signal input of second d type flip flop D2
End is connect with clock signal terminal Clock, the second d type flip flop D2D input terminal and the second d type flip flop D2'sOutput end connection, the
2-D trigger D2Q output and third d type flip flop D3Clock signal input terminal connection；Third d type flip flop D3D input terminal
It is connect with the Q output of rest-set flip-flop；Wherein, the Q output of rest-set flip-flop exports first control signal RST, third d type flip flop
D3Q output output third control signal RSTDelay.
Third current source I in switching frequency detection circuitOUTIt is current generating circuit in voltage controlled oscillator VCO described in Fig. 4
Output electric current, the second comparator VCMP is the first operational transconductance amplifier OTA1 shown in Fig. 3 in first control signal RST=
Working condition when 0.When load current reduces, error amplifier EA controls the output current reduction of voltage controlled oscillator VCO, when
Third current source IOUTOutput electric current less than the second current source IREFOutput electric current, current comparator output is 1, third at this time
Control signal RSTDelay signal shielding the second comparator VCMP output signal, rest-set flip-flop output signal first control signal
RST=0, circuit are reduced by PFM pattern switching to Burst operating mode, voltage controlled oscillator VCO shutdown, output voltage, the second ratio
0 is continued as compared with device VCMP and is started to work；As the output voltage V of switching capacity power sub-circuit 12OUTLess than the 2nd VREF2When,
Second comparator VCMP output is 1, at this time the output signal of first control signal RST signal bucking current comparator, the first control
Signal RST=0 processed, voltage controlled oscillator VCO are opened, and loop is established, and output voltage rises.Here the first reference voltage VREF1=
1.2V, the second reference voltage VREF2=1.15V.
Third control signal RSTDelay signal is the postpones signal of first control signal RST.When switching capacity power
The output voltage V of circuit 12OUTLower than the second reference voltage VREF2When, voltage controlled oscillator VCO is opened, the control loop of PFM mode
It begins setting up, but switching frequency is still lower at this time, current comparator output signal is 1, first control signal RST=0, circuit
Burst mode is kept, output voltage continues to reduce.In order to avoid the appearance of this working condition, third is added and controls signal
RSTDelay signal, after loop establishes a period of time, the work of switching frequency detection circuit.Specifically, referring to Fig. 9, Fig. 9 is
A kind of input-output wave shape figure of the DC-DC converter provided in an embodiment of the present invention under Burst operating mode.
0, Figure 10 is a kind of emulation wave of the DC-DC converter provided in an embodiment of the present invention under PFM mode referring to Figure 1
Shape figure；Wherein, input voltage 2.55V, it can be seen that load current changes to 1.8mA by 600uA, and switching frequency is become by 5.3MHz
Change to 16MHz, output voltage stabilization is in 1.2V.Output voltage ripple 15mV hardly happens variation with load current.When negative
When carrying curent change, the stabilization time of output voltage is determined by the bandwidth of loop, by voltage-controlled when the bias current of error amplifier
The current generating circuit of oscillator VCO provides, and with the increase of load current, voltage controlled oscillator VCO exports electric current and increases, circuit
The stabilization time it is smaller.But under PFM operating mode, in the input voltage range of 2.0V---3.6V, load current range
Only 1.8mA-2mA.
1, Figure 11 is a kind of emulation of the DC-DC converter provided in an embodiment of the present invention under Burst mode referring to Figure 1
Waveform diagram；Wherein, input voltage 3.2V, output voltage stabilization is in 1.2V, but output voltage ripple is larger, reaches 100mV or more.
As can be seen from the figure output electric current changes to 1.6mA by 400uA, and voltage controlled oscillator VCO output frequency is basically stable at 2MHz
Without changing with load current, as load current increases, voltage controlled oscillator VCO is opened and the frequency of shutdown is gradually increasing.
Burst operating mode is exactly based on intermittent working method to solve the requirement of circuit underloading.Simulation result shows load electricity
Stream remains to work normally in 1uA.
2, Figure 12 is a kind of DC-DC converter provided in an embodiment of the present invention in PFM mode and Burst mould referring to Figure 1
The simulation waveform that formula mutually switches；Wherein, when input voltage is 2.7V, load current 1mA, voltage controlled oscillator VCO output frequency
Rate is about 3.3MHz.When load current is switched to 800uA, the output frequency of voltage controlled oscillator VCO is lower than 2MHz, reset signal
RST=0 turns off voltage controlled oscillator VCO, and circuit enters Burst mode.When load current is switched to heavily loaded 2mA, the first control
Signal RST=1 opening pressure control oscillator VCO, loop are established, and after time T=1/fS, switching frequency detection circuit starts work
Make, feedback control sub-circuit enters PFM mode, and PFM mode and Burst mode, which cooperate, effectively expands load current model
It encloses.The switching capacity DC-DC converter of double mode works in 0~2mA, the load current compared with single PFM scheme control
Range increases 9 times.
Please participate in Figure 13, Figure 13 be a kind of DC-DC converter provided in an embodiment of the present invention PFM mode at light load with
The performance comparison schematic diagram of Burst mode；Wherein, when load current jumps to 100 μ A by 10 μ A, it is limited to lesser gain
Bandwidth product, the output voltage under PFM mode are reduced to 722mV, and the reaction time reaches 113 μ s, it is difficult to make as stable power supply
With；And the output voltage under Burst mode keeps stablizing, the switching frequency of interval is increase accordingly, and Burst mode solves underloading
The problem of lower output voltage stabilization.
Referring to Figure 14, Figure 14 be a kind of DC-DC converter provided in an embodiment of the present invention PFM mode at light load with
The transfer efficiency contrast schematic diagram of Burst mode；Wherein, under Burst mode control circuit power consumption reduction, effectively raise
Power conversion efficiency, in 60 μ A, transfer efficiency maximum can promote 14%.
To sum up, specific case used herein is expounded structure and embodiment of the invention, the above implementation
The explanation of example is merely used to help understand method and its core concept of the invention；Meanwhile for the general technology people of this field
Member, according to the thought of the present invention, there will be changes in the specific implementation manner and application range, to sum up, in this specification
Appearance should not be construed as limiting the invention, and protection scope of the present invention should be subject to the attached claims.
Claims (4)
1. a kind of wide loading range adjusting and voltage-reduction switch capacitor DC-DC converter (10) of double mode characterized by comprising
Clock encodes drive sub-circuits (11)；
Switching capacity power sub-circuit (12) is electrically connected clock coding drive sub-circuits (11)；
Feedback control sub-circuit (13) is electrically connected the Capacitance Power sub-circuit (12) and exports feedback signal to the clock and compiles
Code drive sub-circuits (11)；Wherein,
The feedback control sub-circuit (13) includes: the first operational transconductance amplifier (OTA1), compensating electric capacity (CC), compensation resistance
(RC), voltage controlled oscillator (VCO), non-overlapping clock generating unit；Wherein,
First operational transconductance amplifier (OTA1), the voltage controlled oscillator (VCO) and the non-overlapping clock generating unit
It is sequentially connected in series in the output end (V of the switching capacity power sub-circuit (12)OUT) and clock coding drive sub-circuits (11)
Input terminal between；
The inverting input terminal of first operational transconductance amplifier (OTA1) is electrically connected the switching capacity power sub-circuit (12)
Output end (VOUT), non-inverting input terminal is electrically connected the first reference voltage end (VREF)；
Compensation resistance (the RC) and the compensating electric capacity (CC) be sequentially connected in series in first operational transconductance amplifier (OTA1)
Between output end and ground terminal (GND)；
First operational transconductance amplifier (OTA1) includes: the first PMOS tube (MP1), the second PMOS tube (MP2), third PMOS tube
(MP3), the 4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube
(MP8), the 9th PMOS tube (MP9), the tenth PMOS tube (MP10), the first NMOS tube (MN1), the second NMOS tube (MN2), third NMOS tube
(MN3), the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th NMOS tube
(MN8), the 9th NMOS tube (MN9), the tenth NMOS tube (MN10), electric current sink (ISS), first switch (S1) and second switch (S2)；Its
In,
Second PMOS tube (the MP2), the 4th PMOS tube (MP4), the 8th PMOS tube (MP8), the 6th NMOS tube
(MN6) and the second NMOS tube (MN2) be sequentially connected in series between power end (VDD) and ground terminal (GND)；
First PMOS tube (the MP1), the third PMOS tube (MP3), the 7th PMOS tube (MP7), the 5th NMOS tube
(MN5) and the first NMOS tube (MN1) be sequentially connected in series between the power end (VDD) and the ground terminal (GND)；
6th PMOS tube (the MP6), the tenth PMOS tube (MP10), the 8th NMOS tube (MN8) and the 4th NMOS tube
(MN4) be sequentially connected in series in the second PMOS tube (MP2) drain electrode and the ground terminal (GND) between；
5th PMOS tube (the MP5), the 9th PMOS tube (MP9), the 7th NMOS tube (MN7) and the third NMOS tube
(MN3) be sequentially connected in series in the first PMOS tube (MP1) drain electrode and the ground terminal (GND) between；
9th NMOS tube (the MN9) and the heavy (I of the electric currentSS) be sequentially connected in series in the second PMOS tube (MP2) drain electrode and institute
It states between ground terminal (GND)；
Tenth NMOS tube (the MN10) it is electrically connected to the first PMOS tube (MP1) drain electrode and the 9th NMOS tube (MN9)
Between source electrode；
First PMOS tube (the MP1) grid be electrically connected the second PMOS tube (MP2) grid；
Third PMOS tube (the MP3) grid be electrically connected the 4th PMOS tube (MP4) grid；
7th PMOS tube (the MP7) grid be electrically connected the 8th PMOS tube (MP8) grid；
5th NMOS tube (the MN5) grid be electrically connected the 6th NMOS tube (MN6) grid；
First NMOS tube (the MN1) grid and the second NMOS tube (MN2) grid be electrically connected the 7th PMOS tube
(MP7) drain electrode；
5th PMOS tube (the MP5) grid be electrically connected the 6th PMOS tube (MP6) grid；
9th PMOS tube (the MP9) grid be electrically connected the tenth PMOS tube (MP10) grid；
7th NMOS tube (the MN7) grid be electrically connected the 8th NMOS tube (MN8) grid；
Third NMOS tube (the MN3) grid and the 4th NMOS tube (MN4) grid be electrically connected the 9th PMOS tube
(MP9) drain electrode；
9th NMOS tube (the MN9) grid be electrically connected as the non-inverting input terminal of first operational transconductance amplifier (OTA1)
Connect the output end of the switching capacity power sub-circuit (12)；
Tenth PMOS tube (the MP10) grid as first operational transconductance amplifier (OTA1) inverting input terminal distinguish
Through the first switch (S1) and the second switch (S2) the first reference voltage end (V of electrical connectionREF1) and the second reference voltage end
(VREF2)；
8th PMOS tube (the MP8) and the 6th NMOS tube (MN6) node formed is concatenated as first operational transconductance
First output end of amplifier (OTA1)；
Tenth PMOS tube (the MP10) and the 8th NMOS tube (MN8) node formed is concatenated as first operational transconductance
The second output terminal of amplifier (OTA1).
2. DC-DC converter (10) according to claim 1, which is characterized in that the voltage controlled oscillator (VCO) includes:
11st NMOS tube (MN11), the 12nd NMOS tube (MN12), the 11st PMOS tube (MP11), the 12nd PMOS tube (MP12), first
Current source (IBIAS), the second operational transconductance amplifier (OTA2), resistance (RS), third switch (S3), the 4th switch (S4), the 5th
Switch (S5), the 6th switch (S6), first capacitor (C1), the second capacitor (C2), first comparator (CMP) and the first d type flip flop
(D1)；Wherein,
The 11st NMOS tube (MN11) and the first current source (IBIAS) be sequentially connected in series in the power end (VDD) with it is described
Between ground terminal (GND)；
The 12nd PMOS tube (MP12), the 12nd NMOS tube (MN12) and the resistance (RS) be sequentially connected in series in the electricity
Between source (VDD) and the ground terminal (GND)；
The non-inverting input terminal of second operational transconductance amplifier (OTA2) is electrically connected the 11st NMOS tube (MN11) source
Pole, inverting input terminal are electrically connected the 12nd NMOS tube (MN12) source electrode, output end is electrically connected the 12nd NMOS tube
(MN12) grid；
5th switch (the S5) and the first capacitor (C1) it is in parallel after with the third switch (S3) and the 11st PMOS
Manage (MP11) be sequentially connected in series between the ground terminal (GND) and the power end (VDD)；
6th switch (the S6) and the second capacitor (C2) it is in parallel after with the 4th switch (S4) be sequentially connected in series and connect in described
Ground terminal (GND) and the 11st PMOS tube (MP11) drain electrode between；
The non-inverting input terminal of the first comparator (CMP) is electrically connected third reference voltage end (VREF3), inverting input terminal electrical connection
The 11st PMOS tube (MP11) drain electrode；
The input end of clock (Clk) of first d type flip flop (D1) is electrically connected the output end of the first comparator (CMP), institute
The D input terminal for stating the first d type flip flop (D1) is connected with Q output；
The 11st NMOS tube (MN11) grid as the voltage controlled oscillator (VCO) input terminal be electrically connected described first
The output end of operational transconductance amplifier (OTA1)；
The Q output of first d type flip flop (D1) is electrically connected the clock coding as the output end of voltage controlled oscillator (VCO)
Drive sub-circuits (11).
3. DC-DC converter (10) according to claim 2, which is characterized in that second operational transconductance amplifier
It (OTA2) include: the 13rd PMOS tube (MP13), the 14th PMOS tube (MP14), the 15th PMOS tube (MP15), the 16th PMOS tube
(MP16), the 13rd NMOS tube (MN13), the 14th NMOS tube (MN14), the 15th NMOS tube (MN15), the 16th NMOS tube
(MN16), electric current sink (ISS) and third capacitor (CC1)；Wherein,
The 13rd PMOS tube (MP13) and the 13rd NMOS tube (MN13) be sequentially connected in series in the power end (VDD) and institute
It states between ground terminal (GND)；
The 14th PMOS tube (MP14) and the 16th NMOS tube (MN16) be sequentially connected in series in the power end (VDD) and institute
It states between ground terminal (GND)；
The electric current sinks (ISS), the 15th PMOS tube (MP15) and the 14th NMOS tube (MN14) be sequentially connected in series in described
Between power end (VDD) and the ground terminal (GND)；
The 16th PMOS tube (MP16) and the 15th NMOS tube (MN15) be sequentially connected in series in the heavy (I of the electric currentSS) and institute
It states between ground terminal (GND)；
Third capacitor (the CC1) it is electrically connected to the 14th PMOS tube (MP14) and the 16th NMOS tube (MN16) concatenation
Between the node of formation and the ground terminal (GND)；
The 13rd PMOS tube (MP13) grid with drain electrode be connected and be electrically connected the 14th PMOS tube (MP14) grid；
The 14th NMOS tube (MN14) grid with drain electrode be connected and be electrically connected the 13rd NMOS tube (MN13) grid；
The 15th NMOS tube (MN15) grid with drain electrode be connected and be electrically connected the 16th NMOS tube (MN16) grid；
The 16th PMOS tube (MP16) grid as second operational transconductance amplifier (OTA2) non-inverting input terminal electricity
Connect the 11st NMOS tube (MN11) source electrode；
The 15th PMOS tube (MP15) grid as second operational transconductance amplifier (OTA2) inverting input terminal electricity
Connect the 12nd NMOS tube (MN12) source electrode；
The 14th PMOS tube (MP14) and the 16th NMOS tube (MN16) concatenation formed node as described second across
The output end for leading operational amplifier (OTA2) is electrically connected the 12nd NMOS tube (MN12) grid.
4. DC-DC converter (10) according to claim 3, which is characterized in that the non-overlapping clock generating unit packet
It includes: the first phase inverter (INV1), the second phase inverter (INV2), third phase inverter (INV3), the 4th phase inverter (INV4), it is the 5th anti-
Phase device (INV5), hex inverter (INV6), the 7th phase inverter (INV7), the first NAND gate (NAND1) and the second NAND gate
(NAND2)；Wherein,
First NAND gate (the NAND1), the second phase inverter (INV2), the third phase inverter (INV3) and the described 4th
Phase inverter (INV4) successively serial electrical connection；
First phase inverter (the INV1), the second NAND gate (NAND2), the 5th phase inverter (INV5), it is the described 6th anti-
Phase device (INV6) and the 7th phase inverter (INV7) successively serial electrical connection；
Second NAND gate (the NAND2) the second input terminal be electrically connected to the third phase inverter (INV3) with it is the described 4th anti-
Phase device (INV4) concatenate at the node formed；
First NAND gate (the NAND1) the second input terminal be electrically connected to the hex inverter (INV6) and the 7th phase inverter
(INV7) concatenate at the node formed；
First phase inverter (the INV1) input terminal and the first NAND gate (NAND1) first input end be connected and conduct
The input terminal of the non-overlapping clock generating unit is electrically connected the output end of first d type flip flop (D1)；
4th phase inverter (the INV4) output end and the 7th phase inverter (INV7) output end respectively as the non-friendship
The first output end and second output terminal of folded clock generating unit.
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| CN112152482A (en) * | 2020-10-26 | 2020-12-29 | 哈尔滨理工大学 | High-voltage-reduction transformation ratio rectifier based on switched capacitor |
| CN113938004B (en) * | 2021-08-31 | 2024-04-05 | 西安电子科技大学 | Voltage doubling inverter, power supply voltage conversion circuit and electronic product |
| CN114900036A (en) * | 2022-05-24 | 2022-08-12 | 哈尔滨工业大学 | Switched capacitor voltage-stabilizing chip circuit with double control modes |
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