CN110804727A - 应变薄膜异质结、制备方法及应用 - Google Patents
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Abstract
本发明公开了一种应变薄膜异质结、制备方法及应用,属于半导体薄膜制备技术领域,制备方法包括在多靶共溅磁控溅射真空室中分别装入高纯硅靶、高纯锗靶、镉靶、高纯硼靶及高纯本征单晶锗;将高纯本征单晶锗加热至250℃;预溅射硅靶、锗靶以及硼靶各20min;溅射镉靶并沉积镉过渡层,共溅射沉积Si0.25Ge0.75层;保持250℃温度一小时后,待冷却到室温,得到沉积态的Si0.25Ge0.75/Ge薄膜异质结然后退火,整个过程在惰性气体中进行;该方法能够快速制备出Si0.25Ge0.75/Ge应变薄膜异质结,Si0.25Ge0.75/Ge应变薄膜异质结具有均匀的全局应变。
Description
技术领域
本发明属于半导体薄膜制备技术领域,具体涉及一种Si0.25Ge0.75/Ge应变薄膜异质结、制备方法及应用。
背景技术
四族半导体材料在微电子和太阳能电池领域具有广泛的应用。通过磁性离子的掺杂,在信息处理和存储方面具有极大的前景,具有均匀掺杂的磁性粒子的四族半导体薄膜是自旋器件理想的候选材料之一。随着科技的发展,未来高性能微电子器件应同时满足高速、低功耗和室温铁磁性等多功能要求。而现有硅基半导体材料的电学性能较差,尤其是低的空穴迁移率,不但会因晶体管尺寸即将达到极限而阻碍集成电路性能的进一步改善,而且会影响四族半导体材料在其他功能领域的潜在应用,如低的空穴迁移率对自旋极化电流不利,这是由于自旋与空穴迁移率具有显著的关联作用;因此,四族半导体材料的空穴迁移率的提高将对未来微电子技术和应用产生重大影响。而目前大多数提高空穴迁移率的方法是通过降低缺陷和掺杂物的散射,显然,这对器件是不利的,因为器件的功能以及电流的欧姆接触都需要足够高的载流子浓度。由于空穴的浓度与迁移率之间存在着相互制约的关系,要想在高空穴浓度水平下,开发一种新的策略来大幅度提高空穴的迁移率将具有很大的挑战。
基于能带结构调控的应变工程提供了一种在不降低空穴浓度的情况下提升迁移率的可选择途径。在四族半导体中,通过调谐的晶格失配工程,如单轴应变Si薄膜(S.W.Bedell,A.Khakifirooz,D.K.Sadana,Strain scaling for CMOS,MRS Bull.39(2014)131~137.)和双轴应变SiGe纳米线(F.Wen,E.Tutuc,Enhanced Electron Mobilityin Nonplanar Tensile Strained Si Epitaxially Grown on SixGe1~x Nanowires,NanoLett.18(2018)94~100.),可以施加适当的应变来提高空穴的迁移率。然而,这种方式生长的薄膜异质结的临界厚度只有30nm左右,当薄膜异质结厚度超过临界厚度时,由于过大的晶格失配,总是会引入较高的位错密度(M.L.Lee,E.A.Fitzgerald,M.T.Bulsara,M.T.Currie,A.Lochtefeld,Strained Si,SiGe,and Ge Channels for High~mobilityMetal~oxide~semiconductor Field~effect Transistors,J.Appl.Phys.97(2005)011101.)。而这些位错堆集形成的微结构缺陷进一步会导致局部应力应变集中,甚至在材料加工过程中引起微裂纹或凸起(G.Abadias,E.Chason,J.Keckes,M.Sebastiani,G.B.Thompson,E.Barthel,G.L.Doll,C.E.Murray,C.H.Stoesseli,L.Martinu,Stress inThin Films and Coatings Current Status,Challenges,and Prospects,J.Vac.Sci.Technol.A 36(2018)020801.);更严重的是,通过晶格失配法获得的应力和应变会沿着薄膜异质结的深度迅速衰减(S.W.Bedell,A.Khakifirooz,D.K.Sadana,Strainscaling for CMOS,MRS Bull.39(2014)131~137.),随着薄膜异质结厚度的增加,应变越来越小,因此限制了空穴迁移率进一步的提高。
发明内容
为了解决现有技术存在的上述问题,本发明提供了一种应变薄膜异质结的制备方法。
本发明所采用的技术方案为:一种应变薄膜异质结的制备方法,包括以下步骤:
步骤S1:在多靶共溅磁控溅射真空室中分别装入高纯硅靶、高纯锗靶、高纯硼靶以及高纯本征单晶锗,关闭仓门并抽真空至10-5pa;
高纯硅靶是指硅的质量分数大于99.9999%的硅靶,高纯锗靶是指锗的质量分数大于99.9999%的锗靶,高纯硼靶是指烹的质量分数大于99.99%的硼靶,高纯本征单晶锗是锗含量大于99.9999%的本征单晶锗;
步骤S2:将高纯本征单晶锗加热至250℃,并保持一小时;
步骤S3:预溅射硅靶、锗靶以及硼靶各20min,溅射功率为50W,溅射时通入惰性气体,惰性气体的气压为0.5~1Pa;
步骤S4:结束预溅射,开始溅射鍺靶并沉积鍺过渡层,溅射功率为30W,溅射时间为2min,溅射时通入惰性气体,惰性气体的气压为0.3Pa;
步骤S5:共溅射沉积硼原子百分比含量为3%的Si0.25Ge0.75层,溅射功率为硅靶30W、锗靶30W、硼靶70W,溅射时间为20min,溅射时通入惰性气体,惰性气体的气压为0.3Pa;
步骤S6:结束溅射,锗衬底继续保持250℃温度一小时后,结束锗衬底加热,待多靶共溅磁控溅射真空室冷却到室温,得到沉积态的Si0.25Ge0.75/Ge薄膜异质结;
步骤S7:将得到的所述薄膜异质结进行退火,得到Si0.25Ge0.75/Ge应变薄膜异质结。
进一步限定,步骤S4中的所述镉过渡层的厚度为10~20nm。
进一步限定,在步骤S5中所述Si0.25Ge0.75层的厚度为200nm,所述Si0.25Ge0.75层呈非晶相。
进一步限定,步骤S7中退火的具体方法为:所述Si0.25Ge0.75/Ge应变薄膜异质结在30s内迅速升温至650~800℃,并恒温保持1min,随后自然冷却至室温。
与现有技术相比,本发明提供的一种Si0.25Ge0.75/Ge应变薄膜异质结的制备方法,具有如下技术效果或优点:
本发明采用物理气相沉积联合快速热处理方法,能够快速制备出Si0.25Ge0.75/Ge应变薄膜异质结,Si0.25Ge0.75/Ge应变薄膜异质结具有均匀的全局应变,操作工艺简单、产量高以及成本低。通过该方法制备得到的Si0.25Ge0.75/Ge应变薄膜异质结具有超高的空穴迁移率和载流子浓度;在650~800℃范围,随着退火温度的升高压应变逐渐增加,Si0.25Ge0.75/Ge应变薄膜异质结的空穴迁移率和浓度逐渐增加,当退火温度升高至800℃时空穴的迁移率和浓度分别达到1911cm2V~1s~1和1.2×1018cm~3,而800~900℃范围,压应变逐渐降低,Si0.25Ge0.75/Ge应变薄膜异质结的空穴迁移率也逐渐降低。
本发明还提供了一种应变薄膜异质结的制备方法制备得到的Si0.25Ge0.75/Ge应变薄膜异质结。
本发明还提供了应变薄膜异质结在四族半导体材料中的应用,解决了在四族半导体材料中现有的薄膜异质结的厚度和高空穴的迁移率之间的矛盾关系。
附图说明
图1是实施例1所得沉积态的Si0.25Ge0.75/Ge薄膜异质结的示意图描述和微结构表征图;
图2是实施例1所得Si0.25Ge0.75应变薄膜异质结在不同退火温度下微结构演变图;
图3是实施例1所得Si0.25Ge0.75应变薄膜异质结在不同退火温度下的压应变演变图;
图4是实施例1所得Si0.25Ge0.75应变薄膜异质结在不同退火温度下的空穴迁移率和浓度变化曲线。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本技术领域技术人员可以理解,除非另外定义,这里使用的所有术语(包括技术术语和科学术语),具有与本发明所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是,诸如通用字典中定义的那些术语,应该被理解为具有与现有技术的上下文中的意义一致的意义,并且除非被特定定义,否则不会用理想化或过于正式的含义来解释。
实施例1
一种Si0.25Ge0.75/Ge应变薄膜异质结的制备方法,包括以下步骤:
S1:在多靶共溅磁控溅射真空室中分别装入高纯硅、锗靶、硼靶以及装入经过丙酮、酒精超声清洗,氢氟酸、去离子水漂洗过的高纯本征单晶锗,高纯本征单晶锗作为衬底,关闭仓门,并抽真空至10-5pa;
S2:将衬底加热至250℃,并保持一小时;
S3:预溅射硅靶、锗靶以及硼靶20min,溅射功率为50W,溅射时通入氩气,氩气气压为1Pa;
S4:结束预溅射,开始溅射沉积镉过渡层,溅射功率为30W,溅射时间为2min,溅射时通入氩气,氩气气压为0.3Pa;
S5:共溅射沉积硼原子百分比含量为3%的Si0.25Ge0.75层,溅射功率为硅靶30W、锗靶30W、硼靶70W,溅射时间为20min,溅射时通入氩气,氩气气压为0.3Pa;
S6:结束溅射,衬底继续保持250℃温度一小时后,结束衬底加热,待多靶共溅磁控溅射真空室冷却至室温,得到沉积态的Si0.25Ge0.75/Ge薄膜异质结;
S7:将得到的沉积态的Si0.25Ge0.75/Ge薄膜异质结装入快速真空退火炉,Si0.25Ge0.75/Ge薄膜异质结在30s内迅速升温至650~800℃,并恒温保持1min,随后自然冷却至室温,得到Si0.25Ge0.75/Ge应变薄膜异质结。
图1~3为对实施例1中所得的Si0.25Ge0.75/Ge应变薄膜异质结进行表征所得的图片。其中:
图1中(a)图为Si0.25Ge0.75/Ge应变薄膜异质结示意图;(b)图为沉积态的Si0.25Ge0.75/Ge薄膜异质结的横截面透射电镜图像,插图为Si0.25Ge0.75层的傅立叶变换图;(e)图为透射电镜扫描模式下高角环形暗场像和元素面分布图,由该图可以看出,Si0.25Ge0.75层和镉过渡层的分层;(c)图为沉积态的Si0.25Ge0.75/Ge薄膜异质结的界面高分辨透射电镜图;(d)图为沉积态的Si0.25Ge0.75/Ge薄膜异质结的掠入射X射线衍射图,由该图可以看出镉过渡层呈纳米晶,而Si0.25Ge0.75呈非晶态。
图2中(a)图为沉积态的Si0.25Ge0.75/Ge薄膜异质结在不同退火温度后的掠入射X射线衍射图;(b)图、(c)图以及(d)图为650℃、800℃、900℃退火后Si0.25Ge0.75/Ge截面的选择区域电子衍射图;(e)图、(f)图以及(g)为650℃、800℃、900℃退火后Si0.25Ge0.75/Ge截面的高分辨透射电镜图,表明经过快速退火处理后形成了纳米晶的Si0.25Ge0.75/Ge薄膜异质结,且随着退火温度升高,Si0.25Ge0.75晶粒尺寸逐渐增大,然而当温度高于800℃时,Si0.25Ge0.75发生了相分离。
图3中(a)图为沉积态的Si0.25Ge0.75/Ge薄膜异质结在不同退火温度后的拉曼光谱图,表明随着退火温度的增加Si0.25Ge0.75层受到的压应变逐渐增大,在800℃达到最大,当温度继续增加,压应变又开始降低,这是由于Si0.25Ge0.75发生了相分离;(b)图为800℃退火后Si0.25Ge0.75层的高分辨透射电镜图,由该图可知(111)晶面间距变小,(111)指面心立方结构Si0.25Ge0.75的一个晶面,图中的1,2代表晶面指数,证实了Si0.25Ge0.75层产生的压应变。
图4为Si0.25Ge0.75/Ge应变薄膜异质结的空穴迁移率(实心三角形)和浓度(空心正方形)在不同退火温度后的变化;由图4可以看出在650~800℃,随着退火温度的增加,压应变逐渐增加,Si0.25Ge0.75/Ge应变薄膜异质结的空穴迁移率和浓度均显著增加,此时空穴的迁移率和浓度分别达到1911cm2V-1s-1和1.2×1018cm-3,而超过800℃后,压应变开始降低,Si0.25Ge0.75/Ge应变薄膜异质结的空穴迁移率开始下降。
本发明不局限于上述可选实施方式,任何人在本发明的启示下都可得出其他各种形式的产品,但不论在其形状或结构上作任何变化,凡是落入本发明权利要求界定范围内的技术方案,均落在本发明的保护范围之内。
Claims (6)
1.一种应变薄膜异质结的制备方法,其特征在于,包括以下步骤:
步骤S1:在多靶共溅磁控溅射真空室中分别装入高纯硅靶、高纯锗靶、高纯硼靶以及高纯本征单晶锗,关闭仓门并抽真空至10-5pa;
步骤S2:将高纯本征单晶锗加热至250℃,并保持一小时;
步骤S3:预溅射硅靶、锗靶以及硼靶各20min,溅射功率为50W,溅射时通入惰性气体,惰性气体的气压为0.5~1Pa;
步骤S4:结束预溅射,开始溅射鍺靶并沉积鍺过渡层,溅射功率为30W,溅射时间为2min,溅射时通入惰性气体,惰性气体的气压为0.3Pa;
步骤S5:共溅射沉积硼原子百分比含量为3%的Si0.25Ge0.75层,溅射功率为硅靶30W、锗靶30W、硼靶70W,溅射时间为20min,溅射时通入惰性气体,惰性气体的气压为0.3Pa;
步骤S6:结束溅射,锗衬底继续保持250℃温度一小时后,结束锗衬底加热,待多靶共溅磁控溅射真空室冷却到室温,得到沉积态的Si0.25Ge0.75/Ge薄膜异质结;
步骤S7:将得到的所述薄膜异质结进行退火,得到Si0.25Ge0.75/Ge应变薄膜异质结。
2.根据权利要求1所述的一种应变薄膜异质结的制备方法,其特征在于,步骤S4中的所述镉过渡层的厚度为10~20nm。
3.根据权利要求1所述的一种应变薄膜异质结的制备方法,其特征在于,在步骤S5中所述Si0.25Ge0.75层的厚度为200nm,所述Si0.25Ge0.75层呈非晶相。
4.根据权利要求1所述的一种应变薄膜异质结的制备方法,其特征在于,步骤S7中退火的具体方法为:所述薄膜异质结在30s内迅速升温至650~800℃,并恒温保持1min,随后自然冷却至室温。
5.一种如权利要求1~4任一项所述的制备方法得到的应变薄膜异质结。
6.一种如权利要求5所述的应变薄膜异质结在四族半导体材料中的应用。
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