CN110780189A - SDIO interface test equipment and method based on FPGA - Google Patents

Abstract

The invention provides SDIO interface test equipment and a method based on FPGA, wherein the FPGA is used for designing a virtual SDIO card based on SDIO3.0 protocol to replace the existing entity SDIO card, the virtual SDIO card comprises a CMD processing module, a CIA module, a command response module and a read-write test module, the CMD processing module is respectively connected with the command response module and the read-write test module, and the command response module is also connected with the CIA module; the CIA module can provide the CCCR register, the FBR register and the CIS register to customize information meeting FT test requirements, so that the test equipment has universality, the test flexibility is greatly increased, and meanwhile, the hardware design is simplified and the test cost is reduced.

Description

SDIO interface test equipment and method based on FPGA

Technical Field

The invention relates to a test device and a test method for an SDIO interface.

Background

SDIO (secure Digital Input and output) defines a peripheral interface on the SD standard, and an important difference between the SDIO and the SD card specification is that a low-speed standard is added. Only SPI and 1-bit SD transfer modes are required in SDIO cards. The target application of the low speed card is to support low speed IO capability with minimal hardware overhead. The low speed card supports applications such as modems, bar code scanners, and GPS receivers. The high-speed card supports network cards, television cards, combination cards and the like. The combination card refers to memory + SDIO, and for the combination card, operation requires full speed and 4BIT transfer mode, which is specified by the SDIO1.0 standard.

The SDIO is one of the most important interface technologies of future embedded systems, so that a current mobile SOC (System on chip) processor is provided with at least one SDIO HOST interface to facilitate expansion of functions, so that the interface needs to be tested in an FT (final test) test before the SOC leaves a factory.

However, the test method needs to be externally connected with an SDIO card with a specific function and a software driver matched with the SDIO card, and any SDIO card does not contain all contents of an SDIO protocol, so that if some tests need to be added and the SDIO card does not have the function, the test cannot be performed. If the SDIO card manufacturer stops production or another SDIO test of the SOC does not adopt the SDIO card, software is driven to be rewritten, hardware is redesigned, and therefore the test cost is too high and flexibility is low.

Disclosure of Invention

The invention aims to solve the technical problem of providing SDIO interface test equipment and a method based on FPGA, wherein the FPGA is used for designing a virtual SDIO card based on SDIO3.0 protocol to replace the existing entity SDIO card, thereby not only reducing the test cost, but also improving the flexibility.

The test equipment of the invention is realized as follows: a SDIO interface test device based on FPGA comprises a CMD processing module, a CIA module, a command response module and a read-write test module, wherein the CMD processing module is respectively connected with a command response module and the read-write test module, and the command response module is also connected with the CIA module;

the CMD processing module receives a series of commands sent by the SOC through the sdio _ CMD pin, analyzes the commands and transmits the commands to the command response module, then obtains response data from the command response module, and finally returns the response data to the SOC through the sdio _ CMD pin;

the CIA module provides a CCCR register, an FBR register and a CIS register for customizing information meeting the test requirements;

the command response module returns data to be responded according to the type of the command, reads and writes the data of the CIA module to form response data when some commands are required, packs the response data into a command format and transmits the command format to the CMD processing module;

and the read-write test module reads and writes data according to the data transmission command CMD53 format, and stores a string of predefined data for data comparison and data transmission.

Furthermore, the test equipment also comprises a serial port module, wherein the serial port module is connected with the CMD processing module;

the serial port module receives the command type, the command parameter and the response data from the CMD processing module, converts the command type, the command parameter and the response data into ASCII codes, and finally sends the ASCII codes to the graphical interface according to the serial port format, and the graphical interface displays the command type, the command parameter and the response data.

Further, the test equipment is an SDIO card which is designed by using an FPGA and is based on an SDIO3.0 protocol.

The test method of the invention is realized as follows: the SDIO interface test method based on the FPGA is characterized in that the SDIO card is used for testing, and the SDIO card and the SDIO interface are correspondingly connected through pins during testing; and comprises the following processes:

an initialization process: pulling down the SDIO _ det pin by the CMD processing module to enable the SOC to be considered as having an SDIO card inserted, and receiving a series of commands sent by the SOC through the SDIO _ CMD pin for initialization; after receiving the command, the CMD module transmits the command to the command response module through the analysis of the command, the command response module determines whether the data of the CIA module needs to be read and written according to the command and simultaneously calculates a response datum, then transmits the response datum to the CMD processing module, and finally returns the response datum to the SOC through the sdio _ CMD pin;

and (3) reading data test process: the CMD processing module requests a string of predefined data to be transmitted to the SOC from the read-write testing module when receiving a read data command of the SOC, and the SOC compares the received data with the predefined data to obtain a test result of the read data;

and (3) writing data test process: when the CMD processing module receives a data writing command of the SOC, the read-write testing module receives a string of write testing data at the same time, and the string of write testing data is compared with data predefined by the read-write testing module to obtain a test result of the write data.

Further, the testing method of the present invention further comprises:

and (3) a graphical display process: in the test process, after the serial port module receives the type, the parameter and the response data of the command sent by the CMD processing module, the command is converted into an ASCII code, and finally the ASCII code is sent to a graphical interface according to the format of the serial port, and the type, the parameter and the response data of each command are displayed by the graphical interface.

The configuration process comprises the following steps: and configuring the CCCR register, the FBR register and the CIS register of the CIA module to customize the information meeting the test requirement.

And a signal display process: and in the testing process, displaying logic signals inside the FPGA through a logic analyzer carried by FPGA design software.

The invention has the following advantages: the invention uses the FPGA virtual-general SDIO card as the test equipment to replace the entity SDIO card with specific function, the virtual SDIO card comprises a CMD processing module, a CIA module, a command response module and a read-write test module, wherein the CIA module can provide a CCCR register, an FBR register and a CIS register to customize the information meeting the FT test requirement, so that the test equipment has universality to replace the existing entity SDIO card, the test flexibility is greatly increased, the hardware design is simplified, and the test cost is reduced. In addition, except for normal test, the signals of the EMMC interface can be observed in real time on a graphical interface, and meanwhile, the logic signals inside the FPGA are displayed through a logic analyzer of FPGA design software, so that the problem analysis is facilitated.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of the connection state between the SDIO interface test apparatus and the SOC of the present invention.

Fig. 2 is a schematic structural diagram of an internal circuit module of the SDIO interface test apparatus according to the present invention.

Fig. 3 is a diagram of internal register space allocation of the SDIO interface test apparatus of the present invention.

Fig. 4a is the first half of the initialization process of the SDIO interface test apparatus of the present invention.

Fig. 4b is the second half of the initialization process of the SDIO interface test apparatus of the present invention.

In which fig. 4a is the first half of the flow and fig. 4b is the second half of the flow.

Detailed Description

The SDIO interface test equipment based on the FPGA is an SDIO card based on an SDIO3.0 protocol, which is designed by using the FPGA, and the SDIO card can self-define the parameters of the card (such as the maximum bit width supported and whether a memory function exists or not), so that the general SDIO card can meet the test requirements. If additional testing is required, the hardware platform does not need to be redesigned as long as software-driven modifications, such as parameter reconfiguration, are made.

Referring to fig. 1, during testing, the SDIO card is correspondingly connected to an SDIO interface of the SOC through pins; the pins include sdio _ det, sdio _ clk, sdio _ cmd, and sdio _ data [3.0 ].

As shown in fig. 2, in a hardware structure, the SDIO card includes a CMD processing module, a CIA module, a command response module, and a read/write test module, where the CMD processing module is connected to the command response module and the read/write test module, respectively, and the command response module is further connected to the CIA module; the test equipment also comprises a serial port module, and the serial port module is connected with the CMD processing module.

Wherein the content of the first and second substances,

the CMD processing module receives a series of commands sent by the SOC through the sdio _ CMD pin, namely initializes the commands, analyzes the commands and transmits the commands to the command response module, then obtains response data from the command response module, and finally returns the response data to the SOC through the sdio _ CMD pin; some commands in the protocol need to respond to specific data on sdio _ data in addition to this response data, such as: CMD19, which requires the SDIO card to respond to a string of known data on SDIO _ data for adjusting the sampling point.

The CIA module provides a CCCR register, an FBR register and a CIS register for customizing information meeting FT test requirements; as shown in FIG. 3, the CIA (Common IOArea) module comprises three information items of CCCR (Card Common control registers), FBR (function Basic registers) and CIS (Card's Common Card information structure); the CCCR defines a common control register of the SDIO card, and the SOC can check the SDIO card and operate the FBR by operating the CCCR; FBR defines the supported operation of FBR1 through FBR7, including various requirements and functions, power control, etc.; the CIS defines the information structure of some cards, and the CIS has a common CIS and a CIS for each FBR. By customizing register values of three areas of CCCR, FBR and CIS, an SDIO card meeting FT test can be customized, which is the core of the generality of the SDIO card.

And the command response module returns data to be responded according to the type of the command, reads and writes the data of the CIA module to form response data when some commands are required, packs the response data into a command format and transmits the command format to the CMD processing module.

And the read-write test module reads and writes data according to the data transmission command CMD53 format, and stores a string of predefined data for data comparison and data transmission. Specifically, the read-write test module can select whether to read and write by taking bytes as a unit or block (default 512 bytes according to the length set by the SOC) as a unit according to the format of a data transmission command CMD53, the read-write data test module supports single-block read-write and multi-block read-write, and the test methods of the single-block read-write and the multi-block read-write are roughly consistent, and the difference is that the single-block read-write only transmits data of one block, and the multi-block transmits more than two block data.

The serial port module receives the command types, the command parameters and the response data from the CMD processing module, converts the command types, the command parameters and the response data into ASCII codes, and finally sends the ASCII codes to the graphical interface according to the format of the serial port, and the graphical interface displays the command types, the command parameters and the response data.

When a test is started, the CMD processing module pulls down the SDIO _ det pin to enable the SOC to be considered to have an SDIO card inserted, the SOC sends a series of commands to the SDIO card through the SDIO _ CMD pin, after the CMD module receives the commands, the commands are transmitted to the command response module through analysis of the commands, the command response module determines whether data of the CIA module needs to be read and written or not according to the commands, meanwhile, a response datum is calculated, then the response datum is transmitted to the CMD processing module, and finally the CMD processing module returns the response datum to the SOC through the SDIO _ CMD pin (certain commands in the protocol need to respond to specific data on SDIO _ data besides the response datum). And after the SDIO card is identified, data read-write test can be carried out.

The test flow comprises the following steps:

and (3) reading data test process: the CMD processing module requests a string of predefined data to be transmitted to the SOC from the read-write testing module when receiving a read data command of the SOC, and the SOC compares the received data with the predefined data to obtain a test result of the read data;

and (3) writing data test process: when the CMD processing module receives a write data command of the SOC, the read-write testing module simultaneously receives a string of write test data, compares the string of write test data with self predefined data to obtain a test result of write data, and the test result is fed back through test _ status [7:0 ].

Based on the test equipment, the invention also provides an SDIO interface test method based on the FPGA, the SDIO card is used for testing, and the SDIO card and the SDIO interface are correspondingly connected through pins during testing; and comprises the following processes:

an initialization process: pulling down the SDIO _ det pin by the CMD processing module to enable the SOC to be considered as having an SDIO card inserted, and receiving a series of commands sent by the SOC through the SDIO _ CMD pin for initialization; after receiving the command, the CMD module transmits the command to the command response module through the analysis of the command, the command response module determines whether the data of the CIA module needs to be read and written according to the command and simultaneously calculates a response datum, then transmits the response datum to the CMD processing module, and finally returns the response datum to the SOC through the sdio _ CMD pin; as shown in fig. 4a and 4b, the initialization process is performed.

And (3) reading data test process: the CMD processing module requests a string of predefined data to be transmitted to the SOC from the read-write testing module when receiving a read data command of the SOC, and the SOC compares the received data with the predefined data to obtain a test result of the read data;

and (3) writing data test process: when the CMD processing module receives a data writing command of the SOC, the read-write testing module receives a string of write testing data at the same time, and the string of write testing data is compared with data predefined by the read-write testing module to obtain a test result of the write data.

Further comprising:

and (3) a graphical display process: in the test process, after the serial port module receives the type, the parameter and the response data of the command sent by the CMD processing module, the command is converted into an ASCII code, and finally the ASCII code is sent to the graphical interface according to the format of the serial port, and the type, the parameter and the response data of each command are displayed by the graphical interface. And a signal display process: and in the testing process, displaying logic signals inside the FPGA through a logic analyzer carried by FPGA design software. The user can observe the process and the result of each operation, and the advantage of the method is that the reason of the test failure can be better analyzed.

In the method of the present invention, if some test functions need to be added or parameters need to be modified, the method may further include the following steps:

the configuration process comprises the following steps: and configuring the CCCR register, the FBR register and the CIS register of the CIA module to customize the information meeting the FT test requirement. Such as the maximum bit width supported, whether there is a memory function, etc.

Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.

Claims (7)

1. The utility model provides a SDIO interface test equipment based on FPGA which characterized in that: the virtual SDIO card is built through FPGA logic and comprises a CMD processing module, a CIA module, a command response module and a read-write test module, wherein the CMD processing module is respectively connected with a command response module and the read-write test module, and the command response module is also connected with the CIA module;

the CMD processing module receives a series of commands sent by the SOC, analyzes the commands, transmits the commands to the command response module, obtains response data from the command response module, and finally returns the response data to the SOC;

the CIA module provides a CCCR register, an FBR register and a CIS register for customizing information meeting the test requirements;

the command response module returns data to be responded according to the type of the command, reads and writes the data of the CIA module to form response data when some commands are required, packs the response data into a command format and transmits the command format to the CMD processing module;

the read-write test module receives the data of the command analysis module and judges whether the data is a read-write command, if so, the read-write test module starts to read-write the data and stores a string of predefined data for data comparison and data transmission.

2. The SDIO interface test device based on FPGA of claim 1, characterized in that: the CMD processing module is connected with the serial port module;

the serial port module receives the command type, the command parameter and the response data from the CMD processing module, converts the command type, the command parameter and the response data into ASCII codes, and finally sends the ASCII codes to the graphical interface according to the serial port format, and the graphical interface displays the command type, the command parameter and the response data.

3. The SDIO interface test device based on FPGA of claim 1, characterized in that: the virtual SDIO card is formed by virtualizing an FPGA based on an SDIO3.0 protocol.

4. A SDIO interface test method based on FPGA is characterized in that: testing by using the virtual SDIO card of claim 1, wherein the SDIO card and the SDIO interface are correspondingly connected through pins during testing; and comprises the following processes:

an initialization process: pulling down an SDIO _ det pin through the CMD processing module to enable the SOC to be considered as having an SDIO card inserted, and receiving a series of commands sent by the SOC through the SDIO _ CMD pin for initialization; after receiving the command, the CMD module transmits the command to the command response module through the analysis of the command, the command response module determines whether the data of the CIA module needs to be read and written according to the command and simultaneously calculates a response datum, then transmits the response datum to the CMD processing module, and finally returns the response datum to the SOC through the sdio _ CMD pin;

and (3) reading data test process: the CMD processing module requests a string of predefined data to be transmitted to the SOC from the read-write testing module when receiving a read data command of the SOC, and the SOC compares the received data with the predefined data to obtain a test result of the read data;

and (3) writing data test process: when the CMD processing module receives a data writing command of the SOC, the read-write testing module receives a string of write testing data at the same time, and the string of write testing data is compared with data predefined by the read-write testing module to obtain a test result of the write data.

5. The SDIO interface test method based on the FPGA of claim 4, characterized in that: further comprising:

and (3) a graphical display process: in the test process, after the serial port module receives the type, the parameter and the response data of the command sent by the CMD processing module, the command is converted into an ASCII code, and finally the ASCII code is sent to a graphical interface according to the format of the serial port, and the type, the parameter and the response data of each command are displayed by the graphical interface.

6. The SDIO interface test method based on the FPGA of claim 4, characterized in that: before the initialization process, the method further comprises the following steps:

the configuration process comprises the following steps: and configuring the CCCR register, the FBR register and the CIS register of the CIA module to customize the information meeting the test requirement.

7. The SDIO interface test method based on the FPGA of claim 4, characterized in that: further comprising:

and a signal display process: and in the testing process, displaying logic signals inside the FPGA through a logic analyzer carried by FPGA design software.

Images