CN110764394A

CN110764394A - Time-to-digital conversion circuit applied to SPAD detector

Info

Publication number: CN110764394A
Application number: CN201810827996.1A
Authority: CN
Inventors: 毛成; 卜晓峰; 孔祥顺; 吴俊辉
Original assignee: CHAORUI MICROELECTRONICS Co Ltd SUZHOU
Current assignee: CHAORUI MICROELECTRONICS Co Ltd SUZHOU
Priority date: 2018-07-25
Filing date: 2018-07-25
Publication date: 2020-02-07

Abstract

The invention discloses a time-to-digital conversion circuit applied to an SPAD detector, which adopts a series of buffers and D triggers to realize the conversion function from time signals to digital signals by the vernier caliper principle. In the time-to-digital conversion circuit, a start signal and a stop signal are respectively transmitted on two delay chains with different delay speeds, each level of start signal transmitted by a buffer is connected with the D end of the input end of one D trigger, each level of stop signal transmitted by the buffer is connected with the clock input end of the corresponding D trigger, and the Q end of the output end of the D trigger is the digital signal output end.

Description

Time-to-digital conversion circuit applied to SPAD detector

Technical Field

The invention relates to a time-to-digital conversion circuit applied to an SPAD detector, namely a TDC circuit, and belongs to the field of integrated circuits.

Background

The time-to-digital converter is a conversion circuit that converts an analog amount of time into a digital signal for measuring a time interval. With the rise of the Time of Flight (TOF) technology in the field of laser ranging, Time-to-digital converters become increasingly important and become a key technology. The resolution of the time-to-digital converter directly determines the ranging precision of the laser ranging. The high-precision distance measurement requirement is indispensable in many applications, for example, in the docking application of a spacecraft, the distance measurement precision requirement reaches the millimeter level, and the corresponding time interval precision requirement reaches the level of several picoseconds.

Single Photon Avalanche Diode (SPAD) has photon level detection capability and has unique advantages in laser ranging applications. A single SPAD tube is used as a single-point distance measuring detector, a time-to-digital conversion circuit is required to be integrated, the circuit structure is required not to be excessively complex, and the conversion speed must be high enough.

At present, in the prior art, the traditional analog-digital converter has a complex circuit structure, and the conversion speed and the conversion precision are not high; the existing time-to-digital conversion circuit technology has the disadvantages that the circuit structure design is not simplified enough, and the time resolution is difficult to reach a level of several picoseconds.

Disclosure of Invention

The purpose of the invention is as follows: in order to overcome the defects in the prior art, the invention provides the time-to-digital conversion circuit applied to the SPAD detector, the circuit structure is simpler, and the time resolution can be ensured.

The technical scheme is as follows: in order to achieve the purpose, the technical scheme of the invention is as follows:

a time-to-digital conversion circuit applied to an SPAD detector adopts a series of buffers and D triggers, an upper delay chain and a lower delay chain are formed by the buffers, wherein each level of buffer output of one delay chain is connected with the D end of the input end of one D trigger, each level of buffer output of the other delay chain is connected with the clock input end of the corresponding D trigger, and the Q end of the output end of the D trigger is a digital signal output end and used for representing the length of a time interval.

The two delay chains have different delay times, one delay chain with a relatively longer delay time is used as an input delay chain of a start signal, namely a start signal, and the other delay chain with a relatively shorter delay time is used as an input delay chain of an end signal, namely a stop signal. Both the start signal and the stop signal may be provided by the SPAD detector and transmitted as digital pulse signals on the delay chain. The start signal is input first and transmitted on the delay chain with longer delay time, and then the stop signal is input and transmitted on the delay chain with shorter delay time. The stop signal rapidly advances on the delay chain, the distance between the stop signal and the start signal is reduced, the stop signal is aligned with the start signal after passing through the multi-stage buffer, and at the moment, the D end effective signal '1' is recorded by the D trigger when the clock signal is high, and the D end effective signal is output by the Q end of the D trigger. The output of the Q end of the other D triggers is 0 because the input signal of the D end is low when the clock signal is high.

Has the advantages that: compared with the prior art, the time-to-digital conversion circuit applied to the SPAD detector has the following advantages that: 1. the circuit structure is simple, the circuit is particularly suitable for being integrated with an SPAD detector chip, 2, the time resolution is high, and the time resolution can reach several picoseconds by accurately designing the delay time difference of two delay chains.

Drawings

Fig. 1 is a schematic structural diagram of a time-to-digital conversion circuit provided by the present invention;

fig. 2 is an example of an operation timing diagram of the time-to-digital conversion circuit provided by the present invention.

Detailed Description

The invention will be further described with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a time-to-digital conversion circuit provided by the present invention, which adopts a series of buffers and D flip-flops, and an upper delay chain and a lower delay chain are formed by the buffers, wherein each stage of buffer output of one delay chain is connected to an input end D of one D flip-flop, each stage of buffer output of the other delay chain is connected to a clock input end of a corresponding D flip-flop, and an output end Q of the D flip-flop is a digital signal output end for representing the length of a time interval.

Fig. 2 shows an example of an operation timing diagram of the time-to-digital conversion circuit provided by the present invention, which includes four groups of signals, each group of signals includes two signals, namely a black solid line and a dashed line, all the solid line signals include a start signal, an a1 signal, an a2 signal, and an A3 signal, which are signals input to the delay chain at start, i.e. the delay chain at the top in fig. 1; all the dashed signals include a stop signal, a B1 signal, a B2 signal, and a B3 signal, and are signals on the stop input delay chain, i.e., the delay chain at the bottom in fig. 1. Two signals in each group, such as a start signal and a stop signal, an a1 signal and a B1 signal, an a2 signal and a B2 signal, and an A3 signal and a B3 signal, are signals input to the same D flip-flop. Specifically, in the example of fig. 2, the delay time Δ t of the start input delay chain₁Delay time deltat of stop input delay chain of 5 unit time₂And 4 unit time, after the start signal is input into the delay chain, 7 unit time stop signals are generated and input into the delay chain. The start signal and the stop signal are respectively transmitted in respective delay chains, and because the stop signal is generated later and the delay time of the delay chain where the stop signal is located is shorter, a situation that the signal in the stop input delay chain catches up with the signal in the start input delay chain is formed, that is, the distance between the dotted line rising edge and the solid line rising edge in fig. 2 is continuously reduced from top to bottom until the dotted line rising edge and the solid line rising edge are overlapped, and at this time, the output signal of the D flip-flop is "1". Since the D flip-flop is level triggered, when the stop signal catches up and leads the start signal, i.e. the dashed rising edge precedes the solid rising edge, the output of the D flip-flop is still "1" as long as the signals still overlap, i.e. the dashed falling edge is also after the solid rising edge.

By reading the output Q of individual flip-flops₀Q₁Q₂……Q_nThe time interval between the start signal and the stop signal can be calculated. Specifically, the value of Q should be "1" in the middle section, both the front and rear ends are "0", and the first bit of the flip-flop with Q "1" is taken, i.e. Q_iThe value of i when =1 is multiplied by the time unit, and the result is the time interval thus obtained.

Claims

1. A time-to-digital conversion circuit applied to an SPAD detector is characterized in that: the circuit adopts a series of buffers and D triggers, an upper delay chain and a lower delay chain are formed by the buffers, wherein each level of buffer output of one delay chain is connected with the D end of the input end of one D trigger, each level of buffer output of the other delay chain is connected with the clock input end of the corresponding D trigger, and the Q end of the output end of the D trigger is a digital signal output end and is used for representing the length of a time interval.

2. The time-to-digital conversion circuit for an SPAD detector according to claim 1, further characterized by: the delay times of the two delay chains are different, and one delay chain with a relatively longer delay time is used as an input delay chain of a start signal, namely a start signal, and the other delay chain with a relatively shorter delay time is used as an input delay chain of an end signal, namely a stop signal.