CN106168753B - time-to-digital converter - Google Patents
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- CN106168753B CN106168753B CN201610490998.7A CN201610490998A CN106168753B CN 106168753 B CN106168753 B CN 106168753B CN 201610490998 A CN201610490998 A CN 201610490998A CN 106168753 B CN106168753 B CN 106168753B
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The invention discloses a time-to-digital converter, which comprises a time-to-digital conversion unit, a digital time conversion unit and a time amplifier, wherein: the time digital conversion unit is used for carrying out digital quantization on time to realize the digital quantization function of the time; a digital time conversion unit for extracting a portion of the time margin that is less than the quantization time unit and is not quantized; and a time amplifier for linearly amplifying the portion of the time margin extracted by the digital time conversion unit to further perform digital quantization. The time-to-digital converter provided by the invention can meet the performance requirements of high time precision, wide range, high conversion rate and the like. The method is applied to the application field of time mode signal processing technology, and can improve the precision and speed of time-to-digital conversion.
Description
Technical field
The present invention relates to temporal mode signal processing technology application field, especially a kind of high-precision time-to-digital converter
Device (time to digital converter), such as all-digital phase-locked loop, rangefinder, flowmeter etc..
Background technology
From the application projects such as communication, digital oscilloscope, medical imaging field, ground to Atomic Physics, astronomical observation scheduling theory
Study carefully the space flight military industrial technology such as field and laser, radar range finding and satellite positioning field, all be unable to do without high-precision time interval
Measuring technique.Different application environments has the precision of time interval measurement different requirements.In daily life, it is accurate to point
The time interval precision of clock magnitude can meet the general requirements of people, but the fields such as modern military, communication, navigation are answered
With the precision of minute magnitude is far from enough, and with the demand of these field technology developments, the requirement to time precision is increasingly
It is high.1 second time error can cause the underway naval vessel in sea to drift off the course hundreds of meters, and the time error of 1 microsecond can cause to navigate
Its aircraft cannot make a return voyage safely.In addition, for the accuracy for ensuring military precision strike, effectively improving guidance and ignition,
It is required that time interval precision reach nanosecond even magnitude of subnanosecond.
In time interval measurement technology, at present it is most commonly used, be widely time-to-digit converter TDC.TDC is
A kind of special circuit technology that time interval is quantified as to digital quantity, is set forth in the 1980s earliest.TDC early stages mainly answer
For high-energy physics experiment, such as nuclear physics, for average life span, the measurement of transition time and Ion identification etc., these measurements pair
The required precision of TDC is very high.Currently, TDC not only plays important role in scientific experiment, but also in practical application
Flying time mass spectrum analysis also plays an important role, such as the positron emission fault in laser ranging and medical imaging technology
Scan PET.
TDC designing techniques there are the pentagon-based theorem of one " precision-range ability-conversion ratio-linearity-area ", this
A little parameters mutually restrict.And TDC is mainly still measurement and the Function Extension of time correlation from the point of view of current application,
The importance of time precision is primary, the whether commercial chip of industrial quarters maturation or the research hotspot of academia, more
High time precision is the target constantly pursued.At the same time, with the development of temporal mode signal processing technology, each field is answered
It is also higher and higher with the requirement to performances such as TDC range abilities, conversion ratios.
It is, therefore, desirable to provide one kind can realize higher time precision and can improve time-quantum method range and conversion rate
Time-to-digit converter structure.
Invention content
(1) technical problems to be solved
The main purpose of the present invention is to provide the time figures of a kind of high-precision, wide-range range and high conversion rate to turn
Parallel operation.
(2) technical solution
In order to achieve the above objectives, the present invention provides a kind of time-to-digit converters, when which includes
Between digital conversion unit, digit time converting unit and time amplifier, wherein：Time-to-digital converter unit, for the time
Digital quantization is carried out, realizes the digital quantization function of time；Digit time converting unit is less than quantization time unit for extracting
And the time margin part not being quantized；Time amplifier, the time margin part for extracting digit time converting unit
Linear Amplifer is carried out further to carry out digital quantization.
In said program, which has a delay chain, which is connected by multiple delay cells connects
It connects, the output end of each delay cell connects a d type flip flop and a switch simultaneously, and multiple d type flip flops, which are constituted, to be touched
Send out device group, multiple switch constitutes switching group, and the delay chain and the trigger group constitute time-to-digital converter unit, the delay chain with
The switching group constitutes digit time converting unit.
In said program, it is connected with a counter in the output end of the delay chain, the counter is by Reset signal rising edges
Triggering, while all delay cells in the Reset signals rising edge reset delay chain, counter records delay chain are complete 1 shape
The number of state, and then improve the input time range ability of the time-to-digit converter.
In said program, the digit time converting unit is connected with switch control signal Dout, the switch control signal
Dout and the time-to-digital converter unit time is carried out digital quantization output result D0, D1 ..., the relationship between D6 such as
Shown in following table：
1 TDC control word truth tables of table
In said program, the time margin part of the digit time converting unit extraction, no more than prolonging for delay cell
The slow time, the time amplifier to the time margin part carry out Linear Amplifer, improve time-to-digital converter efficiency and
Precision.
(3) advantageous effect
Time-to-digit converter provided by the invention, when each Tin period starts, Trigger signals are low level.
During the high level time length of Tin, through enabling EN, time-to-digital converter unit 20 is as unit of time τ to Tin into line number
Word quantization output.It is more than the Tin of delay chain time span for high level time length, using counter 211 to delay chain
All one state number is counted, and is converted into quantization numeral output, to improve the time-quantum method range of time-to-digit converter.
For in Tin due to less than τ can not digital quantization part time margin, need Trigger high level effect under, lead to
Digit time converting unit 10 is crossed, this part-time surplus less than τ is extracted in the form of complement code, and by time-reversal mirror
Device 30 carries out Linear Amplifer further to carry out digital quantization.In turn, time-to-digit converter provided by the present invention can be with
Meet the performance requirements such as high time precision, wide-range range, high conversion rate.It is applied answers in temporal mode signal processing technology
With the accuracy and speed that time-to-digital converter in field, can be improved.
Description of the drawings
Fig. 1 is the schematic diagram according to the time-to-digit converter of the embodiment of the present invention.
Fig. 2 is the working timing figure as Tin=20.3 τ corresponding to Fig. 1.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
In recent years, TDC technologies are begun to appear in si-substrate integrated circuit.Due to the fast development of CMOS technology technology,
The reduction of characteristic size improves cmos circuit integrated level and robustness, reduces circuit power consumption and cost so that people more incline
To being handled in converting analog signals into digital signal, so analog-digital converter becomes essential module.However,
When CMOS technology develops to smaller characteristic size, conventional voltage pattern analog-digital converter is by feature size downsizing and power supply electricity
The limitation of the factors such as pressure reduction, it is difficult to meet high-resolution requirement, therefore scholars start emphasis turnaround time mode signal
The research of processing circuit, TDC become an important research direction.
For TDC precision problems are improved, industrial quarters is proposed the TDC commercial chips based on GaAs techniques, and time precision is
10ps.And the TDC chips of HYPRES companies of the U.S. be even more it is similar in outstanding person, chip be based on HYPRES Nb/AlOx/Nb
The time precision of tri-layer techniques, realization reaches 6ps.However, in order to reduce cost and be easy to integrated with other functional circuits
Realize miniaturization, in recent years, CMOS TDC just by the increasing concern of industrial circle, have there is ripe high-precision at present
CMOS TDC commercial chips are released, these commercial chips are mainly directed towards spectrum analysis, TOF measurements, medical imaging and ultrasonoscope
Amount etc. is to the higher market of time required precision, such as MAX35101, MAX35102 and MAX35103 of U.S.'s MAXIM company,
Time-quantum method reaches 8ms, and precision reaches 20ps；The TDC-GP1 and TDC-GP2 of German ACAM companies, time-quantum method 3.5ns-
1.8us, measurement accuracy reach 50ps.Its upgraded version TDC-GP21 and TDC-GP22, time-quantum method 500ns-4ms, it measures
Precision can reach 22ps.
In academia, scholars utilize advanced CMOS integrated circuit techniques, have developed a large amount of TDC technologies.Current
CMOS TDC technologies are based primarily upon gate delay unit, the reduction of CMOS technology characteristic size are benefited from, when the delay of gate delay unit
Between accordingly reduce, this is conducive to the raising of TDC time precisions.CMOS TDC technologies can be classified as based on field programmable gate array
FPGA structure and customization structure.
TDC based on on-site programmable gate array FPGA most flexibilities are integrated with the progress of CMOS technology technology
Spend higher and higher, function is more and more perfect.This TDC structures generally use time delay chain method or differential delay chain method, can reach
Up to a hundred picoseconds even tens picoseconds of measurement accuracy.2013, Virtex-s of the M.W.Fishburn et al. based on Xilinx companies
The TDC of 6 type FPGA designs, realization time precision are 19.6ps, time-quantum method ranging from 40ns.But the time of this structure
Range ability is small, time precision is limited to that gate delay unit, power consumption are big, are not suitable for large batch of application.
Customizing TDC structures has maximum design flexibility and best performance (high precision, minimum area, pole
Low power consumption etc.), it is that current CMOS TDC study field the most active.
Time delay chain TDC is earliest, is also most widely used customization TDC structures, operation principle and structure and tradition electricity
Die pressing type quick flashing type analog-to-digital converter ADC is similar.Its, register unit cascaded by gate delay and thermometer encoder form.This
The advantages of kind structure, is simple in structure, can be realized with digital logic gate that especially time-to-digital converter rate is all customizations
It is most fast in TDC structures, but its time precision is limited to the gate delay time, while its time-quantum method range is small, to increase
The quantity that its time-quantum method range often leads to delay cell is added to linearly increase, to increase chip area and power consumption, in addition,
Also reduce time-to-digital converter rate.
In order to solve the problems, such as that the time precision of TDC is limited to gate delay unit, scholars propose various methods to use
Gate delay unit realizes the delay time of subphylum grade, realizes the temporal resolution less than single gate delay.
Vernier type TDC structures are a kind of widely applied industry gate level delay structures, this TDC contain two respectively have it is identical
The delay line of number delay cell, by making the delay time td1 and td2 of gate delay unit in two delay lines, there are subtle
Time difference, you can realize that precision is the time interval measurement of Δ=td1-td2, therefore, theoretically by adjusting two delay lines
The time difference of delay cell can measure infinitesimal time precision.2000, D.Piotr et al. devised a vernier
Type TDC, highest resolution is up to 5ps.But vernier type TDC to the raising of time precision nor infinitely improve, it is practical
Raising multiple be limited in 4-10 times.Meanwhile in delay chain TDC limiting factor (such as time-quantum method range, delay cell
Poor linearity caused by non-match error) more serious in vernier type TDC, its conversion rate in same time range ability
Also below delay chain TDC.Although the non-match error of collimation technique compensation delay cell may be used, collimation technique is complicated
And it needs according to depending on system structure.
In view of the above problems, vernier type TDC has derived many structures, such as two based on time delay chain and vernier type
Step TDC structures, 2D- vernier type TDC, 3D- vernier types TDC, vernier-annular TDC, vernier-GRO TDC and cycle-vernier type prolong
Slow line, but these structures are only the reduction of the quantity of delay cell, and conversion ratio, time-quantum method range do not improve but, the linearity
Performance is not improved, and the technology that calibrates for error is still complicated.
Another kind improve TDC precision subphylum grade delay technology be interpolation technique, be exactly gate delay unit input with
Resistance or logic gate are inserted between output, generate between gate delay unit output and input between average signal.2008,
S.Henzler et al. proposes that a kind of TDC based on passive interpolation method, the TDC utilize the electricity in parallel with main signal delayed branch
Resistance string, to delay time of a delay cell into row interpolation, to obtain the temporal resolution of subphylum grade, the document uses 4
Interpolation again, realizes the temporal resolution of 4.7ps, still, this passive interpolation structure is especially limited to the non-linear of resistance.
The shortcoming of interpolation TDC also resides in that time-quantum method range is small, conversion rate is low, non-caused by the non-match error of delay cell
It is linearly poor etc..
In recent years, in order to while improving TDC time precisions, improve its conversion rate, time amplifier thought is met the tendency of
And give birth to, it is based on time amplifier, scholars propose two step time-reversal mirror type TDC, annular time-reversal mirror type TDC and asynchronous flowing water
Line time-reversal mirror type TDC structures.After these TDC usage times amplifiers are to small time interval amplification, " coarse " only is used only
Quantizer just can obtain higher temporal resolution.2014, the two step time-reversal mirror streams that KwangSeok Kim et al. are proposed
The advantages of water type TDC structures, time precision reach 1.12ps, and conversion rate reaches 250MS/s, this structure is in addition to precision
Except high, conversion rate height, do not need any calibration algorithm, but the disadvantage is that time-quantum method range is small, delay cell not
Non-linear difference caused by matching error.Meanwhile there is also shortcomings for the time amplifier of these TDC structures, in order to obtain
Accurate time-reversal mirror gain, needs correcting circuit.Input linear gain ranging is small；Also a kind of time amplifier structure, is adopted
Single time pulse (pulse width is τ 1) of input is changed into multiple same pulse widths (each with delay cell and/or logic gate
Pulse width be τ 1) pulse train, in order to avoid the overlapping of each pulse in pulse train, when needing the delay of delay cell
Between >=τ 1, which has limited the raisings of TDC conversion ratios.
In conclusion there are five sides of one " precision-range ability-conversion ratio-linearity-area " for TDC designing techniques
Shape rule, these parameters mutually restrict.And TDC is mainly still measurement and the work(of time correlation from the point of view of current application
Can extension, the importance of time precision is primary, and whether the commercial chip of industrial quarters maturation or academia grind
Study carefully hot spot, higher time precision is the target constantly pursued.At the same time, with the hair of temporal mode signal processing technology
Exhibition, each field are also higher and higher using the requirement to performances such as TDC range abilities, conversion ratios.
In view of the demand, the present invention provides a kind of time-to-digit converters, as shown in Figure 1, the time-to-digital converter
Device includes time-to-digital converter unit, digit time converting unit and time amplifier, wherein：Time-to-digital converter unit is used
In carrying out digital quantization to the time, the digital quantization function of time is realized；Digit time converting unit is less than quantization for extracting
Chronomere and the time margin part not being quantized；Time amplifier, the time for extracting digit time converting unit
Balance carries out Linear Amplifer further to carry out digital quantization.
In Fig. 1, which has a delay chain, the delay chain be connected in series with by multiple delay cells and
At the output end of each delay cell connects a d type flip flop and a switch simultaneously, and multiple d type flip flops constitute trigger
Group, multiple switch constitute switching group, which constitutes time-to-digital converter unit with the trigger group, which opens with this
Pass group constitutes digit time converting unit.
It is connected with a counter in the output end of the delay chain, which is triggered by Reset signal rising edges, simultaneously
All delay cells in the Reset signals rising edge reset delay chain, counter records delay chain are the number of all one state,
And then improve the input time range ability of the time-to-digit converter.
Digit time converting unit is connected with switch control signal Dout, switch control signal Dout and the time number
Word converting unit the time is carried out digital quantization output result D0, D1 ..., the relationship between D6 it is as shown in the table：
1 TDC control word truth tables of table
The time margin part of the digit time converting unit extraction, is not more than the delay time of delay cell, described
Time amplifier carries out Linear Amplifer to the time margin part, improves the efficiency and precision of time-to-digital converter.
Below by specific embodiment and Fig. 1 and Fig. 2 is combined to do further in detail the time-to-digit converter of the present invention
Description.
Fig. 1 is the schematic diagram according to the time-to-digit converter of the embodiment of the present invention.The time-to-digit converter mainly by
Time-to-digital converter unit 20, digit time converting unit 10 and time amplifier 30 are constituted.Wherein, time-to-digital converter unit
20 by delay cell 201,202 ..., 208, counter 211 and trigger 221,222 ..., 227 constitute, realize to time Tin
Digital quantization.Digit time converting unit 10 by delay cell 201,202 ..., 208 and switch 101,102 ..., 108 structures
At extraction of the realization to the time margin of less than one delay unit τ in time Tin.Time amplifier 30 is realized to more than the time
N times of Linear Amplifer of amount, wherein N are programmable.
When each Tin period starts, Trigger signals are low level.When Tin becomes high level from low level,
Through or door 40, EN high level is also become from low level, 1 level of logic by delay cell 201,202 ..., 208 delays constituted
Transmitted in chain, until Tin and EN becomes low level, at this time delay cell 201,202 ..., 208 switch to protect by transmission working condition
Hold state.Tin failing edges trigger the rising edge of CK, trigger 221,222 ..., 227 using delay time T as quantization unit, respectively
To delay cell 201,202 ..., 208 output sample, in conjunction with TDC control truth table generate switch 101,102 ..., 108
Control word.After the completion of sampling, Trigger signals become high level, warp or door 40 from low level, and EN is become from low level again
High level, the continuation of 1 level of logic are transmitted in delay chain, the switch that 1 level of logic is closed by some in switching group, input
To the input terminal of time amplifier, 1 level of logic and the Trigger of this arrival carry out logic XOR operation, with the shape of complement code
Formula by Tin due to less than τ can not the time margin of digital quantization extract, and pass through time amplifier 30 and carry out timeline
Property amplification, further to carry out time-to-digital converter.
Fig. 2 is the sequence diagram that the high level time of hypothesis Tin in the embodiment of the present invention is 20.3 τ, and the rising edge of Tin is (low
Level becomes high level) pass through or door 40, promote EN also to become high level from low level.By 8 delay cells 201,202 ...,
The 208 equal delay chains that constitute are in the case where the high level of EN is enabled, and 1 level of logic transmits in delay chain, until Tin is become from high level
Low level, at this time EN low level is also become from high level, delay cell 201,202 ..., 208 output be hold mode.
Tin failing edge triggering CK rising edges generation, by trigger 221,222 ..., 227, to delay cell 201,
202 ..., 208 output is sampled, in conjunction with counter export Dout and trigger 221,222 ..., 227 sampling outputs, i.e.,
The digital quantization result of Tin high level times can be obtained.Since the delay time of each delay cell in delay chain is τ, so
The count value Dout of counter is 2, and corresponding binary one 0, trigger group exports D6D5D4D3D2D1D0It is 0001111.
Actually digital quantization output of the time-to-digital converter unit to the Tin corresponding time is 20 τ, 0.3 τ of surplus
It can not be quantified since minimum delay time is limited.In order to improve TDC precision, need to find out 0.3 τ of surplus to come, and
It is further amplified, further thin quantization is carried out to give rear stage TDC.
Trigger 221,222 ..., 227 complete sampling after, the TDC control words truth table in conjunction with shown in following table, switch
Control word is 100, and correspondingly, switch 105 is connected.The rising edge of Trigger signals arrives after sampling is completed, and EN becomes again
For high level, the continuation of 1 level of logic is transmitted in delay chain, and after by 0.7 τ, 1 level of logic passes through switch 105, output
XOR operation is carried out to the input terminal Arr of time amplifier 30, and with Trigger, after N times of amplification of time amplifier,
Tout output pulse widths are the τ of N × 0.7.
Digit time converting unit is switched to the form output 0.7 of complement code without directly exporting 0.3 τ of surplus
τ。
Due to that can be amplified to actual time margin and further quantify, so improving time precision.By right
Output per level-one delay cell carries out " when m- number conversion " and " number-time converts ", improves the conversion rate of TDC.
By the way that the amplification factor N of time amplifier 30 is arranged, can time precision further be improved N times.By the way that counter 211 is arranged
Count value, can effectively improve the time-quantum method range of TDC.
TDC control word truth tables
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the present invention
Within the scope of shield.
Claims (4)
1. a kind of time-to-digit converter, which is characterized in that the time-to-digit converter includes time-to-digital converter unit, number
Time converting unit and time amplifier, wherein：
Time-to-digital converter unit realizes the digital quantization function of time for carrying out digital quantization to the time；
Digit time converting unit, for extracting the time margin part not being quantized less than quantization time unit；
Time amplifier, the time margin part for extracting digit time converting unit carry out Linear Amplifer so as to further
Carry out digital quantization；
Wherein, the time margin part of the digit time converting unit extraction, is not more than the delay time of delay cell, described
Time amplifier carries out Linear Amplifer to the time margin part, improves the efficiency and precision of time-to-digital converter.
2. time-to-digit converter according to claim 1, which is characterized in that the time-to-digit converter has a delay
Chain, the delay chain are connected in series by multiple delay cells, output end one D triggering of connection simultaneously of each delay cell
Device and a switch, multiple d type flip flops constitute trigger group, and multiple switch constitutes switching group, the delay chain and the trigger group
Time-to-digital converter unit is constituted, which constitutes digit time converting unit with the switching group.
3. time-to-digit converter according to claim 2, which is characterized in that be connected with one in the output end of the delay chain
Counter, the counter are triggered by Reset signal rising edges, while all in the Reset signals rising edge reset delay chain
Delay cell, counter records delay chain are the number of all one state, and then improve the input time amount of the time-to-digit converter
Journey range.
4. time-to-digit converter according to claim 1, which is characterized in that the digit time converting unit is connected with
Switch control signal Dout, switch control signal Dout carry out digital quantization with the time-to-digital converter unit to the time
Export result D0, D1 ..., the relationship between D6 it is as shown in the table：
1 TDC control word truth tables of table
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| CN107272395B (en) * | 2017-08-03 | 2018-06-19 | 睿力集成电路有限公司 | Time-to-digit converter and its conversion method |
| CN108549205B (en) * | 2018-04-12 | 2020-08-04 | 中国科学院微电子研究所 | Two-step time-to-digital converter based on time amplifier |
| CN110764395A (en) * | 2018-07-25 | 2020-02-07 | 苏州超锐微电子有限公司 | Annular time-to-digital conversion circuit applied to SPAD detector |
| EP3828647B1 (en) * | 2019-03-18 | 2023-01-25 | Shenzhen Goodix Technology Co., Ltd. | Time-to-digital conversion circuit and related method |
| CN110262209B (en) * | 2019-06-03 | 2020-06-26 | 中国科学技术大学 | Time-to-digital converter based on FPGA |
| CN110824889B (en) * | 2019-11-08 | 2021-05-28 | 中山大学 | Time-to-digital converter based on novel time amplifier |
| CN111025884B (en) * | 2019-12-08 | 2021-10-26 | 复旦大学 | Two-step high-speed dynamic time-to-digital converter |
| CN112445121B (en) * | 2021-02-01 | 2021-04-16 | 南京邮电大学 | Time register and time domain operation circuit for time-digital converter |
| WO2023283951A1 (en) * | 2021-07-16 | 2023-01-19 | 深圳市速腾聚创科技有限公司 | Time-of-flight measurement method, circuit, apparatus, storage medium and electronic device |
| CN117092444B (en) * | 2023-10-19 | 2023-12-29 | 成都电科星拓科技有限公司 | Method, system, equipment and medium for indirectly measuring DTC stepping without depending on instrument |
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| WO2001069328A2 (en) * | 2000-03-17 | 2001-09-20 | Vector 12 Corporation | High resolution time-to-digital converter |
| CN201583811U (en) * | 2009-10-15 | 2010-09-15 | 山东力创赢芯集成电路有限公司 | Time-to-digital converter with temperature measurement and driving functions |
| CN103092059B (en) * | 2012-12-24 | 2015-05-27 | 中国科学技术大学 | Time digital converter based on antifuse field programmable gata array (FPGA) and temperature drift correcting method thereof |
| US8957712B2 (en) * | 2013-03-15 | 2015-02-17 | Qualcomm Incorporated | Mixed signal TDC with embedded T2V ADC |
| CN103532559B (en) * | 2013-10-22 | 2016-05-04 | 天津大学 | Circulation timei digital quantizer |
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2016
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