CN110729354A - Silicon carbide transverse MOSFET device and preparation method thereof - Google Patents
Silicon carbide transverse MOSFET device and preparation method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 51
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 51
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 239000000377 silicon dioxide Substances 0.000 claims description 16
- 238000004140 cleaning Methods 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 8
- 229910052906 cristobalite Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229910052682 stishovite Inorganic materials 0.000 claims description 8
- 229910052905 tridymite Inorganic materials 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 4
- 238000005406 washing Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
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Abstract
The invention relates to the field of semiconductor devices, and discloses a silicon carbide transverse MOSFET device and a preparation method thereof. And an N-type source region and an N-type RESURF region are arranged on two sides of the top of the P-drift region, an N + type source contact region is arranged above the N-type source region, and an N + type drain contact region is arranged above the N-type RESURF region. And a gate dielectric layer is covered on the exposed P-type drift region between the N-type source region and the N-type RESURF region. The gate dielectric layer transversely extends to cover the N-type RESURF region, a gate electrode is arranged on the gate dielectric layer, a source electrode is arranged on the N + type source contact region 7, and a drain electrode is arranged on the N + type drain contact region. The device has no ion implantation area, thereby greatly reducing the cost of the device and improving the yield of the device. The device is in a transverse device structure, and integration is convenient to realize. The invention also provides a preparation method of the silicon carbide transverse MOSFET device.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a silicon carbide transverse MOSFET device for integration.
Background
Due to the excellent material characteristics, silicon carbide power devices are playing more and more important roles in the fields of power electronics, new energy automobiles, photovoltaics and the like. The development of discrete silicon carbide devices has often led to the accumulation of many process and reliability achievements and experiences that in turn have been used in the development of integrated circuits. With the continuous progress of silicon carbide substrates and epitaxial technologies, it has become possible to fabricate silicon carbide-based power integrated circuits with superior performance.
The basis of the development of silicon-based power integrated circuits is the innovation of the invention and the process of the basic components of the integrated circuits. Due to the advantages of high reliability, low driving difficulty and the like, the most commonly used power MOS device in the silicon-based power integrated circuit is an LDMOS device. A lateral MOSFET structure that is simple, reliable, and compatible with existing discrete silicon carbide vertical devices is critical to the development of silicon carbide power integrated circuits.
Disclosure of Invention
Technical problem to be solved
The invention aims to provide a silicon carbide transverse MOSFET device structure suitable for monolithic integration and a preparation method thereof aiming at the characteristics of silicon carbide materials. The novel silicon carbide transverse MOSFET device has a high quality factor and good performance. And the process does not need an ion implantation process, thereby greatly reducing the device cost.
(II) technical scheme
The technical scheme of the invention comprehensively considers the aspects of material characteristics, process difficulty, device performance, cost and the like, and provides the silicon carbide transverse MOSFET device structure. The structure comprises an N + type high-doped substrate, a P + type isolation layer and a P-type drift region, wherein the P + type isolation layer and the P-type drift region are sequentially arranged on the N + type high-doped substrate; an N-type source region and an N-type RESURF region are arranged on two sides of the top of the P-type drift region; an N + type source contact region is arranged above the N type source region, and an N + type drain contact region is arranged above the N type RESURF region; a gate dielectric layer covers the exposed P-type drift region between the N-type source region and the N-type RESURF region, and the gate dielectric layer transversely extends to cover the N-type RESURF region; and a grid electrode is arranged above the grid dielectric layer, a source electrode is arranged above the N + type source contact region, and a drain electrode is arranged above the N + type drain contact region.
Preferably, the thickness of the P + type isolation layer is 0.5-2 μm, and the doping concentration is 5 x 1017cm-3-1×1019cm-3(ii) a The thickness of the P-type drift region is 4-20 μm, and the doping concentration is 5 × 1016cm-3-5×1017cm-3。
Preferably, the N-type source region and the N-type RESURF region are made of the same material, the thickness of the N-type source region and the thickness of the N-type RESURF region are 0.2-0.6 mu m, and the doping concentration of the N-type source region and the doping concentration of the N-type RESURF region are 1 multiplied by 1017cm-3To 1X 1018cm-3(ii) a The N + type source contact region and the N + type drain contact region are made of the same material, the thickness of the N + type source contact region and the N + type drain contact region is 0.2-0.5 mu m, and the doping concentration of the N + type source contact region and the N + type drain contact region is 1 multiplied by 1018cm-3To 2X 1019cm-3。
Preferably, the gate dielectric layer is SiO2The thickness of the material is 30nm-60 nm.
Preferably, the gate is N-type doped polysilicon; the source electrode and the drain electrode are made of metal nickel and have the thickness of 100 nm.
In another aspect of the invention, a method for preparing the silicon carbide lateral MOSFET device is provided, which comprises the following steps:
s1: sequentially growing a P + type isolation layer, a P-type drift region, an N type layer and an N + type layer on an N + type highly doped substrate;
s2: etching the N + type layer to the N type layer to form an N + type source contact region and an N + type drain contact region;
s3: etching the N-type layer to the surface of the P-drift region, and dividing the N-type layer into an N-type source region and an N-type RESURF region;
s4: after cleaning, oxidizing or depositing a gate dielectric, and annealing to reduce a surface state;
s5: depositing grid polysilicon, and flattening the CMP surface;
s6: and stripping the source drain metal.
Preferably, the step S2 includes:
s2.1, depositing a layer of SiO with the thickness of 1 mu m on the surface of the N + type layer after cleaning2；
S2.2 coating photoresist, photoetching and developing, etching SiO with the photoresist as a mask2Forming an etching mask of the silicon carbide;
s2.3 with the SiO2Etching silicon carbide to the surface of an N-type layer by using the silicon carbide as a mask, and dividing the N + type layer into an N + type source contact region and an N + type drain contact region;
and S2.4, oxidizing for 30 minutes at 1200 ℃, and washing away a surface oxidation layer and an etching damage layer by using a BOE solution.
Preferably, the step S3 includes:
s3.1, depositing a layer of SiO with the thickness of 1 mu m on the surface of the N-type layer after cleaning2Etching SiO with photoresist as mask after photoresist coating, photoetching and developing2；
S3.2 cleaning, then using SiO2Etching silicon carbide to the surface of the P-drift region by using the silicon carbide as a mask, and dividing the N-type layer into an N-type region and an N-type RESURF region;
and S3.3, after cleaning, oxidizing for 30 minutes at 1200 ℃, and washing away a surface oxidation layer and an etching damage layer by using a BOE solution.
Preferably, the step S4 includes:
after S4.1 cleaning, SiO was deposited to a thickness of 35nm using ALD2Dry oxygen oxidation at 1250 ℃ for 10 minutes in H2Annealing in situ for 30 minutes at 1250 ℃ in the environment;
s4.2 annealing is continued for 2 hours in an NO environment, and the NO annealing temperature is 1275 ℃.
(III) advantageous effects
The invention designs a silicon carbide transverse MOSFET device structure which is completely compatible with the existing silicon carbide vertical structure process, adopts a commercialized silicon carbide N + substrate, has lower cost and is very convenient to be used as a basic component of a silicon carbide integrated circuit. Ion implantation and high-temperature annealing activation ion implantation are not needed in the device preparation process, so that the device has lower process cost and yield. The device is in a transverse device structure, and integration is convenient to realize.
Drawings
FIG. 1 is a block diagram of a lateral MOSFET device of silicon carbide in accordance with the present invention;
FIG. 2 is a process flow diagram of a silicon carbide lateral MOSFET device of the present invention;
FIG. 3 is a schematic diagram of a device manufacturing process step S1 according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a device manufacturing process step S2 according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a device manufacturing process step S3 according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a device manufacturing process step S4 according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a device manufacturing process step S5 according to an embodiment of the present invention.
The transistor comprises an N + type highly doped substrate 1, a P + type isolation layer 2, a P-type drift region 3, an N-type RESURF region 4, an N-type source region 5, an N + type source contact region 7, an N + type drain contact region 8, a gate dielectric layer 9, a gate electrode 10, a source electrode 11 and a drain electrode 12
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
In one aspect of the embodiments of the present invention, a silicon carbide lateral MOSFET structure is provided, and fig. 1 is a schematic structural diagram of a silicon carbide lateral MOSFET device according to the present invention. As shown in fig. 1, the structure comprises an N + type highly doped substrate 1, on which a P + type epitaxial buried isolation layer 2 and a P-type drift region 3 are sequentially formed. An N-type source region 5 and an N-type RESURF region 4 are arranged on two sides of the top of the P-drift region 3, an N + type source contact region 7 is arranged above the N-type source region 5, and an N + type drain contact region 8 is arranged above the N-type RESURF region 4. A gate dielectric layer 9 covers the exposed P-type drift region 3 between the N-type source region 5 and the N-type RESURF region 4, the gate dielectric layer 9 transversely extends to cover the N-type RESURF region 4, a gate electrode 10 is arranged on the gate dielectric layer 9, a source electrode 11 is arranged on the N + type source contact region 7, and a drain electrode 12 is arranged on the N + type drain contact region 8.
In the embodiment of the invention, preferably, the thickness of the P + -type epitaxial isolation buried layer is 0.5 μm to 2 μm, and the doping concentration is 5 × 1017cm-3To 1X 1019cm-3. The thickness of the P-drift region is 4-20 μm, and the doping concentration is 5 × 1016cm-3To 5X 1017cm-3。
In the embodiment of the present invention, preferably, the N-type source region 5 and the N-type RESURF region 4 are prepared from the same epitaxial layer, and have a thickness of 0.2 μm to 0.6 μm and a doping concentration of 1 × 1017cm-3To 1X 1018cm-3. The N + type source contact region 7 and the N + type drain contact region 8 are prepared from the same epitaxial layer, the thickness is 0.2-0.5 mu m, and the doping concentration is 1 multiplied by 1018cm-3To 2X 1019cm-3。
In the embodiment of the present invention, preferably, the gate dielectric layer 9 is SiO2Material with a thickness of 30nm to 60 nm. The gate 10 is N-type doped polysilicon, and the source electrode 11 and the drain electrode 12 are made of metal Ni and have a thickness of 100 nm.
In another aspect of the embodiments of the present invention, a method for manufacturing the silicon carbide LDMOS device is provided, which includes the following steps:
step S1: sequentially growing a P + type isolation layer, a P-type drift region, an N type layer and an N + type layer on an N + type silicon carbide substrate;
as shown in fig. 3, a P + -type isolation layer 2, a P-type drift region 3, an N-type layer 4 and an N + -type layer 5 are sequentially grown on an N + -type silicon carbide substrate 1.
Step S2: etching the surface of the silicon carbide to the N-type layer to form an N + source contact region and an N + drain contact region;
after cleaning the surface of the epitaxial wafer, a layer of silicon dioxide with a thickness of 1 μm was deposited on the silicon carbide surface, as shown in fig. 4. And after the photoresist is coated, photoetching and developing, etching the silicon dioxide by taking the photoresist as a mask to form an etching mask of the silicon carbide. And after the silicon dioxide etching is finished, etching the silicon carbide to the surface of the N + type layer 4 by using the silicon dioxide as a mask, and dividing the N + type layer 5 into an N + type source contact region 7 and an N + type drain contact region 8. After the wafer was cleaned again, oxidation was performed at 1200 ℃ for 30 minutes, and the surface oxide layer and the etching damage layer were washed away with a BOE solution.
Step S3: etching the silicon carbide to the surface of the P-drift region 3, and dividing the N-type layer into an N-type source region 5 and an N-type RESURF region 4;
as shown in fig. 5, the surface of the epitaxial wafer is cleaned again, a layer of silicon dioxide with the thickness of 1 μm is deposited on the surface of the silicon carbide, and after photoresist is used as a mask, the silicon dioxide is etched. And after etching is finished, etching the silicon carbide to the surface of the P-drift region 3 by using silicon dioxide as a mask, and dividing the N-type layer 4 into an N-type region 5 and an N-type RESURF region 4. After the wafer was cleaned again, oxidation was performed at 1200 ℃ for 30 minutes, and the surface oxide layer and the etching damage layer were washed away with a BOE solution.
Step S4: cleaning the surface of a wafer, oxidizing or depositing a gate dielectric, and annealing to reduce the surface state;
as shown in fig. 6, the surface of the epitaxial wafer was cleaned again, SiO2 was deposited using ALD to a thickness of 35nm, followed by dry oxygen oxidation at 1250 ℃ for 10 minutes, in-situ annealing at 1250 ℃ for 30 minutes in an H2 ambient, followed by annealing at 1250 ℃ for 2 hours in an NO ambient, followed by an NO anneal at 1275 ℃.
Step S5: depositing grid polysilicon, and flattening the CMP surface;
as shown in fig. 7, polysilicon is deposited using PECVD to fill the etched trenches. And then, carrying out N-type doping on the polysilicon by adopting a two-step diffusion method. After doping is complete, the device surface is planarized using CMP and the wafer surface is cleaned.
Step S6: and stripping the source and drain metal, and performing contact annealing to form an electrode.
And after gluing, photoetching and developing, carrying out wet etching on the silicon dioxide by using a BOE solution, and opening source and drain contact windows. Baking to harden the film, evaporating 100nm metal Ni, soaking in acetone solution, and ultrasonically stripping the metal Ni. And then performing rapid thermal annealing at 975 ℃ for 1 minute and 30 seconds to form a source electrode 11 and a drain electrode 12 of the device. A lateral MOSFET device of silicon carbide is finally formed as shown in fig. 1.
The above-mentioned embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above-mentioned embodiments are only examples of the present invention and are not intended to limit the present invention. It is within the spirit and scope of the present invention to change the thickness or doping concentration of a region, and to change the metal material selected for the gate dielectric layer and the ohmic contact.
Claims (9)
1. A silicon carbide lateral MOSFET device, characterized by: comprises an N + type highly doped substrate, a P + type isolation layer and a P-type drift region sequentially arranged on the N + type highly doped substrate; an N-type source region and an N-type RESURF region are arranged on two sides of the top of the P-type drift region; an N + type source contact region is arranged above the N type source region, and an N + type drain contact region is arranged above the N type RESURF region; a gate dielectric layer covers the exposed P-type drift region between the N-type source region and the N-type RESURF region, and the gate dielectric layer transversely extends to cover the N-type RESURF region; and a grid electrode is arranged above the grid dielectric layer, a source electrode is arranged above the N + type source contact region, and a drain electrode is arranged above the N + type drain contact region.
2. The silicon carbide lateral MOSFET device of claim 1, wherein: the thickness of the P + type isolation layer is 0.5-2 μm, and the doping concentration is 5 multiplied by 1017cm-3-1×1019cm-3(ii) a The thickness of the P-type drift region is 4-20 μm, and the doping concentration is 5 × 1016cm-3-5×1017cm-3。
3. The silicon carbide lateral MOSFET device of claim 1, wherein: the N-type source region and the N-type RESURF region are made of the same material, the thickness of the N-type source region and the N-type RESURF region is 0.2-0.6 mu m, and the doping concentration of the N-type source region and the N-type RESURF region is 1 multiplied by 1017cm-3To 1X 1018cm-3(ii) a The N + type source contact region and the N + type drain contact region are made of the same material, the thickness of the N + type source contact region and the N + type drain contact region is 0.2-0.5 mu m, and the doping concentration of the N + type source contact region and the N + type drain contact region is 1 multiplied by 1018cm-3To 2X 1019cm-3。
4. The silicon carbide lateral MOSFET device of claim 1, wherein: the gridThe dielectric layer is SiO2The thickness of the material is 30nm-60 nm.
5. The silicon carbide lateral MOSFET device of claim 1, wherein: the grid electrode is N-type doped polycrystalline silicon; the source electrode and the drain electrode are made of metal nickel and have the thickness of 100 nm.
6. A preparation method of a silicon carbide transverse MOSFET device is characterized by comprising the following steps:
s1: sequentially growing a P + type isolation layer, a P-type drift region, an N type layer and an N + type layer on an N + type highly doped substrate;
s2: etching the N + type layer to the N type layer to form an N + type source contact region and an N + type drain contact region;
s3: etching the N-type layer to the surface of the P-drift region, and dividing the N-type layer into an N-type source region and an N-type RESURF region;
s4: after cleaning, oxidizing or depositing a gate dielectric, and annealing to reduce a surface state;
s5: depositing grid polysilicon, and flattening the CMP surface;
s6: and stripping the source drain metal.
7. The method of claim 6, wherein the step S2 includes:
s2.1, depositing a layer of SiO with the thickness of 1 mu m on the surface of the N + type layer after cleaning2；
S2.2 coating photoresist, photoetching and developing, etching SiO with the photoresist as a mask2Forming an etching mask of the silicon carbide;
s2.3 with the SiO2Etching silicon carbide to the surface of an N-type layer by using the silicon carbide as a mask, and dividing the N + type layer into an N + type source contact region and an N + type drain contact region;
and S2.4, oxidizing for 30 minutes at 1200 ℃, and washing away a surface oxidation layer and an etching damage layer by using a BOE solution.
8. The method of claim 6, wherein the step S3 includes:
s3.1, depositing a layer of SiO with the thickness of 1 mu m on the surface of the N-type layer after cleaning2Etching SiO with photoresist as mask after photoresist coating, photoetching and developing2；
S3.2 cleaning, then using SiO2Etching silicon carbide to the surface of the P-drift region by using the silicon carbide as a mask, and dividing the N-type layer into an N-type region and an N-type RESURF region;
and S3.3, after cleaning, oxidizing for 30 minutes at 1200 ℃, and washing away a surface oxidation layer and an etching damage layer by using a BOE solution.
9. The method of claim 6, wherein the step S4 includes:
after S4.1 cleaning, SiO was deposited to a thickness of 35nm using ALD2Dry oxygen oxidation at 1250 ℃ for 10 minutes in H2Annealing in situ for 30 minutes at 1250 ℃ in the environment;
s4.2 annealing is continued for 2 hours in an NO environment, and the NO annealing temperature is 1275 ℃.
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