CN110690123B - 具有裸片附接焊盘锁定特征的热无引线阵列封装 - Google Patents
具有裸片附接焊盘锁定特征的热无引线阵列封装 Download PDFInfo
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Abstract
本发明的实施例是针对于一种具有裸片附接焊盘锁定特征的热无引线阵列封装及其制造方法。对铜层的两个表面进行半蚀刻以界定封装接触阵列和裸片附接焊盘。为了实现更佳的可靠性,将每个裸片附接焊盘完全嵌入密封材料以提供良好的机械锁定特征。在一些实施例中,所述接触包括四个有源拐角接触。
Description
本申请是于2013年7月3日向中国国家专利局提出、申请号为201310283598.5、发明名称为“具有裸片附接焊盘锁定特征的热无引线阵列封装”的中国发明专利申请的分案申请。
技术领域
本发明涉及半导体器件制造领域,尤其涉及一种具有裸片附接焊盘锁定特征的热无引线阵列封装及其制造方法。
背景技术
热无引线阵列(TLA)封装的当前工艺和技术可生产这样的结构特征,其中裸片附接焊盘(DAP)仅部分地嵌入模塑料以充当对抗由于封装内的各种组件之间的热膨胀系数(CTE)失配所引起的热应力和机械应力的机械锁定特征。通常,各种组件之间的剪应力能够在环境应变或插板级可靠性测试的过程中导致故障。对于具有较大裸片-DAP面积比(通常为85%或更大)的封装,尤为如此。授予Fan等人的美国专利第7,049,177号中公开了一种用于形成TLA封装的现有工艺。Fan讲授了一种涉及双半蚀刻步骤的形成TLA封装的工艺。然而,由于DAP和接触两者仅部分地嵌入用于机械锁定的模塑料这一事实,所以此工艺具有缺陷。图1示出现有技术中的多行无引线封装的侧视图。现有技术的半导体封装100包括裸片附接焊盘105、接触110、安装在裸片附接焊盘105上的IC芯片115以及用于将芯片115键合到接触110的键合线125。模塑料120密封键合线125和IC芯片115。接触110和裸片附接焊盘105非完全嵌入模塑料120并且从模塑料120的底部突出。与其中接触和DAP完全嵌入(仅暴露单个面以用于连接和热转移)的标准QFN封装相比,TLA的可靠性性能较不强健。
授予McLellan等人的美国专利第6,498,099号中公开了一种方案。McLellan讲授了在牺牲载体上堆积的金属,其中在密封之后蚀刻去除牺牲载体。堆积过程中使用的方法导致作为锁定特征的具有蘑菇形轮廓的DAP和引线。然而,金属堆积工艺的耗时较长,因此无价格竞争性。
授予Fan等人的美国专利第7,033,517号和授予Fan等人的美国专利第7,247,526号中描述了其它方案。在这些文献中,将两个金属箔(即,引线框条带和载体条带)层压在一起,并且随后在密封之后将其分离。对引线框条带首先进行图案化,并且在将一个表面层压到载体条带上之前,对所述相同的表面进行半蚀刻。对引线框条带的非图案化侧进行图案化并且蚀刻以完全界定单个I/O引线和DAP。在装配和密封之后,使用加热工艺移除载体条带。所得结构具有完全嵌入的DAP,但是不提供类似TLA的有托脚引线以便于焊接和安装到PCB。
此外,对于具有从DAP向封装引线框的四个拐角接触焊盘延伸的嵌入式联结杆(tie bar)的标准单行QFN封装,存在缺点。通常,在装配过程之后,留下这些联结杆。不幸地,在装配工艺之后所留下的这些联结杆占据了有价值的占用面积(footprint)空间。图4示出现有技术中的单行无引线封装的底视图。如所示,围绕裸片附接焊盘415存在32个接触,其中8个接触405暴露于侧面。然而,封装400的拐角410处的有价值的占用面积空间保持未被使用。
本发明至少解决现有技术中的这些限制。
发明内容
本发明的实施例是针对于一种具有裸片附接焊盘锁定特征的热无引线阵列封装及其制造方法。对铜层的两个表面进行半蚀刻以界定封装接触阵列和裸片附接焊盘。为了更佳的可靠性,将每个裸片附接焊盘完全嵌入密封材料以提供良好的机械锁定特征。对引线框的顶面执行第一半蚀刻以形成接触和裸片附接焊盘。对于此文献,顶面意欲表示附接半导体裸片的表面,而非基本方向。对裸片附接焊盘的边缘与最近的一行接触之间的引线框的底面执行第二半蚀刻。除支撑结构(例如,联结杆)之外,将此区域蚀穿。在一些实施例中,每个联结杆大体上处于裸片附接焊盘的每个侧面的中心。替代地,每个联结杆大体上处于裸片附接焊盘的拐角。接着,可将此单层引线框基板用于装配无引线半导体封装。可使用标准QFN工艺和装备完成封装装配工艺的其它步骤(例如,裸片附接、引线键合、模制、标记和/或条带测试(strip testing))。以条带形执行回蚀以界定各个接触并将其彼此隔离并且将其与裸片附接焊盘隔离。
在一个方面,一种半导体封装包括裸片附接焊盘、多个接触、安装在所述裸片附接焊盘的内表面上的半导体裸片、将所述半导体裸片耦合到所述多个接触的键合线以及模塑料。所述裸片附接焊盘通常包括内表面和暴露表面。所述多个接触通常包括更接近所述裸片附接焊盘的内接触。所述模塑料通常包括第一底面,其从所述裸片附接焊盘的所述暴露表面向所述内接触延伸。在一些实施例中,所述模塑料的第一底面到达所述内接触。替代地,所述模塑料的第一底面不到达所述内接触。将所述裸片附接焊盘嵌入所述模塑料,从而使所述第一底面与所述裸片附接焊盘的暴露表面、所述接触的底面或两者共面。所述模塑料的第一底面至少部分地与所述裸片附接焊盘外切。所述模塑料还可包括第二底面,其通常相对于所述裸片附接焊盘的暴露表面、所述接触的底面或两者凹陷。所述裸片附接焊盘的第一和第二底面之间的过渡被称为半导体封装的梯级特征。所述梯级特征可出现在内接触之前或内接触的边缘处。
在一些实施例中,所述模塑料的第一底面从所述裸片附接焊盘延伸到达所述内接触,并且与所述裸片附接焊盘的暴露表面和/或所述内接触的底面共面。所述裸片附接焊盘和所述内接触之间的模塑料包括出现在内接触的边缘处的梯级特征。
替代地,所述模塑料的第一底面从所述裸片附接焊盘延伸,但是不到达所述内接触,从而在所述模塑料的第一底面和所述内接触的底面之间留下间隙。所述裸片附接焊盘和所述内接触之间的模塑料包括出现在所述内接触之前的梯级特征。
在一些实施例中,所述内接触部分地密封。在一些实施例中,所述多个接触从所述模塑料突出。在一些实施例中,所述裸片附接焊盘和所述多个接触焊盘具有啮合特征。在一些实施例中,所述多个接触包括有源的拐角接触。
在另一方面,提供一种针对于制造半导体封装的方法。其中,蚀刻引线框以形成多个联结杆、多个接触和通过所述多个联结杆耦合到所述多个接触的一部分的裸片附接焊盘,并且形成通过所述引线框进行蚀刻的围绕所述裸片附接焊盘的多个区域。在一些实施例中,选择性地镀覆所述引线框的顶面,并且将所述引线框的底面与胶带(tape)层压。可以Ag,Ni、Pd和Au的叠层,NiPdAu合金,NiAu或NiAu合金或其它适当的镀覆材料对所述顶面进行镀覆。接着,制备半导体封装。通常,将裸片耦合到裸片附接焊盘,将裸片上的键合焊盘接线键合到所述多个接触。接着,对所述裸片附接焊盘、所述多个接触、所述裸片和键合线进行密封。在一些实施例中,在制备所述封装之后,将所述胶带从所述引线框的底面移除。进一步蚀刻所述引线框的底面以将所述多个接触与所述裸片附接焊盘隔离。在一些实施例中,将可焊接材料涂覆到述引线框的底面。可焊接材料为Sn、NiAu、NiPdAu、Ag、SnPb、SnAgCu、SnAgCuNi、无铅合成物或其它适当的材料。接着,对所述半导体封装进行单片化。
在一些实施例中,将所述裸片附接焊盘嵌入模塑料,从而使所述裸片附接焊盘的暴露表面处于所述半导体封装的底部,并且所述裸片附接焊盘和最接近所述裸片附接焊盘的接触之间的模塑料从所述裸片附接焊盘的暴露表面向所述接触延伸。所述裸片附接焊盘和接近所述裸片附接焊盘的接触之间的模塑料包括梯级特征,其为所述模塑料的第一底面和第二底面之间的过渡。所述梯级特征出现在接近所述裸片附接焊盘的接触的边缘之前或出现在接近所述裸片附接焊盘的接触的边缘处。
在一些实施例中,每个联结杆从所述裸片附接焊盘的拐角延伸,并且其中,在蚀刻所述底面之后,所述多个接触包括有源的拐角接触。在一些实施例中,所有的接触均未暴露于所述半导体封装的侧面。替代地,所述接触中的全部或部分暴露于所述半导体封装的侧面。
附图说明
本发明的新颖特征在所附权利要求中阐述。然而,为了说明的目的,在以下附图中阐述本发明的若干实施例。
图1示出现有技术中的多行无引线封装的侧视图。
图2A示出根据本发明的改进型多行无引线封装的侧视图。
图2B-2F示出根据本发明的制造图2A的改进型多行无引线封装的处理步骤。
图3A-3C示出根据本发明的另一改进型多行无引线封装以及制造所述改进型多行无引线封装的所选处理步骤。
图4示出现有技术中的单行无引线封装的底视图。
图5A示出根据本发明的改进型单行无引线封装的底视图。
图5B-5F示出根据本发明的制造图5A的改进型单行无引线封装的处理步骤。
具体实施方式
在下列描述中,为了解释的目的,陈述了大量的细节。然而,本领域的普通技术人员可在不使用这些具体细节的情况下实践本发明。因此,本发明非意欲局限于所示的实施例,而是符合与本文所描述原理和特点或其等效替代相一致的最广范围。
现将详细参考附图所示的本发明的实施。在整个附图和下列详细描述中,将使用相同的参考指示符来表示相同的或类似的部件。
本发明的实施例是针对于一种具有裸片附接焊盘锁定特征的热无引线阵列封装及其制造方法。其中,对铜层的两个表面进行半蚀刻以界定封装接触阵列和裸片附接焊盘。为了更佳的可靠性,将每个裸片附接焊盘完全嵌入密封材料以提供良好的机械锁定特征。对引线框的顶面执行第一半蚀刻以形成接触和裸片附接焊盘。对引线框的底面执行第二半蚀刻,其中所述底面包括介于裸片附接焊盘的边缘与最近的一行接触之间的区域。除支撑结构(例如,联结杆)之外,将这些区域蚀穿。在一些实施例中,每个联结杆大体上处于裸片附接焊盘的每个侧面的中心。替代地,每个联结杆可处于裸片附接焊盘的拐角处。接着,可将此单层引线框用于装配无引线半导体封装。可使用标准QFN工艺和装备完成封装装配工艺的其它步骤(例如,裸片附接、引线键合、模制、标记和/或条带测试)。以条带形执行回蚀以界定各个接触并将其彼此隔离并且将其与裸片附接焊盘隔离。在一些实施例中,可如此形成四个有源拐角接触。
改进型多行QFN封装
图2A示出根据本发明的改进型多行无引线封装的侧视图。半导体封装200包括裸片附接焊盘205、接触210、安装在裸片附接焊盘205上的IC芯片215以及用于将芯片215键合到接触210的键合线225。模塑料220密封键合线225和IC芯片215。裸片附接焊盘205完全嵌入模塑料220的底部,并且不会从模塑料220的底部突出。优选地,裸片附接焊盘205仅暴露于单个表面,具体地说,暴露于封装200的底部。为了获得更佳的机械锁定特征,裸片附接焊盘205的暴露表面通常与模塑料220的第一底面齐平或共面。模塑料220的第一底面从裸片附接焊盘205的暴露表面向接触210延伸。如所示,优选地,裸片附接焊盘205和接触210位于相同的平面上。
接触的一部分包括围绕裸片附接焊盘205的内接触。内接触为靠近或接近裸片附接焊盘205的那些接触。如图2A所示,优选地,裸片附接焊盘205和内接触之间的模塑料、裸片附接焊盘205和内接触的底面均共面。优选地,接触210中的任一个都不暴露于半导体封装200的侧面。在一些实施例中,如图2A所示,在更接近裸片附接焊盘205的有托脚表面的侧面上,内接触被部分地密封;而所有的其它接触(例如,外接触)均从模塑料220完全突出一定的距离。模塑料220的第一底面从裸片附接焊盘205延伸并且到达内接触。梯级特征出现在内接触的边缘,其中模塑料220的第一底面过渡到模塑料220的第二底面。
替代地,如图3A所示,裸片附接焊盘205和内接触之间的模塑料220'可包括梯级特征285以便于焊接和安装到印刷电路板,其中梯级特征285为邻近内接触的缺口。梯级特征285形成模塑料220'的第二底面。模塑料220'的第一底面从裸片附接焊盘205延伸,但是不到达内接触。替代地,模塑料220'的第二底面从内接触向裸片附接焊盘205的暴露表面延伸。模塑料220'的第一底面和模塑料220’的第二底面会合以形成梯级特征285。梯级特征285出现在内接触之前。模塑料220'的第二底面通常相对于裸片附接焊盘205和内接触的底面凹陷。在本实施例中,所有的接触210在其有托脚表面均未被密封。替代地,接触210从模塑料220'向外突出一定的距离。
图2B-2F示出根据本发明的制造图2A的改进型多行无引线封装200的处理步骤。具体地,图2B示出根据本发明的制造图2A的改进型多行无引线封装200的方法,而图2C-2F示出通过图2B所示方法的每个步骤制造的例示性结果。
如图2B所示,方法230开始于步骤235,其中提供金属条带。优选地,由一片裸铜或一些其它金属,例如合金42,形成金属层。图2C-2E仅示出金属条带内的一个单元。这些单元在金属条带内通常以阵列格式排列。
在步骤240,使用例如光致抗蚀剂(PR)掩模选择性地半蚀刻金属条带的顶面。PR掩模可防止金属条带上的区域被蚀刻掉。通常,基于特定的用户设计对顶面进行蚀刻。在图2C中,以灰色的淡影示出蚀刻的区域。在金属条带内所有的单元上同时执行此步骤和随后的步骤。
在步骤245,围绕裸片附接焊盘的周边,使用例如PR掩模,选择性地半蚀刻金属条带的底面。在一些实施例中,此半蚀刻区域覆盖金属条带顶面上的初始半蚀刻图案化以形成围绕裸片附接焊盘的周边的蚀穿区域和用于将裸片附接焊盘固定到引线框的联结杆。在一些实施例中,形成最少四个联结杆,其中每个联结杆固定四边形裸片附接焊盘的一侧。在密封过程中,蚀穿区域可有利地使模塑料从引线框的顶部到达其底部并且围绕裸片附接焊盘的侧面。
在一些实施例中,如图2A所示,蚀穿区域从裸片附接焊盘向内接触延伸,其导致内接触在其有托脚表面的侧面部分地密封。这些蚀穿区域在内接触的边缘创建梯级特征。替代地,如图3B所示,蚀穿区域窄于图2C所示的蚀穿区域。这些较窄的蚀穿区域在内接触之前创建梯级特征,其导致内接触完全突出模塑料,如图3A所示。
在一些实施例中,同时执行步骤240和步骤245。具体地,将PR掩模涂覆到引线框的两侧,并且同时蚀刻引线框的两侧。此被称为单步骤蚀刻。
在一些实施例中,替代执行步骤245,可将PR掩模涂覆到顶面,并且再次选择性地蚀刻所述顶侧以创建围绕裸片附接焊盘的穿孔。因此,无需底面部分蚀刻。
在步骤250,为接触和/或裸片附接焊盘选择性地镀覆金属条带的顶面。在一些实施例中,镀覆包含Ni、Pd和Au。然而,普通的技术人员将认识到,可设想其它镀覆,例如NiPdAu合金、NiAu或NiAu合金。接触上的镀覆是用于键合线。裸片附接焊盘上的镀覆材料是可选的,因为对于无向下键合的设计而言裸片附接焊盘可为裸铜;或者,为了向下键合目的,裸片附接焊盘可被完全镀覆或选择性地镀覆(例如,在裸片附接焊盘的***区域)。这些均基于特定的用户设计。
在步骤255,对金属条带的底面进行胶带层压以防止模塑料通过围绕裸片附接焊盘周边的蚀穿区域或开放“通孔”从金属条带下方渗出。
在步骤260,制备或装配半导体封装。制备半导体封装包括:将IC芯片附接到裸片附接焊盘,引线键合,模制,模制后固化,激光标记以及可选的条带测试。
在步骤265,通过在模塑工艺之后从金属条带的底面剥离,移除胶带。
在步骤270,使用例如PR掩模选择性地蚀刻底面以暴露并界定接触和裸片附接焊盘。其后,通常将接触彼此电隔离并且与裸片附接焊盘电隔离。若需要,由于此隔离,可以按照条带形对所述单元进行电测试。
在步骤275,可将可焊接材料涂覆到底面。在一些实施例中,以锡、焊料、NiAu、NiPdAu、Ag或其它用于印刷电路板安装目的的可焊接材料对底面上暴露的接触和裸片附接焊盘进行选择性地镀覆。焊料膏涂层或焊料球施加也是适合的选项。
在步骤280,对封装进行单片化。将条带内的器件彼此单片化以形成各个成品器件。使用高速锯、激光、高压喷水器或一些其它适当的装置执行单片化。图2F示出半导体器件200的单片化,而图3C示出半导体器件200'的单片化。在步骤280之后,过程230结束。
图2A示出单片化后的半导体器件200。如上文所论述,封装后的半导体封装200包括裸片附接焊盘205、接触210、安装在裸片附接焊盘205的内表面上的IC芯片215以及用于将芯片215键合到接触210的键合线225。模塑料220密封键合线225和IC芯片215。裸片附接焊盘205完全嵌入模塑料220的底部,并且不会从模塑料220的底部突出。裸片附接焊盘205包括位于封装200的底部的暴露表面。裸片附接焊盘205的暴露表面通常与模塑料220的第一底面齐平或共面。模塑料220的第一底面从裸片附接焊盘205的暴露表面向内接触延伸并且到达内接触。梯级特征出现在内接触的边缘,其中模塑料220的第一底面过渡到模塑料220的第二底面。
图3A示出单片化后的半导体器件200'。如上文所论述,封装后的半导体封装200'包括裸片附接焊盘205、接触210、安装在裸片附接焊盘205的内表面上的IC芯片215以及用于将芯片215键合到接触210的键合线225。模塑料220'密封键合线225和IC芯片215。裸片附接焊盘205完全嵌入模塑料220'的底部,并且不会从模塑料220'的底部突出。裸片附接焊盘205包括位于封装200'的底部的暴露表面。裸片附接焊盘205的暴露表面通常与模塑料220'的第一底面齐平或共面。模塑料220'的第一底面从裸片附接焊盘205的暴露表面向内接触延伸,但是不到达内接触。替代地,模塑料220'的第二底面从内接触向裸片附接焊盘205的暴露表面延伸。模塑料220'的第一底面和模塑料220'的第二底面会合形成梯级特征。梯级特征出现在内接触之前。
为了实现更为强健的锁定特征,改进型多行无引线封装200、200'具有完全嵌入模塑料的裸片附接焊盘。位于封装底部的裸片附接焊盘的暴露表面与模塑料齐平。端接接触中的一部分或全部部分地嵌入模塑料并且从模塑料突出一定的距离。在一些实施例中,裸片附接焊盘和内接触之间的梯级特征可便于焊接和安装到印刷电路板。优选地,引线框制造步骤为穿通蚀刻和半蚀刻的组合。
改进型单行QFN封装
图5A示出根据本发明的改进型单行无引线封装的底视图。与现有技术的单行无引线封装400相比,此实例中的半导体封装500具有四个附加的有源接触505。四个附加的接触505通常位于封装500的拐角510处。如下文所论述,优选地,所有的接触505和裸片附接焊盘515均处于相同的平面内并且与模塑料570齐平。所有的接触505均暴露于封装500的侧面。
图5B-5F示出根据本发明的制造图5A的改进型单行无引线封装500的处理步骤。具体地,图5B示出根据本发明的制造图5A的改进型单行无引线封装500的方法,而图5C-5F示出通过图5B所示方法的每个步骤制造的例示性结果。
如图5B所示,方法520开始于步骤525,其中提供金属条带。优选地,由一片裸铜或一些其它金属,例如合金42,形成金属层。图5C-5E仅示出金属条带内的仅一个单元。这些单元在金属条带内通常以阵列格式排列。
在步骤530,使用例如PR掩模选择性地半蚀刻金属条带的顶面和底面。通常,基于特定的用户设计对顶面和底面进行蚀刻。在图5C中,以灰色的淡影示出半蚀刻区域。创建接触焊盘、裸片附接焊盘和从裸片附接焊盘的拐角向引线框延伸的四个联结杆。通常,联结杆将裸片附接焊盘连接到引线框。在一些实施例中,围绕裸片附接焊盘的周边并且在接触焊盘之间创建蚀穿区域。在密封过程中,蚀穿区域可有利地使模塑料从引线框的顶部到达其底部并且围绕裸片附接焊盘的侧面。可同时或独立地蚀刻所述表面。
在步骤535,为接触和/或裸片附接焊盘选择性地镀覆金属条带的顶面。通常,顶面的镀覆为Ag或Ni、Pd和Au的叠层。然而,普通的技术人员将认识到,可设想其它镀覆,例如NiPdAu合金、NiAu或NiAu合金。接触上的镀覆是用于键合线。裸片附接焊盘上的镀覆是可选的,因为对于无向下键合的设计而言裸片附接焊盘可为裸铜;或者,为了向下键合目的,裸片附接焊盘可被完全镀覆或选择性地镀覆(例如,在裸片附接焊盘的***区域)。这些均基于特定的用户设计。图5C示出具有***镀覆的裸片附接焊盘。
在步骤540,对金属条带的底面进行胶带层压以防止模制化合物通过开放“通孔”或蚀穿区域从金属条带下方渗出。
在步骤545,制备或装配半导体封装。制备半导体封装包括:将IC芯片附接到裸片附接焊盘,引线键合,模制,模制后固化,激光标记以及可选的条带测试。
在步骤550,通过在模塑工艺之后从金属条带的底面剥离,移除胶带。
在步骤555,使用例如PR掩模选择性地蚀刻底面以从裸片附接焊盘切断四个对角线联结杆,留下四个有源拐角端子。通常,之后将接触彼此电隔离并且与裸片附接焊盘电隔离。若需要,由于此隔离,可以按照条带形对所述单元进行电测试。
在步骤560,可将可焊接材料涂覆到底面。在一些实施例中,为了印刷电路板安装目的,以Sn、SnPb、NiAu、NiPdAu、Ag或其它可焊接材料,包括无铅合成物,例如SnAgCu和SnAgCuNi,对底面上暴露的接触和裸片附接焊盘进行选择性地镀覆。暴露的接触上的焊料膏涂层或焊料球施加也是适合的选项。
在步骤565,对封装进行单片化。将条带内的器件彼此单片化以形成各个成品器件。使用高速锯、激光、高压喷水器或一些其它适当的装置执行单片化。
为了实现更为强健的锁定特征,改进型单行无引线封装500具有完全嵌入模塑料的裸片附接焊盘和接触。优选地,裸片附接焊盘和接触的暴露表面与模塑料共面。该封装大体上利用了封装的所有有价值的占用面积空间。尤其,该封装具有位于其拐角处的附加I/O引线。
如图5F所示,半导体封装500包括裸片附接焊盘515、接触505、安装在裸片附接焊盘515的内表面上的IC芯片575以及用于将芯片575键合到接触505的键合线580。模塑料570密封键合线580和IC芯片575。裸片附接焊盘515和接触505完全嵌入模塑料570的底部并且不从模塑料570的底部突出。裸片附接焊盘515和接触505的底面与模塑料570的底面齐平或共面。裸片附接焊盘515和接触焊盘505具有啮合特征。不同的是,对裸片附接焊盘515和接触焊盘505进行蚀刻,从而使它们联结以与模塑料完全锁定。引线框制造步骤为穿通蚀刻和半蚀刻的组合。
优点
本发明讲授了一种替代的引线框制造工艺和装配方法,其可获得具有与标准QFN类似的机械锁定特征的TLA结构。此导致TLA封装中的强健的可靠性。可获得与标准QFN相当的可靠性等级,而无需减小裸片-DAP比率(例如,减小给定DAP尺寸的可能的最大裸片尺寸)。换句话说,本发明允许对于多行无引线封装可能的最大裸片尺寸。
此外,本发明具有与现有技术的多行封装相同的设计灵活性,其中可围绕IC芯片设计封装。在基于引线框的封装中,此封装技术可实现高达85%的板面积的减小,极大地减小了总信号长度,并且可实现较低的每I/O接线键合封装的成本以及高得多的每本体尺寸的I/O计数。TLA能够替换现有的封装,例如双行QFN、大本体QFN、QFP、FBGA和功率QFN。本发明还可扩展到高级应用,例如MCM、SIP、堆叠裸片和倒装芯片。本发明还使用与标准QFN相同的装备和工艺。用户设计无需任何硬质工具,因此无需资本投资。
对于单行QFN,本发明讲授了一种引线框制造工艺和装配方法,其可去除联结杆并隔离4个拐角接触以提供4个附加的I/O引线。
尽管本论述涵盖单行或多行无引线封装两者的方法和结构,并且具体指向TLA封装,但是应理解,本发明可扩展到高密度引线框阵列(HLA)和标准QFN。
虽然已参照大量的特定细节描述了本发明,但是本领域的普通技术人员将认识到,可以其它特定的形式实施本发明,而不背离本发明的精神。因此,本领域的普通技术人员将理解,本发明并非局限于上述细节,而是由所附权利要求限定。
Claims (22)
1.一种半导体封装,包含:
裸片附接焊盘,其包括内表面和暴露表面;
多个接触,其中所述多个接触包括最接近所述裸片附接焊盘的内接触;
半导体裸片,安装在所述裸片附接焊盘的所述内表面上;
多个联结杆,将所述裸片附接焊盘耦合至所述多个接触;
键合线,其将所述半导体裸片耦合到所述多个接触;以及
模塑料,包括第一底面,其中所述第一底面从所述裸片附接焊盘的所述暴露表面向所述内接触延伸,
其中所述裸片附接焊盘和所述多个接触通过蚀刻引线框而形成;以及
其中所述半导体封装至少通过选择性地镀覆所述引线框的顶面并在蚀刻所述引线框之后将所述引线框的底面与胶带进行层压来制造;并且
其中所述多个接触包括有源的拐角接触,所述拐角接触中的每个拐角接触位于所述引线框的拐角中的一个或多个拐角的顶点上,其中所述联结杆中的每个联结杆从所述裸片附接焊盘的拐角延伸到所述拐角接触中的一个拐角接触,其中所述顶点是导电的并且被设置为I/O引线。
2.如权利要求1所述的半导体封装,其特征在于,所述裸片附接焊盘和所述内接触之间的模塑料、所述裸片附接焊盘以及所述内接触的底面均共面。
3.如权利要求1所述的半导体封装,其特征在于,所述裸片附接焊盘和所述内接触之间的模塑料包括梯级特征,并且其中所述梯级特征形成所述模塑料的第二底面。
4.如权利要求3所述的半导体封装,其特征在于,所述梯级特征为邻近所述内接触的模塑料的缺口。
5.如权利要求1所述的半导体封装,其特征在于,所述模塑料包括第二底面,其中所述模塑料的所述第二底面从所述内接触向所述暴露表面延伸。
6.如权利要求1所述的半导体封装,其特征在于,所述模塑料包括相对于所述内接触的底面凹陷的第二底面。
7.如权利要求1所述的半导体封装,其特征在于,所述内接触被部分地密封。
8.如权利要求1所述的半导体封装,其特征在于,所述多个接触从所述模塑料突出一定的距离。
9.如权利要求1所述的半导体封装,其特征在于,所述裸片附接焊盘和所述多个接触焊盘具有啮合特征。
10.一种制造半导体封装的方法,包含:
蚀刻引线框以形成多个联结杆、多个接触和通过所述多个联结杆耦合到所述多个接触的一部分的裸片附接焊盘,并且以形成蚀刻穿过所述引线框的围绕所述裸片附接焊盘的多个区域;
选择性地镀覆所述引线框的顶面;
将所述引线框的底面与胶带进行层压;
制备所述半导体封装;
蚀刻所述引线框的底面以将所述多个接触与所述裸片附接焊盘隔离;以及
对所述半导体封装进行单片化;
其中所述多个接触包括一个或多个拐角接触,所述拐角接触中的每个拐角接触位于所述引线框的拐角中的一个或多个拐角的顶点上,其中所述联结杆中的每个联结杆从所述裸片附接焊盘的拐角延伸到所述拐角接触中的一个拐角接触,其中所述顶点是导电的并且被设置为I/O引线。
11.如权利要求10所述的方法,其特征在于,以Ag,Ni、Pd和Au的叠层,NiPdAu合金,NiAu或NiAu合金对所述顶面进行镀覆。
12.如权利要求10所述的方法,进一步包含:在制备所述半导体封装之后,从所述引线框的底面移除所述胶带。
13.如权利要求12所述的方法,其特征在于,所述方法进一步包含:在蚀刻所述引线框的底面之后,向所述引线框的底面选择性地涂覆可焊接材料。
14.如权利要求13所述的方法,其特征在于,所述可焊接材料为Sn、NiAu、NiPdAu、Ag、SnPb、SnAgCu、SnAgCuNi或无铅合成物。
15.如权利要求10所述的方法,其特征在于,制备所述半导体封装包括:
将裸片耦合到所述裸片附接焊盘;
将所述裸片引线键合到所述多个接触;以及
密封所述裸片附接焊盘、所述多个接触、所述裸片和键合线。
16.如权利要求10所述的方法,其特征在于,制备所述半导体封装,由此将所述裸片附接焊盘嵌入模塑料中,从而使所述裸片附接焊盘的暴露表面处于所述半导体封装的底部,并且其中所述裸片附接焊盘和最接近所述裸片附接焊盘的接触之间的模塑料从所述裸片附接焊盘的暴露表面向所述接触延伸。
17.如权利要求16所述的方法,其特征在于,所述裸片附接焊盘和所述最接近所述裸片附接焊盘的接触之间的模塑料包括梯级特征。
18.如权利要求10所述的方法,其中在蚀刻所述底面之后,所述多个接触包括有源的拐角接触。
19.如权利要求10所述的方法,其特征在于,所有的接触均未暴露于所述半导体封装的侧面。
20.如权利要求10所述的方法,其特征在于,所有的接触均暴露于所述半导体封装的侧面。
21.根据权利要求16所述的方法,其中所述模塑料形成下底面的部分从所述裸片附接焊盘延伸到所述接触的最内行。
22.根据权利要求16所述的方法,其中经单片化的所述半导体封装包括:
与第一水平对齐的下底面,并且所述下底面由所述裸片附接焊盘的底部和所述模塑料的第一部分形成;和
与高于所述第一水平的第二水平对齐的上底面,并且所述上底面至少部分地由所述模塑料的第二部分形成,其中在所述裸片附接焊盘和所述接触的最内行之间,所述模塑料的底部包括在所述第一水平和所述第二水平之间的梯级。
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CN201911093393.4A Active CN110690123B (zh) | 2012-07-03 | 2013-07-03 | 具有裸片附接焊盘锁定特征的热无引线阵列封装 |
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CN110690123A (zh) | 2020-01-14 |
US20140008777A1 (en) | 2014-01-09 |
CN103531565A (zh) | 2014-01-22 |
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