CN110687138B - Method and device for measuring semiconductor structure and extracting boundary characteristic - Google Patents
Method and device for measuring semiconductor structure and extracting boundary characteristic Download PDFInfo
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- CN110687138B CN110687138B CN201910836957.2A CN201910836957A CN110687138B CN 110687138 B CN110687138 B CN 110687138B CN 201910836957 A CN201910836957 A CN 201910836957A CN 110687138 B CN110687138 B CN 110687138B
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Abstract
The application discloses a method and a device for measuring a semiconductor structure and extracting boundary characteristics. The boundary feature extraction method comprises the following steps: acquiring a section image of the semiconductor structure output by a transmission electron microscope, wherein the section image comprises a section pattern of at least one hole, and a plane where the section pattern is located is vertical to the axial direction of the hole; screening out a first preset pattern by using an energy filtering transmission electron microscopic technology; and identifying a boundary of a first predetermined pattern, wherein the first predetermined pattern is composed of polysilicon in the hole. The boundary feature extraction method utilizes the special property of interaction between polysilicon and electrons, enhances the contrast of the first preset pattern, and achieves the purpose of clearly identifying the boundary of the first preset pattern.
Description
Technical Field
The present invention relates to semiconductor technology, and more particularly, to a method and apparatus for measuring a semiconductor structure and extracting boundary characteristics.
Background
As semiconductor devices are miniaturized, the critical dimension of the semiconductor devices has been reduced to the nanometer level, which means that the critical dimension will determine the performance of the semiconductor devices, and therefore, it has become an essential link to accurately measure the critical dimension and grasp the variation degree of the critical dimension on the nanometer level.
In the prior art, a general simple shape of a semiconductor device or a single and large critical dimension of the semiconductor device can be measured by a measuring tool, but for a complex and small critical dimension structure (such as 3D NAND), the measuring tool in the prior art cannot meet the requirement, mainly because:
1. for example, when a channel hole in a 3D memory device is observed by using an electron microscope, the polysilicon channel layer and the tunneling layer filled in the channel hole have almost the same photo gray scale, and the interface between the polysilicon channel layer and the tunneling layer cannot be distinguished, thereby causing a problem of inaccurate measurement result. Such measurement error may seriously affect the process optimization and electrical performance test of the product.
2. When the prior art is used for measurement, a photo needs to be observed by naked eyes, and for a complex structure with small key size, the difference degree is difficult to distinguish manually, so that the problem of low precision exists.
3. Because manual observation is needed, continuous automatic measurement for multiple times cannot be realized, the problem of low measurement efficiency exists, and the research and development progress is influenced.
Therefore, it is desirable to further improve the measurement and boundary feature extraction method of the semiconductor structure and the apparatus thereof, thereby improving the measurement accuracy, the measurement efficiency and the reliability.
Disclosure of Invention
The invention aims to provide an improved method and a device for measuring a semiconductor structure and extracting boundary characteristics, which utilize the special property of interaction between polysilicon and electrons, enhance the contrast of a first preset pattern and achieve the aim of clearly identifying the boundary of the first preset pattern.
According to a first aspect of the present invention, there is provided a boundary feature extraction method for a semiconductor structure, including: a method for extracting boundary features of a semiconductor structure is characterized by comprising the following steps: acquiring a section image of the semiconductor structure output by a transmission electron microscope, wherein the section image comprises a section pattern of at least one hole, and a plane of the section pattern is perpendicular to the axial direction of the hole; screening out a first preset pattern by using an energy filtering transmission electron microscopic technology; and identifying a boundary of the first predetermined pattern, wherein the first predetermined pattern is composed of polysilicon in the hole.
Preferably, the polysilicon fills the entire space within the hole, and the boundary of the first predetermined pattern serves as the boundary of the hole.
Preferably, the method further comprises the following steps: identifying a boundary of at least one second preset pattern in the graph according to the section image; and obtaining at least one third preset pattern boundary in the hole according to the boundary in the first preset pattern and the boundary of the second preset pattern, wherein the at least one third preset pattern is positioned between the first preset pattern and the at least one second preset pattern.
Preferably, the semiconductor structure includes a 3D memory device, the hole includes a channel hole in the 3D memory device, the channel hole is filled with a channel layer and a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer surrounding the channel layer in sequence, wherein the first preset pattern includes a cross-sectional pattern of the channel layer, the second preset pattern includes a cross-sectional pattern of the charge storage layer, and the third preset pattern includes a cross-sectional pattern of the tunneling dielectric layer.
Preferably, an insulating inner core is further filled in the channel hole, the channel layer surrounds the insulating inner core, and the third preset pattern further includes a cross-sectional pattern of the insulating inner core.
Preferably, the second preset pattern further includes a cross-sectional pattern of the gate dielectric layer.
Preferably, the boundary of the first preset pattern, the boundary of the second preset pattern and the boundary of the third preset pattern are used for automatically measuring the critical dimension and/or distortion value and/or the notching degree of each filling layer in the trench hole.
According to a second aspect of the present invention, there is provided a method of measuring a semiconductor structure, comprising: acquiring a section image of the semiconductor structure output by a transmission electron microscope, wherein the section image comprises a section pattern of at least one hole, and a plane of the section pattern is perpendicular to the axial direction of the hole; screening out a preset pattern by using an energy filtering transmission electron microscopy technology; identifying a boundary of the predetermined pattern, the predetermined pattern being comprised of polysilicon in the hole; obtaining the crystallization area of the polycrystalline silicon according to the section image; obtaining the total area of the preset pattern according to the boundary of the preset pattern; and obtaining the crystallization rate of the polysilicon in the hole according to the ratio of the crystallization area to the total area.
According to a third aspect of the present invention, there is provided a boundary feature extraction apparatus of a semiconductor structure, comprising: the acquisition module is used for acquiring a section image of the semiconductor structure output by a transmission electron microscope, and comprises a section pattern of at least one hole, wherein the plane of the section pattern is perpendicular to the axial direction of the hole; the screening module is used for screening out a first preset pattern by utilizing an energy filtering transmission electron microscopic technology; and the first identification module is used for identifying the boundary of the first preset pattern, wherein the first preset pattern is formed by polysilicon in the hole.
Preferably, the polysilicon fills the entire space within the hole, and the boundary of the first predetermined pattern serves as the boundary of the hole.
Preferably, the method further comprises the following steps: the second identification module is used for identifying the boundary of at least one second preset pattern in the graph according to the section image; and a third recognition module, configured to obtain at least one third preset pattern boundary in the hole according to a boundary in the first preset pattern and a boundary in the second preset pattern, where the at least one third preset pattern is located between the first preset pattern and the at least one second preset pattern.
Preferably, the semiconductor structure includes a 3D memory device, the hole includes a channel hole in the 3D memory device, the channel hole is filled with a channel layer and a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer surrounding the channel layer in sequence, wherein the first preset pattern includes a cross-sectional pattern of the channel layer, the second preset pattern includes a cross-sectional pattern of the charge storage layer, and the third preset pattern includes a cross-sectional pattern of the tunneling dielectric layer.
Preferably, an insulating inner core is further filled in the channel hole, the channel layer surrounds the insulating inner core, and the third preset pattern further includes a cross-sectional pattern of the insulating inner core.
Preferably, the second preset pattern further includes a cross-sectional pattern of the gate dielectric layer.
Preferably, the boundary of the first preset pattern, the boundary of the second preset pattern and the boundary of the third preset pattern are used for automatically measuring the critical dimension and/or distortion value and/or roughness of each filling layer in the trench hole.
According to a fourth aspect of the present invention, there is provided a measurement apparatus of a semiconductor structure, comprising: the acquisition module is used for acquiring a section image of the semiconductor structure output by a transmission electron microscope, and comprises a section pattern of at least one hole, wherein the plane of the section pattern is perpendicular to the axial direction of the hole; the screening module is used for screening out a preset pattern by utilizing an energy filtering transmission electron microscopy technology; the recognition module is used for recognizing the boundary of the preset pattern, and the preset pattern is formed by the polycrystalline silicon in the hole; the first measuring module is used for obtaining the crystallization area of the polycrystalline silicon according to the section image; the second measurement module is used for obtaining the total area of the preset pattern according to the boundary in the preset pattern; and a calculation module for obtaining the crystallization rate of the polysilicon in the hole according to the ratio of the crystallization area to the total area.
According to the method and the device for measuring the semiconductor structure and extracting the boundary characteristics, the detailed characteristics of the semiconductor structure can be obtained by acquiring the section image of the semiconductor structure output by a transmission electron microscope, wherein the pixel size is generally from a few nanometers to dozens of nanometers and even below the nanometer level; the first preset pattern is screened by using the energy filtering transmission electronic microscopic technology, and because the first preset pattern is formed by polysilicon in the holes, when the first preset pattern is screened by using the energy filtering transmission electronic microscopic technology, the output filtered electron is like a result of interaction between incident electrons and the polysilicon, on the screened section image, the brightness of the part formed by the polysilicon is greatly enhanced, and the brightness formed by other substances is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic diagram illustrating steps of a method for extracting boundary features of a semiconductor structure according to an embodiment of the present invention.
Fig. 2 shows a schematic diagram of the step S03 in fig. 1.
Fig. 3 shows a schematic view of sectional images taken at different heights along the same horizontal direction.
Fig. 4 shows a schematic cross-sectional view of fig. 3 along line AA.
Fig. 5a is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.
Figure 5b shows a schematic cross-sectional image of figure 5a after screening using energy-filtered transmission electron microscopy.
Fig. 6 shows a schematic diagram of the principle of energy-filtered transmission electron microscopy.
Fig. 7a shows a schematic diagram of the boundary image of fig. 5 b.
Fig. 7b shows a simplified schematic of the boundary image of fig. 7 a.
Fig. 8a shows a schematic diagram of the boundary image of fig. 5 a.
Fig. 8b shows a simplified schematic diagram of the boundary image of fig. 8 a.
Fig. 9 shows a schematic view of the superposition of fig. 7b and 8 b.
Fig. 10a and 10b are schematic diagrams illustrating the steps of identifying the boundary of the hole according to the embodiment of the present invention.
Fig. 11 is a schematic step diagram illustrating a method for measuring a semiconductor structure according to an embodiment of the present invention.
Fig. 12a shows the sectional image obtained in step S10 of fig. 11.
Fig. 12b shows the preset pattern obtained in step S20 of fig. 11.
Fig. 13 is a diagram showing the output result of the crystallization rate obtained in step S60 of fig. 11.
Fig. 14 is a schematic structural diagram illustrating a boundary feature extraction apparatus of a semiconductor structure according to an embodiment of the present invention.
FIG. 15 is a schematic structural diagram of a measuring apparatus for a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 1 shows a schematic step diagram of a method for measuring a semiconductor structure according to an embodiment of the present invention.
In step S01, a cross-sectional image of the semiconductor structure output by a Transmission Electron Microscope (TEM) is acquired.
In this step, for example, sectional images are taken at different heights in the same horizontal direction of the semiconductor structure 100, as shown in fig. 3, for example, sectional images are taken along the AA line and the BB line, respectively, and sectional patterns of different depths of the same hole 101 can be obtained. Wherein only one hole 101 is shown in figure 3 for clarity of presentation. However, embodiments of the present invention are not obvious and other arrangements of the number of holes in a semiconductor may be made as desired by those skilled in the art. For example, when the semiconductor structure is a 3D memory, the semiconductor structure may include a plurality of holes 101 as channel holes or other deep hole structures.
Hereinafter, the hole 101 will be described as an example of a channel hole of a 3D memory, and it is necessary to fill the channel layer 111 and the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114, which sequentially surround the channel layer 111, in the hole 101. In some other embodiments, it is also desirable to fill the hole 101 with an insulating core 115 surrounded by the channel layer 111, as shown in fig. 4, wherein the channel layer 111 is composed of, for example, polysilicon, the tunneling dielectric layer 112, the gate dielectric layer 114, and the insulating core 115 are respectively composed of oxides, such as silicon oxide, and the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals.
In this step, the sectional image is a gray scale image obtained directly or indirectly and includes a sectional pattern of at least one hole, the plane of the sectional pattern being perpendicular to the axial direction of the hole, as shown in fig. 5 a.
In step S02, a first predetermined pattern, which is a cross-sectional pattern of the channel layer 111 and the insulating core 115, is screened out by using Energy Filtered Transmission Electron Microscopy (EFTEM), as shown in fig. 5 b.
Referring to fig. 6, the energy-filtered transmission electron microscopy will be described in detail, as shown in fig. 6, an image a is an image output by a TEM, the image a is converted into a spectrum by a prism 102, the spectrum is energy-filtered by an energy-selective slit 103, and a selected portion is converted back into an energy-filtered image B, so as to obtain a screened first preset pattern.
In a specific embodiment, when TEM imaging is performed, incident electrons interact with substances, a part of the incident electrons lose energy, and the incident electrons losing energy are distinguished by EFTEM and are imaged separately to form an energy-filtered image. If the energy-filtered image is a result of characterizing the interaction of the incident electrons and the polysilicon, the luminance of the portion of the polysilicon on the energy-filtered image is greatly enhanced (see the luminance of the channel layer 111 in fig. 5a and the channel layer 111 in fig. 5 b), while the luminance of the portion of the other material is reduced (see the effect of the tunnel dielectric layer 112, the charge storage layer 113, the gate dielectric layer 114, and the insulating core 115 in fig. 5 b). The method utilizes the special property of interaction between polysilicon and electrons, and enhances the contrast of the channel layer 111.
The boundary of the first preset pattern is identified in step S03. As the critical dimensions of semiconductor devices have been reduced to the nanometer scale, one step that is important for measuring device critical dimensions is to obtain precise pattern boundaries to provide accurate parameters for subsequent critical dimension measurements. As shown in fig. 2, the boundary of the graph can be recognized through the following steps S031 through S032.
In step S031, the cross-section image is denoised.
In this step, for example, a plurality of functions of unit length and gray scale value are obtained according to the gray scale value of each row of pixels of the cross-sectional image. Then, each function is subjected to high-frequency filtering. After high frequency filtering, noise in the image can be filtered out.
In step S032, a calculus process is performed on the section image to identify the boundary of the pattern. In this step, for example, first, second-order derivative processing is performed on each of the functions, second-order derivatives of each function are obtained, and boundary points of each row of pixels are identified based on the second-order derivatives of each function. Thereafter, a plurality of boundary point coordinates on the boundary are obtained based on the second derivative processing result. The boundary point coordinates of each line of pixels need to be calculated, and a plurality of boundary point coordinates form a boundary curve of the graph. Finally, a boundary image is obtained according to each second derivative, as shown in fig. 7a, wherein a plurality of derivative values in each derivative are required to be converted into gray levels, and each derivative corresponds to a row of pixels.
Fig. 7b shows a simplified schematic diagram of the boundary image of fig. 7a, as can be seen from fig. 7a and 7b, the boundary 1 may represent the boundary of the hole, the pattern sandwiched by the boundary 4 and the boundary 5 is a cross-sectional pattern of the channel layer 111, the pattern surrounded by the boundary 5 is a cross-sectional pattern of the insulating core 115, and may also be expressed as: the boundary of the cross-sectional pattern of the channel layer 111 is boundary 4 and boundary 5, and the boundary of the cross-sectional pattern of the insulating core 115 is boundary 5.
In step S04, a boundary of at least one second predetermined pattern in the pattern is identified according to the profile image, as shown in fig. 8a and 8b, wherein the second predetermined pattern is a cross-sectional pattern of the charge storage layer 113 and the gate dielectric layer 114. Since the method and steps for identifying the boundary of the second predetermined pattern are similar to those of the first predetermined pattern, the description is omitted here, and the step S031 to the step S032 above may be referred to identify the boundary of the second predetermined pattern.
As can be seen from fig. 8a and 8b, the boundary 1 may represent the boundary of the hole, the pattern sandwiched between the boundary 1 and the boundary 2 is the cross-sectional pattern of the gate dielectric layer 114, and the pattern sandwiched between the boundary 2 and the boundary 3 is the cross-sectional pattern of the charge storage layer 113. It can also be expressed as: the boundaries of the cross-sectional pattern of the gate dielectric layer 114 are boundary 1 and boundary 2, and the boundaries of the cross-sectional pattern of the charge storage layer 113 are boundary 2 and boundary 3.
In step S05, at least one third predetermined pattern boundary in the hole is obtained according to the boundary in the first predetermined pattern and the boundary in the second predetermined pattern, where at least one third predetermined pattern is located between the first predetermined pattern and at least one second predetermined pattern, and as a specific example, the third predetermined pattern includes a cross-sectional pattern of the tunnel medium layer 112.
In this step, fig. 9 is obtained by graphically superimposing fig. 7b and fig. 8b, so that the boundary 1 to the boundary 5 are all represented in fig. 9. In the process of superimposition, since both fig. 7b and fig. 8b include the boundary 1, the boundary 1 may be used as a reference for the graphic superimposition alignment, and the boundary 1 in fig. 7b and fig. 8b may be superimposed.
As shown in fig. 9, the pattern sandwiched between boundary 3 and boundary 4 is the cross-sectional pattern of tunnel dielectric layer 112, which can also be expressed as the boundary of the cross-sectional pattern of tunnel dielectric layer 112 is boundary 3 and boundary 4. To this end, the boundaries of the respective filling layers in the trench holes are obtained, and in the subsequent measurement step, the boundaries of the first predetermined pattern, the boundaries of the second predetermined pattern, and the boundaries of the third predetermined pattern may be used to automatically measure the critical dimension and/or distortion value and/or the notching degree of the respective filling layers in the trench holes.
In some other embodiments, if it is desired to separately obtain the size of the hole 101, the hole 101 may be directly filled with a polysilicon material, and the steps S01 to S03 are performed, wherein the boundary of the first predetermined pattern serves as the boundary of the hole since the polysilicon fills the entire space in the hole. As shown in fig. 10a to 10b, in which fig. 10a is a TEM image and fig. 10b is an EFTEM-screened image, comparing fig. 10a and 10b, the EFTEM-screened image can clearly define the boundary of the hole 101.
Fig. 11 is a schematic step diagram illustrating a method for measuring a semiconductor structure according to an embodiment of the present invention.
In step S10, a cross-sectional image of the semiconductor structure output by the transmission electron microscope is acquired, which includes a cross-sectional profile of at least one hole, the cross-sectional profile lying in a plane perpendicular to the axial direction of the hole, as shown in fig. 12 a. In step S20, the predetermined pattern is screened out using energy-filtered transmission electron microscopy, as shown in fig. 12 b. In step S30, the boundary of the preset pattern, which is composed of polysilicon in the hole, is identified. Since the specific contents of steps S10-S30 are substantially identical to steps S01-S03 in fig. 1, they will not be described in detail here. Wherein the predetermined pattern is a cross-sectional pattern of the channel layer 111.
In step S40, the total area of the preset pattern is obtained according to the boundaries of the preset pattern. In this step, ellipse fitting may be performed on two boundaries of the channel layer 111, respectively, and then the difference value of the two ellipses may be used as the total area of the cross-sectional pattern of the channel layer 111.
In step S50, the crystal area of the polycrystalline silicon is obtained from the sectional image. In this step, the crystallized area of the polycrystalline silicon is measured, for example, using Polymerase Chain Reaction (PCR).
In step S60, the crystallization rate of the polysilicon in the hole is obtained from the ratio of the crystallization area to the total area, as shown in fig. 13. Wherein, it can be known that the crystallization rate of the polysilicon in the trench hole is 70.3%
Fig. 14 is a schematic structural diagram illustrating a boundary feature extraction apparatus for a semiconductor structure according to an embodiment of the present invention.
As shown in fig. 14, the boundary feature extraction apparatus of the semiconductor structure according to the embodiment of the present invention includes: an acquisition module 110, a screening module 120, a first recognition module 130, a second recognition module 140, and a third recognition module 150.
The obtaining module 110 is configured to obtain a cross-sectional image of the semiconductor structure output by the transmission electron microscope, the cross-sectional image including a cross-sectional view of at least one hole, the plane of the cross-sectional view being perpendicular to the axial direction of the hole. The screening module 120 is configured to screen out a first predetermined pattern by using an energy filtering transmission electron microscopy technique. The first recognition module 130 is used for recognizing a boundary of a first predetermined pattern, wherein the first predetermined pattern is formed by polysilicon in the hole. The second recognition module 140 is configured to recognize a boundary of at least one second preset pattern in the graph according to the sectional image. The third identifying module 150 is configured to obtain at least one third preset pattern boundary in the hole according to the boundary in the first preset pattern and the boundary in the second preset pattern, where the at least one third preset pattern is located between the first preset pattern and the at least one second preset pattern.
In some embodiments, the polysilicon fills the entire space within the hole, and the boundary of the first predetermined pattern serves as the boundary of the hole.
In other embodiments, a semiconductor structure includes a 3D memory device, the hole including a channel hole in the 3D memory device, the channel hole being filled with a channel layer and a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer surrounding the channel layer in sequence, wherein a first predetermined pattern includes a cross-sectional pattern of the channel layer, a second predetermined pattern includes a cross-sectional pattern of the charge storage layer, and a third predetermined pattern includes a cross-sectional pattern of the tunneling dielectric layer.
In some preferred embodiments, the channel hole is further filled with an insulating core, the channel layer surrounds the insulating core, and the third predetermined pattern further includes a cross-sectional pattern of the insulating core. The second preset pattern also comprises a cross-sectional pattern of the gate dielectric layer. The boundary of the first preset pattern, the boundary of the second preset pattern and the boundary of the third preset pattern are used for automatically measuring the critical dimension and/or distortion value and/or roughness of each filling layer in the trench hole.
The boundary extraction device of the semiconductor structure according to the embodiment of the present invention automatically extracts the boundary of the semiconductor structure, so as to implement the above boundary extraction method, which is not described herein again.
FIG. 15 is a schematic structural diagram of a measuring apparatus for a semiconductor structure according to an embodiment of the present invention.
As shown in fig. 15, the measuring apparatus of the semiconductor structure according to the embodiment of the present invention includes: an acquisition module 210, a screening module 220, an identification module 230, a first measurement module 240, a second measurement module 250, and a calculation module 260.
The obtaining module 210 is configured to obtain a cross-sectional image of the semiconductor structure output by the transmission electron microscope, and includes a cross-sectional view of at least one hole, where a plane of the cross-sectional view is perpendicular to an axial direction of the hole. The screening module 220 is configured to screen out a predetermined pattern using energy-filtered transmission electron microscopy. The recognition module 230 is used for recognizing the boundary of the preset pattern, which is composed of the polysilicon in the hole. The first measurement module 240 is used for obtaining the crystallization area of the polysilicon according to the cross-sectional image. The second measuring module 250 is configured to obtain a total area of the preset pattern according to a boundary in the preset pattern. The calculation module 260 is configured to obtain a crystallization rate of the polysilicon in the hole according to a ratio of the crystallization area to the total area.
The measuring device of the semiconductor structure according to the embodiment of the invention automatically measures the semiconductor structure to realize the measuring method, and details are not repeated here.
According to the method and the device for measuring the semiconductor structure and extracting the boundary characteristics, the detail characteristics of the semiconductor structure can be obtained by acquiring the section image of the semiconductor structure output by a transmission electron microscope, and the pixel size is generally from a few nanometers to dozens of nanometers and even below the nanometer level; the method utilizes the special property of the interaction between the polysilicon and the electrons to enhance the contrast of the first preset pattern and achieve the purpose of clearly identifying the boundary of the first preset pattern.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (14)
1. A method for extracting boundary features of a semiconductor structure is characterized by comprising the following steps:
acquiring a section image of the semiconductor structure output by a transmission electron microscope, wherein the section image comprises a section pattern of at least one hole, and a plane of the section pattern is perpendicular to the axial direction of the hole;
screening out a first preset pattern and a second preset pattern by using an energy filtering transmission electron microscopic technology;
identifying a boundary of the first predetermined pattern and a boundary of the at least one second predetermined pattern, wherein at least one coincident boundary exists between the boundary of the first predetermined pattern and the boundary of the at least one second predetermined pattern, and
obtaining at least one third preset pattern boundary in the hole according to the boundary of the first preset pattern and the boundary of the second preset pattern, wherein the at least one third preset pattern is located between the first preset pattern and the at least one second preset pattern;
wherein the semiconductor structure includes a 3D memory device, the hole includes a channel hole in the 3D memory device, and the first predetermined pattern is composed of polysilicon in the hole.
2. The boundary feature extraction method according to claim 1, wherein the polysilicon fills all of the space in the hole, and the boundary of the first predetermined pattern serves as the boundary of the hole.
3. The boundary feature extraction method according to claim 1, wherein a channel layer, a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer are filled in the channel hole and sequentially surround the channel layer;
the first preset pattern comprises a cross-sectional pattern of the channel layer, the second preset pattern comprises a cross-sectional pattern of the charge storage layer, and the third preset pattern comprises a cross-sectional pattern of the tunneling medium layer.
4. The boundary feature extraction method according to claim 3, wherein the channel hole is further filled with an insulating inner core, the channel layer surrounds the insulating inner core, and the third preset pattern further includes a cross-sectional pattern of the insulating inner core.
5. The boundary feature extraction method of claim 4, wherein the second predetermined pattern further comprises a cross-sectional pattern of the gate dielectric layer.
6. The method as claimed in claim 5, wherein the boundary of the first predetermined pattern, the boundary of the second predetermined pattern and the boundary of the third predetermined pattern are used to automatically measure the critical dimension and/or the distortion value and/or the notching degree of each filling layer in the trench hole.
7. A method of measuring a semiconductor structure, comprising:
acquiring a section image of the semiconductor structure output by a transmission electron microscope, wherein the section image comprises a section pattern of at least one hole, and a plane of the section pattern is perpendicular to the axial direction of the hole;
screening out a first preset pattern and a second preset pattern by using an energy filtering transmission electron microscopic technology;
identifying a boundary of the first preset pattern and a boundary of at least one second preset pattern, wherein at least one coincident boundary exists in the boundary of the first preset pattern and the boundary of the at least one second preset pattern, at least one third preset pattern is located between the first preset pattern and the at least one second preset pattern, the semiconductor structure comprises a 3D memory device, the hole comprises a channel hole in the 3D memory device, and the first preset pattern is formed by polysilicon in the hole;
obtaining the crystallization area of the polycrystalline silicon according to the section image;
obtaining the total area of the first preset pattern according to the boundary of the first preset pattern; and
and obtaining the crystallization rate of the polycrystalline silicon in the hole according to the ratio of the crystallization area to the total area.
8. An apparatus for extracting boundary features of a semiconductor structure, comprising:
the acquisition module is used for acquiring a section image of the semiconductor structure output by a transmission electron microscope, and comprises a section pattern of at least one hole, wherein the plane of the section pattern is perpendicular to the axial direction of the hole;
the screening module is used for screening out a first preset pattern and a second preset pattern by utilizing an energy filtering transmission electronic microscopic technology;
the first identification module is used for identifying the boundary of the first preset pattern;
a second recognition module for recognizing a boundary of at least one second preset pattern in the graph according to the sectional image, wherein at least one coincident boundary exists between the boundary of the first preset pattern and the boundary of the at least one second preset pattern, and at least one third preset pattern is located between the first preset pattern and the at least one second preset pattern, and
a third identification module, configured to obtain at least one third preset pattern boundary in the hole according to a boundary in the first preset pattern and a boundary in the second preset pattern;
wherein the semiconductor structure includes a 3D memory device, the hole includes a channel hole in the 3D memory device, and the first predetermined pattern is composed of polysilicon in the hole.
9. The boundary feature extraction device according to claim 8, wherein the polysilicon fills all of the space within the hole, and the boundary of the first predetermined pattern serves as the boundary of the hole.
10. The boundary feature extraction device according to claim 8, wherein a channel layer, a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer are filled in the channel hole and sequentially surround the channel layer;
the first preset pattern comprises a cross-sectional pattern of the channel layer, the second preset pattern comprises a cross-sectional pattern of the charge storage layer, and the third preset pattern comprises a cross-sectional pattern of the tunneling medium layer.
11. The boundary feature extraction device according to claim 10, wherein the channel hole is further filled with an insulating inner core, the channel layer surrounds the insulating inner core, and the third preset pattern further includes a cross-sectional pattern of the insulating inner core.
12. The boundary feature extraction device according to claim 11, wherein the second predetermined pattern further includes a cross-sectional pattern of the gate dielectric layer.
13. The boundary feature extraction apparatus according to claim 12, wherein the boundaries of the first predetermined pattern, the boundaries of the second predetermined pattern, and the boundaries of the third predetermined pattern are used to automatically measure the critical dimension and/or distortion value and/or roughness of each filling layer in the trench hole.
14. A measurement device for a semiconductor structure, comprising:
the acquisition module is used for acquiring a section image of the semiconductor structure output by a transmission electron microscope, and comprises a section pattern of at least one hole, wherein the plane of the section pattern is perpendicular to the axial direction of the hole;
the screening module is used for screening out a first preset pattern and a second preset pattern by utilizing an energy filtering transmission electronic microscopic technology;
an identifying module, configured to identify a boundary of the first preset pattern and a boundary of at least one of the second preset patterns, where at least one of the boundary of the first preset pattern and the boundary of at least one of the second preset patterns coincides with each other, at least one third preset pattern is located between the first preset pattern and at least one of the second preset patterns, the semiconductor structure includes a 3D memory device, the hole includes a channel hole in the 3D memory device, and the first preset pattern is formed by polysilicon in the hole;
the first measuring module is used for obtaining the crystallization area of the polycrystalline silicon according to the section image;
the second measurement module is used for obtaining the total area of the first preset pattern according to the boundary in the first preset pattern; and
and the calculation module is used for obtaining the crystallization rate of the polycrystalline silicon in the hole according to the ratio of the crystallization area to the total area.
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