CN110659236A - AXI bus transmission device capable of autonomously replying write response - Google Patents
AXI bus transmission device capable of autonomously replying write response Download PDFInfo
- Publication number
- CN110659236A CN110659236A CN201910905083.1A CN201910905083A CN110659236A CN 110659236 A CN110659236 A CN 110659236A CN 201910905083 A CN201910905083 A CN 201910905083A CN 110659236 A CN110659236 A CN 110659236A
- Authority
- CN
- China
- Prior art keywords
- fifo
- write
- module
- counting
- axi bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3041—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is an input/output interface
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Quality & Reliability (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Communication Control (AREA)
Abstract
The invention discloses an AXI bus transmission device for autonomously replying write response, which is connected between an AXI bus and a local bus and used for replacing slave equipment to return write response, and comprises an FIFO _ A, FIFO _ B, a counting module, a comparison module and a selector; the FIFO _ A is connected with the AXI bus and used for storing awid and awlen signals in a received write command sent by the AW channel, the counting module is connected with the AXI bus and used for counting actually received effective data, and the input end of the FIFO _ B is connected with the output end of the counting module and used for storing actual data receiving length information; the comparison module is used for comparing whether the length values stored in the FIFO _ A and the FIFO _ B are equal or not, and the input end of the selector is respectively connected with the output end of the comparison module and the input end of the selector 2 to select and output write response. The invention automatically extracts the current command element and the slave equipment state, generates the write response, and automatically replies without changing the design of the slave equipment module.
Description
Technical Field
The invention relates to an AXI bus transmission device, in particular to an AXI bus transmission device capable of autonomously replying write response, and belongs to the technical field of AXI bus transmission devices.
Background
The bus protocol is various, and the master and slave device modules can shield the influence caused by different bus protocol interfaces when being designed, and use own specific transmission protocol interfaces, called local interface protocols, so that the master and slave device modules need to convert the bus protocol into the local interface protocol (bus transmission) module to be hung on different buses.
The AXI bus protocol is a bus transfer protocol that is currently in widespread use. According to the AXI bus protocol, when a point-to-point transmission is performed, a master device module (hardware apparatus) sends a write command and write data to a slave device module (hardware apparatus), and after the data transmission is completed, the slave device needs to return a write response. If the slave device returns a write response to the AXI bus, the slave device needs to also support the AXI protocol, specifically a corresponding AXI interface, which may cause the slave device to be complicated in design, or modify the already designed slave device.
Disclosure of Invention
The invention provides an AXI bus transmission device capable of autonomously replying write response, which automatically extracts current command elements and slave equipment states according to the characteristics of an AXI protocol, generates write response, and automatically replies without additional interaction with a slave equipment module, thereby not changing the design of the slave equipment module.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: the device is connected between the AXI bus and a local bus and used for replacing slave equipment to return a write response, and comprises a FIFO _ A, FIFO _ B, a counting module, a comparison module and a selector; FIFO _ A is connected with AXI bus, used for storing awid and awlen signals in the received write command sent by AW channel, awid represents ID of write command, each write command has corresponding ID value, awlen represents write data transmission length information in write command; the counting module is connected with the AXI bus and used for counting the actually received effective data and writing the recorded actual data transmission length information into the FIFO _ B; the input end of the FIFO _ B is connected with the output end of the counting module and used for storing the actual data receiving length information; the input end of the comparison module is respectively connected with the output ends of the FIFO _ A and the FIFO _ B and is used for comparing whether the length values stored in the FIFO _ A and the FIFO _ B are equal, if so, 0 is output, otherwise, 2 is output, 0 represents correct, and 2 represents transmission error; the input end of the selector is respectively connected with the output end of the comparison module and the output end of the comparison module 2, the enabling end of the selector is connected with the lclk _ dis and the lrst, the lclk _ dis is a clock turn-off signal of the slave equipment module and effectively represents that the clock of the slave equipment module is turned off, the lrst is a reset signal of the slave equipment module and effectively represents that the slave equipment is in a reset state currently, if the current lclk _ dis or the lrst is effective, the comparison module 2 is selected to be output, otherwise, the comparison module result is output; the output of the selector is bresp, the id value in the FIFO _ A is directly assigned to bid, and bresp and bid are the write response returned by the device.
Further, the counting module is connected with a write data channel W of the AXI bus, and a last write signal wlast in the write data channel W determines the working state of the counting module; when the W channel receives valid data and the current wlast is invalid, the counting module starts counting from 0, when the W channel receives one valid data and the wlast signal is invalid, the counting value is added by 1, when the wlast is valid, the counting module writes the currently recorded actual data transmission length information into FIFO _ B, and the counter is cleared.
Furthermore, FIFO _ A is connected to write command channel AW of AXI bus, AW channel receives effective AXI write command, and stores signal values of awid and awlen into FIFO _ A.
Further, when neither FIFO _ a nor FIFO _ B is empty, the comparison module reads the values in both FIFOs at the same time once, wherein the id value stored in FIFO _ a is given to bid, and compares whether the length values stored in both FIFOs are equal, if so, outputs 0, otherwise, outputs 2.
Further, the FIFO _ a may continuously or intermittently receive a plurality of AXI write commands, the counting module counting once for each write command.
The invention has the beneficial effects that: the invention monitors the AXI transmission command and the local equipment module on the basis of supporting the AXI protocol, autonomously replies the AXI write response according to the actual transmission condition and the working condition of the equipment module, ensures the normal operation of an AXI bus system, can effectively reflect the transmission condition of the current write command, and does not need to additionally modify the originally defined local interface.
Drawings
Fig. 1 is a schematic block diagram of the present invention.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
The embodiment discloses an AXI bus transmission device capable of autonomously replying write response, which is connected between an AXI bus and a local bus and is used for replacing slave equipment to return write response, wherein the method for realizing the function comprises the steps of monitoring an AXI transmission command and local slave equipment (namely, automatically extracting a current command element and a slave equipment state), and autonomously replying the AXI write response according to an actual transmission condition and an equipment module working condition, so that the normal operation of an AXI bus system is ensured, the transmission condition of the current write command can be effectively reflected, and an originally defined local interface is not required to be additionally modified.
As shown in fig. 1, the AXI bus transfer device includes a FIFO A, FIFO B, a count module, a compare module, and a selector.
FIFO _ A is connected with AXI bus, used for storing awid and awlen signals in the received write command sent by AW channel, awid represents ID of write command, each write command has corresponding ID value, awlen represents write data transmission length information in write command; the counting module is connected with the AXI bus and used for counting the actually received effective data and writing the recorded actual data transmission length information into the FIFO _ B; the input end of the FIFO _ B is connected with the output end of the counting module and used for storing the actual data receiving length information; the input end of the comparison module is respectively connected with the output ends of the FIFO _ A and the FIFO _ B and is used for comparing whether the length values stored in the FIFO _ A and the FIFO _ B are equal, if so, 0 is output, otherwise, 2 is output, wherein 0 represents correct, and 2 represents transmission error; the input end of the selector is respectively connected with the output end of the comparison module and the output end of the comparison module 2, the enabling end of the selector is connected with the lclk _ dis and the lrst, the lclk _ dis is a clock turn-off signal of the slave equipment module and effectively represents that the clock of the slave equipment module is turned off, the lrst is a reset signal of the slave equipment module and effectively represents that the slave equipment is in a reset state currently, if the current lclk _ dis or the lrst is effective, the comparison module 2 is selected to be output, otherwise, the comparison module result is output; the output of the selector is bresp, the id value in the FIFO _ A is directly assigned to bid, and bresp and bid are the write response returned by the device.
In this embodiment, the counting module is connected to a write data channel W of the AXI bus, and a last write signal wlast in the write data channel W determines a working state of the counting module. The W channel receives valid data, when the current wlan is invalid and low, the counting module starts counting from 0, when the wlan is valid and high, the counting module writes the currently recorded actual data transmission length information into FIFO _ B, and clears the counter.
In this embodiment, FIFO _ a is connected to a write command channel AW of the AXI bus, and the AW channel receives an effective AXI write command and stores signal values awid and awlen into FIFO _ a.
And when neither FIFO _ A nor FIFO _ B is empty, the comparison module reads the values in the two FIFOs once, wherein the id value stored in the FIFO _ A is given to bid, and compares whether the length values stored in the two FIFOs are equal or not, if so, 0 is output, otherwise, 2 is output.
The specific process of returning the write-back response by utilizing the device is as follows:
1. and the AW channel receives a valid AXI write command and stores signal values of awid and awlen into FIFO _ A. The commands can be continuously and discontinuously received in a plurality of pieces, and the counting module counts once for each writing command. The FIFO _ a depth depends on the number of commands that can be buffered.
2. The W channel receives valid write data, and the current wlast signal is invalid, the counter starts counting from 0. The counter value is incremented by 1 each time a valid data is received and the wlan signal is inactive.
3. And when the W channel receives valid write data and the current wlast signal is valid, the counter stops counting and writes the current count value into the FIFO _ B. The counter then clears the count value. After the zero clearing, the data length of the next write command can be counted continuously.
4. The comparison module detects that neither FIFO _ a nor FIFO _ B is empty and reads from both FIFOs once each. The id value in FIFO _ A is directly assigned to bid, and the write command and the write response id are in one-to-one correspondence according to the AXI protocol. The length values recorded in FIFO _ A and FIFO _ B are compared, if the length values are consistent, 0 is output, otherwise 2 is output.
5. The selector selects to assign the output value of the comparison module or 2 to bresp according to the current lclk _ dis and lrst signal values. If lclk _ dis or lrst are arbitrarily valid, assign 2 to bresp; otherwise, the output value of the comparison module is output.
The present invention monitors the slave status via lclk _ dis and lrst signals. According to the AXI protocol, any write-together transfer initiated by the master module cannot be paused or cancelled and the slave module must give an acknowledgement or the master module will wait all the time. The present embodiment monitors the slave device status in real time, and if the current slave device module is in the reset status or the local clock off status and cannot correctly receive the data sent by the bus, after receiving the write command and the write data, automatically returns the response 2. Thus, the system can not be jammed.
According to AXI protocol specifications, in the write command channel AW, one write command contains write data transfer length information awlen. In the write data channel W, the last data transmission will be asserted with the wlast signal (write last signal) high, and otherwise, the signal will be low. In this embodiment, the data transmission length in the received write command is compared with the actual data transmission number, and if the data transmission length is not consistent with the actual data transmission number, a response 2 is returned; otherwise, an answer of 0 is returned. The actual number of data transfers is derived from the wlast count of the write data channel. The receiving sequence of the writing commands and the receiving sequence of the writing data are in one-to-one correspondence and are not out of order.
According to the characteristics of the AXI protocol, the invention automatically extracts the current command element and the slave equipment state, generates a write response and automatically replies, and does not need to additionally interact with the slave equipment module, thereby not changing the design of the slave equipment module.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.
Claims (5)
1. An AXI bus transfer apparatus capable of autonomously replying to a write response, characterized in that: the device is connected between an AXI bus and a local bus and used for replacing slave equipment to return a write response, and comprises a FIFO _ A, FIFO _ B, a counting module, a comparison module and a selector; FIFO _ A is connected with AXI bus, used for storing awid and awlen signals in the received write command sent by AW channel, awid represents ID of write command, each write command has corresponding ID value, awlen represents write data transmission length information in write command; the counting module is connected with the AXI bus and used for counting the actually received effective data and writing the recorded actual data transmission length information into the FIFO _ B; the input end of the FIFO _ B is connected with the output end of the counting module and used for storing the actual data receiving length information; the input end of the comparison module is respectively connected with the output ends of the FIFO _ A and the FIFO _ B and is used for comparing whether the length values stored in the FIFO _ A and the FIFO _ B are equal, if so, 0 is output, otherwise, 2 is output, wherein 0 represents correct, and 2 represents transmission error; the input end of the selector is respectively connected with the output end of the comparison module and the output end of the comparison module 2, the enabling end of the selector is connected with the lclk _ dis and the lrst, the lclk _ dis is a clock turn-off signal of the slave equipment module and effectively represents that the clock of the slave equipment module is turned off, the lrst is a reset signal of the slave equipment module and effectively represents that the slave equipment is in a reset state currently, if the current lclk _ dis or the lrst is effective, the comparison module 2 is selected to be output, otherwise, the comparison module result is output; the output of the selector is bresp, the id value in the FIFO _ A is directly assigned to bid, and bresp and bid are the write response returned by the device.
2. The AXI bus transfer apparatus capable of autonomously replying to write acknowledgement as recited in claim 1, wherein: the counting module is connected with a write data channel W of the AXI bus, and a last write signal wlast in the write data channel W determines the working state of the counting module; when the W channel receives valid data and the current wlast is invalid, the counting module starts counting from 0, when the W channel receives one valid data and the wlast signal is invalid, the counting value is added by 1, when the wlast is valid, the counting module writes the currently recorded actual data transmission length information into FIFO _ B, and the counter is cleared.
3. The AXI bus transfer apparatus capable of autonomously replying to write acknowledgement as recited in claim 1, wherein: FIFO _ A is connected with write command channel AW of AXI bus, AW channel receives effective AXI write command, and stores signal values of awid and awlen into FIFO _ A.
4. The AXI bus transfer apparatus capable of autonomously replying to write acknowledgement as recited in claim 1, wherein: and when neither FIFO _ A nor FIFO _ B is empty, the comparison module reads the values in the two FIFOs once, wherein the id value stored in the FIFO _ A is given to bid, and compares whether the length values stored in the two FIFOs are equal or not, if so, 0 is output, otherwise, 2 is output.
5. The autonomously replicable acknowledge AXI bus transfer apparatus as claimed in claim 1 or 3, characterized in that: the FIFO _ a may receive a plurality of AXI write commands continuously or intermittently, the counting module counting once for each write command.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910905083.1A CN110659236B (en) | 2019-09-24 | 2019-09-24 | AXI bus transmission device capable of autonomously replying write response |
| PCT/CN2019/111413 WO2021056631A1 (en) | 2019-09-24 | 2019-10-16 | Axi bus transmission apparatus capable of autonomously replying write response |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910905083.1A CN110659236B (en) | 2019-09-24 | 2019-09-24 | AXI bus transmission device capable of autonomously replying write response |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110659236A true CN110659236A (en) | 2020-01-07 |
| CN110659236B CN110659236B (en) | 2023-04-07 |
Family
ID=69038888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910905083.1A Active CN110659236B (en) | 2019-09-24 | 2019-09-24 | AXI bus transmission device capable of autonomously replying write response |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110659236B (en) |
| WO (1) | WO2021056631A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113254368A (en) * | 2021-07-15 | 2021-08-13 | 苏州浪潮智能科技有限公司 | Data writing method and data reading method from AXI bus to OPB bus |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853237A (en) * | 2010-05-31 | 2010-10-06 | 华为技术有限公司 | On-chip system and AXI bus transmission method |
| US20110106991A1 (en) * | 2009-10-29 | 2011-05-05 | Renesas Electronics Corporation | Bus system and bus control method |
| CN102799509A (en) * | 2012-07-10 | 2012-11-28 | 中国科学技术大学 | High-bandwidth extendable complex logic verification system based on double FPGA (Field- Programmable Gate Array) chips |
| CN103186492A (en) * | 2011-12-28 | 2013-07-03 | 联芯科技有限公司 | AXI (Advanced Extensible Interface) bus-based data consistency protection method and system |
| CN103605632A (en) * | 2013-11-18 | 2014-02-26 | 山东大学 | Method and device for communication between AXI (advanced extensible interface) bus and AHB (advanced high-performance bus) |
| CN105245398A (en) * | 2015-09-07 | 2016-01-13 | 上海交通大学 | Multichannel parallel detection system for massive LOC (Lab-on-Chip) signal processing |
| CN107577636A (en) * | 2017-09-12 | 2018-01-12 | 天津津航技术物理研究所 | A kind of AXI bus interface datas Transmission system and transmission method based on SOC |
| US10133549B1 (en) * | 2017-12-04 | 2018-11-20 | Kyocera Document Solutions Inc. | Systems and methods for implementing a synchronous FIFO with registered outputs |
| CN109471824A (en) * | 2018-11-22 | 2019-03-15 | 青岛方寸微电子科技有限公司 | Data transmission system and method based on AXI bus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5617429B2 (en) * | 2010-08-19 | 2014-11-05 | ソニー株式会社 | Bridge system for connecting the bus system and the bus system to the connected device |
| CN109446132A (en) * | 2018-12-04 | 2019-03-08 | 青岛方寸微电子科技有限公司 | A kind of interface bus device and data communication protocol |
-
2019
- 2019-09-24 CN CN201910905083.1A patent/CN110659236B/en active Active
- 2019-10-16 WO PCT/CN2019/111413 patent/WO2021056631A1/en active Application Filing
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110106991A1 (en) * | 2009-10-29 | 2011-05-05 | Renesas Electronics Corporation | Bus system and bus control method |
| CN101853237A (en) * | 2010-05-31 | 2010-10-06 | 华为技术有限公司 | On-chip system and AXI bus transmission method |
| CN103186492A (en) * | 2011-12-28 | 2013-07-03 | 联芯科技有限公司 | AXI (Advanced Extensible Interface) bus-based data consistency protection method and system |
| CN102799509A (en) * | 2012-07-10 | 2012-11-28 | 中国科学技术大学 | High-bandwidth extendable complex logic verification system based on double FPGA (Field- Programmable Gate Array) chips |
| CN103605632A (en) * | 2013-11-18 | 2014-02-26 | 山东大学 | Method and device for communication between AXI (advanced extensible interface) bus and AHB (advanced high-performance bus) |
| CN105245398A (en) * | 2015-09-07 | 2016-01-13 | 上海交通大学 | Multichannel parallel detection system for massive LOC (Lab-on-Chip) signal processing |
| CN107577636A (en) * | 2017-09-12 | 2018-01-12 | 天津津航技术物理研究所 | A kind of AXI bus interface datas Transmission system and transmission method based on SOC |
| US10133549B1 (en) * | 2017-12-04 | 2018-11-20 | Kyocera Document Solutions Inc. | Systems and methods for implementing a synchronous FIFO with registered outputs |
| CN109471824A (en) * | 2018-11-22 | 2019-03-15 | 青岛方寸微电子科技有限公司 | Data transmission system and method based on AXI bus |
Non-Patent Citations (1)
| Title |
|---|
| 任慈军: "基于AXI总线的DDR数据流量监控器的设计", 《中国优秀硕士学位论文全文数据库》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113254368A (en) * | 2021-07-15 | 2021-08-13 | 苏州浪潮智能科技有限公司 | Data writing method and data reading method from AXI bus to OPB bus |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021056631A1 (en) | 2021-04-01 |
| CN110659236B (en) | 2023-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1764703B1 (en) | A system for providing access to multiple data buffers of a data retaining and processing device | |
| CN100481043C (en) | Method, system, and program for handling input/output commands | |
| CN103064805B (en) | SPI controller and communication means | |
| CN1570907B (en) | Multiprocessor system | |
| EP3420462B1 (en) | Bus bridge for translating requests between a module bus and an axi bus | |
| CN102841869B (en) | Multi-channel I2C controller based on FPGA | |
| US20040205267A1 (en) | Bridge for removing master-induced stalls on a data bus | |
| CN109656851B (en) | System with time determination and comprising multiple high-speed bus channels and shared interface | |
| CN102147778A (en) | Data transmission system based on half-duplex serial bus and transmission control method | |
| CN102073611B (en) | I2C bus control system and method | |
| CN104714907A (en) | Design method for converting PCI bus into ISA bus or APB bus | |
| CN103235767B (en) | A kind of principal and subordinate MII management interface serial communication method | |
| CN110659236B (en) | AXI bus transmission device capable of autonomously replying write response | |
| CN105550131B (en) | A kind of interface data processing system and method based on finite state machine and ARINC659 buses | |
| CN103870415A (en) | Method and system for executing business on bus | |
| CN113946480A (en) | Detection device and method for I2C bus | |
| CN116414767B (en) | Reordering method and system for AXI protocol-based out-of-order response | |
| US4612541A (en) | Data transmission system having high-speed transmission procedures | |
| CN105446863A (en) | Electronic device with recording capability and circuit status recording method | |
| CN100514318C (en) | Bridge and data clearing method of electronic system | |
| CN101196859B (en) | Direct access memory device and direct access memory operation method | |
| CN113934671B (en) | Interface control chip and network equipment | |
| US6941408B2 (en) | Bus interface system with two separate data transfer interfaces | |
| CN103079094B (en) | The communication means of set top box main chip and front panel and Set Top Box | |
| CN114520729B (en) | Communication isolation system and communication isolation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |