CN110659037B - JTAG-based burning device - Google Patents

JTAG-based burning device Download PDF

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Publication number
CN110659037B
CN110659037B CN201910912881.7A CN201910912881A CN110659037B CN 110659037 B CN110659037 B CN 110659037B CN 201910912881 A CN201910912881 A CN 201910912881A CN 110659037 B CN110659037 B CN 110659037B
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controllable switch
jtag
chip
master
control
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CN110659037A (en
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王鹏
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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Priority to CN201910912881.7A priority Critical patent/CN110659037B/en
Priority to US17/615,522 priority patent/US11874323B2/en
Priority to PCT/CN2019/108475 priority patent/WO2021056401A1/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3656—Software debugging using additional hardware using a specific debug interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/008—Reliability or availability analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/25—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/06—Spare resources, e.g. for permanent fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/61—Installation
    • G06F8/63—Image based installation; Cloning; Build to order
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
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  • Software Systems (AREA)
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  • Environmental & Geological Engineering (AREA)
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  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention discloses a JTAG-based burning device, which comprises controllable switches arranged between a TDI end and a first chip of a JTAG host and between every two adjacent chips and a master controllable switch module arranged between every chip and a TDO end of the JTAG host, wherein the JTAG host can control the input end of the corresponding controllable switch to be connected with the corresponding output end of the corresponding controllable switch module according to a received burning instruction, and also control the output end of the master controllable switch module to be connected with the corresponding input end of the master controllable switch module.

Description

JTAG-based burning device
Technical Field
The invention relates to the technical field of JTAG, in particular to a JTAG-based burning device.
Background
JTAG (Joint Test Action Group) is an international standard Test protocol and is mainly used for testing the inside of a chip. Most advanced devices support JTAG protocol, such as DSP, FPGA and other devices. The standard JTAG interface is 4-wire: TMS, TCK, TDI and TDO, corresponding to mode selection, clock, data input and data output lines, respectively.
JTAG is originally used to Test a chip, and its basic principle is to define a TAP (Test Access Port) inside a device and Test internal nodes through a dedicated JTAG Test tool. JTAG test allows a plurality of devices to be connected in series through JTAG interfaces, namely, TDO of a previous JTAG device is connected to TDI of a next JTAG device to form a JTAG chain, so that each device is tested respectively.
Today, JTAG can also be used to firmware burn chips. Specifically, a plurality of JTAG devices are connected in series to form a JTAG chain, and a JTAG host, such as a BMC (Baseboard management Controller), performs firmware burning on chips (Integrated Circuit) such as a CPLD and an FPGA through the JTAG chain. However, some chips do not support the burning of the serial firmware, and the JTAG function of the chips is required to be used under the condition of being independently connected with a JTAG host, so that a plurality of circuits are required to be built when a plurality of chips are burnt, the test efficiency is reduced, and the circuit complexity is increased.
Disclosure of Invention
The invention aims to provide a JTAG-based burning device, which does not need manual regulation, improves the testing efficiency and simplifies the circuit structure.
In order to solve the technical problem, the invention provides a JTAG-based burning device, which comprises a JTAG host, N chips, a total controllable switch module and N controllable switches, wherein the JTAG host comprises a first chip, a second chip, a third chip and a fourth chip;
the input end of the first controllable switch is connected with the TDI end of the JTAG host, the first output end of the first controllable switch is connected with the TDI end of the first chip, and the second output end of the first controllable switch is connected with the TDI ends of the ith to Nth chips respectively; the input end of the ith controllable switch is connected with the TDO end of the ith-1 chip, the first output end of the ith controllable switch is connected with the ith-1 input end of the master controllable switch module, and the second output end of the ith controllable switch is connected with the TDI end of the ith chip; the output end of the Nth chip is connected with the Nth input end of the master controllable switch module, the output end of the master controllable switch module is connected with the TDO end of the JTAG host, and i is more than or equal to 2 and less than or equal to N;
the JTAG host is also respectively connected with the control ends of the N controllable switches and the control end of the master controllable switch module, and is used for controlling the input end of the corresponding controllable switch to be connected with the corresponding output end thereof according to the burning instruction and controlling the output end of the master controllable switch module to be connected with the corresponding input end thereof.
Preferably, the total controllable switch module comprises a total controllable switch;
the control end of the first controllable switch, the control end of the second controllable switch, the control end of the … Nth controllable switch and the control end of the main controllable switch are respectively connected with the control ends of the N +1 switches of the JTAG host in a one-to-one correspondence manner.
Preferably, the control terminal of the first controllable switch, the control terminal of the second controllable switch, and the control terminal of the … Nth controllable switch are respectively connected to N switch control terminals of the JTAG host;
the master controllable switch module comprises:
the total controllable switch comprises N input ends and an output end;
and the conversion module is used for generating a corresponding control instruction according to the control level output by the JTAG host so as to control the output end of the master controllable switch to be connected with the corresponding input end of the master controllable switch.
Preferably, N is 2, and the conversion module is a logic gate.
Preferably, the first controllable switch and the second controllable switch are both used for connecting the input end with the first output end when receiving a high level, and for connecting the input end with the second output end when receiving a low level;
the main controllable switch is used for connecting the output end with the second input end when receiving a high level and connecting the output end with the first input end when receiving a low level;
the logic gate is an exclusive-nor gate.
Preferably, the first controllable switch, the second controllable switch and the main controllable switch are single-pole double-throw switches.
Preferably, the distance between the first controllable switch and the second chip is less than 500 mil.
Preferably, the distance between the second controllable switch and the second chip is less than 500 mil.
Preferably, the distance between the first controllable switch and the second chip is less than 500 mils, and the distance between the second controllable switch and the second chip is less than 500 mils.
Preferably, the burning device further comprises a prompting module;
and the JTAG host is also used for generating information of the chip to be burned according to the burning command and sending the information to the prompting module.
The invention provides a JTAG-based burning device, which comprises controllable switches arranged between a TDI end and a first chip of a JTAG host and between every two adjacent chips and a master controllable switch module arranged between every chip and a TDO end of the JTAG host, wherein the JTAG host can control the input end of the corresponding controllable switch to be connected with the corresponding output end of the JTAG host according to a received burning instruction and also control the output end of the master controllable switch module to be connected with the corresponding input end of the master controllable switch module.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a JTAG-based burning device according to the present invention;
FIG. 2 is a schematic diagram of another JTAG-based burning apparatus according to the present invention;
FIG. 3 is a schematic structural diagram of another JTAG-based burning device provided by the present invention.
Detailed Description
The core of the invention is to provide a JTAG-based burning device, which does not need manual regulation, improves the testing efficiency and simplifies the circuit structure.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a JTAG-based recording device according to the present invention, where the recording device includes a JTAG host 1, N chips, a master controllable switch module 2, and N controllable switches;
the input end of the first controllable switch K1 is connected with the TDI end of the JTAG host 1, the first output end is connected with the TDI end of the first chip IC1, and the second output end is respectively connected with the TDI ends of the i-th to N-th chips ICN; the input end of the ith controllable switch is connected with the TDO end of the ith-1 chip, the first output end of the ith controllable switch is connected with the ith-1 input end of the master controllable switch module 2, and the second output end of the ith controllable switch is connected with the TDI end of the ith chip; the output end of the N chip ICN is connected with the N input end of the total controllable switch module 2, the output end of the total controllable switch module 2 is connected with the TDO end of the JTAG host 1, and i is more than or equal to 2 and less than or equal to N;
the JTAG host 1 is further connected to the control terminals of the N controllable switches and the control terminal of the master controllable switch module 2, respectively, and is configured to control the input terminals of the corresponding controllable switches to be connected to the corresponding output terminals thereof according to the burning command, and control the output terminals of the master controllable switch module 2 to be connected to the corresponding input terminals thereof.
In order to burn a plurality of chips, for the chips which do not support burning of serial firmware, different from the prior art in which the chips are separately connected with a JTAG host 1 for burning, only one master circuit is built in the application, specifically, controllable switches are respectively arranged between a TDI end of the JTAG host 1 and a first chip IC1 and between each two adjacent chips, a master controllable switch module 2 is arranged between each chip and a TDO end of the JTAG host 1, and in addition, an output end of the controllable switch connected with the TDI end of the JTAG host 1 is connected with the TDI ends of other chips besides the TDI end of the first chip IC 1. The input end of each controllable switch is optionally connected with the output end thereof, and the input end of the main controllable switch module 2 is optionally connected with the output end thereof.
When the controllable switch module 2 is applied, a user only needs to input a burning command, the JTAG host 1 can control the input end of the corresponding controllable switch to be connected with the corresponding output end thereof according to the burning command, and control the output end of the main controllable switch module 2 to be connected with the corresponding input end thereof. The burning command may specifically include a command for burning which chip or chips are to be burned. For example, the burning command is a command for burning all chips capable of burning firmware in series, the JTAG host 1 controls the connection of the corresponding input and output terminals of the corresponding controllable switches to realize that the chips to be burned are connected in series to form a JTAG chain, the JTAG host 1 also controls the input terminal of the master controllable switch module 2 connected to the output terminal of the last chip in the JTAG chain to be connected to the output terminal of the master controllable switch module 2, and then, the JTAG host 1 can burn firmware in the JTAG chain. In addition, the burning command may also be a command for burning a single chip that does not support burning of serial firmware, and at this time, the JTAG host 1 may control the input terminal of the first controllable switch K1 to be connected to the output terminal connected to the chip to be burned, and control the input terminal of the controllable switch at the rear end of the chip to be burned to be connected to the output terminal connected to the master controllable switch module 2, and simultaneously control the input terminal of the master controllable switch module 2 connected to the chip to be burned through the controllable switch to be connected to the output terminal thereof, thereby implementing the JTAG host 1 to burn firmware alone on the chip to be burned.
Referring to fig. 2, the operation principle of the present application will be described, and fig. 2 is a schematic structural diagram of another JTAG-based recording apparatus provided in the present invention.
Supposing that firmware burning needs to be performed on both the first chip IC1 and the second chip IC2, at this time, the JTAG host 1 controls the input end a of the first controllable switch K1 to be connected with the first output end B1, also controls the input end a of the second controllable switch K2 to be connected with the first output end B1, and also controls the second input end B2 of the master controllable switch module 2 to be connected with the output end a thereof, and through this way, the JTAG host 1 can perform serial firmware burning on the first chip IC1 and the second chip IC 2.
Assuming that firmware burning is only required to be performed on the first chip IC1, at this time, the JTAG host 1 controls the input terminal a of the first controllable switch K1 to be connected to the first output terminal B1, controls the input terminal a of the second controllable switch K2 to be connected to the second output terminal B2, and controls the first input terminal B1 of the master controllable switch 21 to be connected to the output terminal a thereof, and through this way, the JTAG host 1 can perform firmware burning on the first chip IC 1.
Assuming that firmware burning is only required to be performed on the second chip IC2, at this time, the JTAG host 1 controls the input end a of the first controllable switch K1 to be connected to the second output end B2, controls the input end of the second controllable switch K2 to be connected to the second output end B2 (to prevent signals in the first chip IC1 from being transmitted to the second chip IC2 and interfering with burning of the second chip IC 2), and controls the second input end B2 of the master controllable switch 21 to be connected to the output end a thereof, so that the JTAG host 1 can perform firmware burning on the second chip IC 2.
In summary, the invention provides a JTAG-based burning apparatus, which includes controllable switches disposed between the TDI terminal of a JTAG host 1 and a first chip IC1, and between each two adjacent chips, and further includes a total controllable switch module 2 disposed between each chip and the TDO terminal of the JTAG host 1, the JTAG host 1 can control the corresponding controllable switch input terminal to connect with its corresponding output terminal according to a received burning instruction, and also control the output terminal of the total controllable switch module 2 to connect with its corresponding input terminal, therefore, the present application only needs to build a circuit, can automatically realize the adjustment of the JTAG link by controlling the connection relationship of the input and output terminals of the corresponding switch, and realizes the switching of the JTAG circuit between the serial topology and the parallel topology, thereby realizing the burning of firmware of different chips or chip combinations, without manual adjustment, and improving the testing efficiency, the circuit structure is simplified.
On the basis of the above-described embodiment:
as a preferred embodiment, the total controllable switch module 2 comprises a total controllable switch 21;
the control end of the first controllable switch K1, the control end of the second controllable switch K2, the control end of the … nth controllable switch KN and the control end of the master controllable switch 21 are respectively connected with the N +1 switch control ends of the JTAG host 1 in a one-to-one correspondence manner.
Specifically, the master controllable switch module 2 may only include one master controllable switch 21, the control end of the master controllable switch 21 and the control end of the first controllable switch K1, the control end of the second controllable switch K2, and the control end of the … nth controllable switch KN are directly connected to N +1 switch control ends of the JTAG host 1, and at this time, the JTAG host 1 directly controls the N controllable switches and the master controllable switch 21, and conversion by other devices is not required, so that reliability of switch control is improved.
As a preferred embodiment, the control terminal of the first controllable switch K1, the control terminal of the second controllable switch K2, and the control terminal of the … nth controllable switch KN are respectively connected to N switch control terminals of the JTAG host 1;
the total controllable switch module 2 comprises:
a master controllable switch 21 including N input terminals, one output terminal;
and the conversion module is used for generating a corresponding control instruction according to the control level output by the JTAG host 1 so as to control the output end of the master controllable switch 21 to be connected with the corresponding input end of the master controllable switch 21.
It is not difficult to obtain, which input end and output end of the master controllable switch 21 are connected with the input and output ends of other controllable switches has a logical relationship, based on the logical relationship, the master controllable switch module 2 comprises the master controllable switch 21 and a conversion module, the input end of the conversion module is connected with the N switch control ends of the JTAG host 1, the output end is connected with the control end of the master controllable switch 21, and is used for converting the control level output by the JTAG host 1 into a corresponding control instruction according to the logical relationship, and further controlling the output end of the master controllable switch 21 to be connected with the corresponding input end, so that the structure of the JTAG host 1 is simplified by one pin of the JTAG host 1.
In a preferred embodiment, N is 2, and the conversion module is a logic gate.
In order to implement corresponding logic conversion on each control level output by the JTAG host 1, in this embodiment, the conversion module may be a logic gate, and the logic gate has the advantage of low cost and low power consumption.
In a preferred embodiment, the first controllable switch K1 and the second controllable switch K2 are both configured to connect the input terminal to the first output terminal when receiving a high level, and to connect the input terminal to the second output terminal when receiving a low level;
the master controllable switch 21 is used for connecting the output end with the second input end when receiving a high level and connecting the output end with the first input end when receiving a low level;
the logic gate is an exclusive or gate 22.
Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of another JTAG-based recording apparatus provided in the present invention.
In this embodiment, the logic gate is an exclusive OR gate 22, and the truth table of the exclusive OR gate 22 is as follows
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
It is not difficult to obtain, the JTAG host 1 outputs a high level to the first controllable switch K1 and the second controllable switch K2, respectively, so that when the first chip IC1 and the second chip IC2 are connected in series, two input ends of the exclusive nor gate 22 are at the high level, the output is at the high level, and the output end a of the master controllable switch 21 is connected with the second input end B2, thereby implementing the serial firmware burning of the first chip IC1 and the second chip IC2 by the JTAG host 1.
The JTAG host 1 outputs a high level to the first controllable switch K1 and a low level to the second controllable switch K2 to perform firmware burning only on the first chip IC1, then one of the two input terminals of the exclusive or gate 22 is a high level and the other is a low level, and the output thereof is a low level, and at this time, the output terminal a of the master controllable switch 21 is connected with the first input terminal B1, so that the JTAG host 1 can perform firmware burning only on the first chip IC 1. At this time, the output terminal of the second chip IC2 and the second input terminal B2 of the master controllable switch 21 are in a connected state, but the connection between the JTAG host 1 and the first chip IC1 is not affected due to the isolation of the master controllable switch 21.
The JTAG host 1 outputs a low level to the first controllable switch K1 and outputs a low level to the second controllable switch K2 to perform firmware burning only on the second chip IC2, both input ends of the exclusive-nor gate 22 are at a low level at this time, the output thereof is at a high level, and the output end a of the master controllable switch 21 is connected to the second input end B2 at this time, so that the JTAG host 1 can perform firmware burning only on the second chip IC 2. At this time, the output terminal of the first chip IC1 and the first input terminal B1 of the master controllable switch 21 are in a connected state, but the connection between the JTAG host 1 and the second chip IC2 is not affected due to the isolation of the master controllable switch 21.
Therefore, the burning control of each chip can be realized through the method, and the control method is simple and reliable.
As a preferred embodiment, the first controllable switch K1, the second controllable switch K2 and the total controllable switch 21 are single-pole double-throw switches.
Specifically, the first controllable switch K1, the second controllable switch K2 and the main controllable switch 21 are all single-pole double-throw switches, and the single-pole double-throw switches have the advantages of simple structure and high reliability. Of course, the first controllable switch K1, the second controllable switch K2 and the overall controllable switch 21 may be other types of switches, and the present application is not limited thereto.
In a preferred embodiment, the distance between the first controllable switch K1 and the second chip IC2 is less than 500 mils.
In a preferred embodiment, the distance between the second controllable switch K2 and the second chip IC2 is less than 500 mils.
In a preferred embodiment, the distance between the first controllable switch K1 and the second chip IC2 is less than 500mil, and the distance between the second controllable switch K2 and the second chip IC2 is less than 500 mil.
Specifically, considering that the recording device may generate stub signals during operation to affect the signal quality of TDI/TDO, referring to fig. 3, for example, when the first chip IC1 and the second chip IC2 are recorded in series firmware, the stub portion is located between the point D and the point B2 of the second output terminal B2 of the first controllable switch K1; when only the first chip IC1 is subjected to firmware burning, the stub part does not exist in the circuit; when only the second chip IC2 is to be burned, the first output terminal B1 to the point D of the second controllable switch K2 is the stub portion.
In order to reduce the influence of stub on the signal quality of TDI/TDO as much as possible, layout of layout should be designed according to the following principle: the second controllable switch K2 is disposed near the second chip IC2, and the first controllable switch K1 is disposed near the second chip IC 2. Based on this, the present implementation finds, through a large number of simulation experiments, that when the distance between the first controllable switch K1 and the second chip IC2 is less than 500 mils, and/or the distance between the second controllable switch K2 and the second chip IC2 is less than 500 mils, the effect of stub on the signal quality of TDI/TDO is small. The specific distance between the first controllable switch K1 and the second chip IC2 and the specific distance between the second controllable switch K2 and the second chip IC2 are not particularly limited in this embodiment, and are determined according to practical situations.
Therefore, the method can effectively reduce the influence of stub on the signal quality of TDI/TDO, and improve the signal transmission quality of TDI/TDO.
As a preferred embodiment, the burning device further comprises a prompt module;
the JTAG host 1 is also used for generating information of the chip to be burned according to the burning command and sending the information to the prompt module.
Specifically, in order to facilitate the user to know the information of the chip to be burned currently, for example, the serial number of the chip to be burned, in this embodiment, the burning device further includes a prompting module for prompting the information of the chip to be burned generated according to the burning command, so as to improve the user experience.
The prompting module here can be, but is not limited to, a display screen.
It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A burning device based on JTAG is characterized by comprising a JTAG host, N chips, a master controllable switch module and N controllable switches;
the input end of the first controllable switch is connected with the TDI end of the JTAG host, the first output end of the first controllable switch is connected with the TDI end of the first chip, and the second output end of the first controllable switch is connected with the TDI ends of the ith to Nth chips respectively; the input end of the ith controllable switch is connected with the TDO end of the ith-1 chip, the first output end of the ith controllable switch is connected with the ith-1 input end of the master controllable switch module, and the second output end of the ith controllable switch is connected with the TDI end of the ith chip; the output end of the Nth chip is connected with the Nth input end of the master controllable switch module, the output end of the master controllable switch module is connected with the TDO end of the JTAG host, and i is more than or equal to 2 and less than or equal to N;
the JTAG host is also respectively connected with the control ends of the N controllable switches and the control end of the master controllable switch module, and is used for controlling the input end of the corresponding controllable switch to be connected with the corresponding output end thereof according to the burning instruction and controlling the output end of the master controllable switch module to be connected with the corresponding input end thereof.
2. The JTAG-based programming device of claim 1, wherein the master controllable switch module includes a master controllable switch;
the control end of the first controllable switch, the control end of the second controllable switch, the control end of the … Nth controllable switch and the control end of the main controllable switch are respectively connected with the control ends of the N +1 switches of the JTAG host in a one-to-one correspondence manner.
3. The JTAG-based burning device of claim 1, wherein a control terminal of the first controllable switch, a control terminal of the second controllable switch, and a control terminal of the … Nth controllable switch are respectively connected to N switch control terminals of the JTAG host;
the master controllable switch module comprises:
the total controllable switch comprises N input ends and an output end;
and the conversion module is used for generating a corresponding control instruction according to the control level output by the JTAG host so as to control the output end of the master controllable switch to be connected with the corresponding input end of the master controllable switch.
4. The JTAG-based programming device of claim 3, wherein N is 2 and the converting module is a logic gate.
5. The JTAG-based programming device of claim 4, wherein the first controllable switch and the second controllable switch are both configured to have an input connected to the first output when receiving a high level and to have an input connected to the second output when receiving a low level;
the main controllable switch is used for connecting the output end with the second input end when receiving a high level and connecting the output end with the first input end when receiving a low level;
the logic gate is an exclusive-nor gate.
6. The JTAG-based programming device of claim 4, wherein the first controllable switch, the second controllable switch, and the master controllable switch are single-pole double-throw switches.
7. The JTAG-based programming device of any one of claims 2 to 6, wherein a distance between the first controllable switch and the second chip is less than 500 mils.
8. The JTAG-based programming device of any one of claims 2 to 6, wherein a distance between the second controllable switch and the second chip is less than 500 mils.
9. The JTAG-based programming device of any one of claims 2 to 6, wherein a distance between the first controllable switch and the second chip is less than 500 mils, and a distance between the second controllable switch and the second chip is less than 500 mils.
10. The JTAG-based programming device of claim 1, further comprising a hint module;
and the JTAG host is also used for generating information of the chip to be burned according to the burning command and sending the information to the prompting module.
CN201910912881.7A 2019-09-25 2019-09-25 JTAG-based burning device Active CN110659037B (en)

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