CN110649031B - Three-dimensional memory, preparation method thereof and photoetching mask - Google Patents
Three-dimensional memory, preparation method thereof and photoetching mask Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 105
- 238000011049 filling Methods 0.000 claims abstract description 91
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- 230000003139 buffering effect Effects 0.000 claims description 54
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- 238000005530 etching Methods 0.000 claims description 13
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 12
- 239000000945 filler Substances 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 10
- 239000011159 matrix material Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 description 24
- 239000004065 semiconductor Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
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- 238000000206 photolithography Methods 0.000 description 3
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- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
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- 229910052681 coesite Inorganic materials 0.000 description 1
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- 229910052906 cristobalite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
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- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
The embodiment of the invention discloses a three-dimensional memory, a preparation method thereof and a photoetching mask plate; wherein the three-dimensional memory comprises: a plurality of memory cell regions arranged at intervals; a filling material layer filled between the memory cell regions for electrically isolating the memory cell regions; a conductive plug penetrating the filling material layer and electrically connected with the gate layer in the memory unit region; and a stress buffer structure formed in the step of forming the conductive plug, wherein the stress buffer structure is located in the filling material layer and comprises a part which is arranged at a preset distance from the side wall of at least one memory cell region so as to buffer the stress influence of the filling material layer on the side wall of the memory cell region.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory, a preparation method thereof and a photoetching mask.
Background
Memory (Memory) is a Memory device used in modern information technology to store information. With the increasing demands of various electronic devices for integration and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the demands, and in such a situation, a three-dimensional (3D) memory has come into play.
In the preparation of the three-dimensional memory, a stacked structure is mainly formed on a substrate, and the stacked structure is divided into a plurality of memory cell areas arranged at intervals along the plane direction of the substrate, so that a memory array is formed; step areas (SS areas) are formed around the memory cell areas, so that each layer of gate electrodes in the memory cell areas are electrically connected with vertical conductive plugs (contacts, CTs) through corresponding step surfaces, and therefore, the addressing operation of each layer of gate electrodes corresponding to the memory cell areas is achieved. Above the step regions and between the memory cell regions, a layer of filler material needs to be formed, which provides a planar top surface for the device structure.
However, the current process for fabricating three-dimensional memory is highly affected by local stress, because the periphery of the memory cell region is filled with a filling material layer; due to the process, the filling material layer is easy to deform in the subsequent high-temperature annealing process, so that the memory cell region is extruded. In addition, since the top pattern of the memory cell region is a large-sized Block (GB), it is often used as an Overlay (OVL) marker in the photolithography process; once the memory cell area boundary is deformed by extrusion, overlay deviation is directly caused, and the product yield is reduced.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a three-dimensional memory, a method for manufacturing the same, and a photolithography mask to solve at least one of the problems in the background art.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
an embodiment of the present invention provides a three-dimensional memory, including:
a plurality of memory cell regions arranged at intervals;
a filling material layer filled between the memory cell regions for electrically isolating the memory cell regions;
a conductive plug penetrating the filling material layer and electrically connected with the gate layer in the memory unit region; and the number of the first and second groups,
and a stress buffer structure formed in the step of forming the conductive plug, wherein the stress buffer structure is located in the filling material layer and includes a portion spaced apart from a sidewall of at least one memory cell region by a predetermined distance, so as to buffer the stress influence of the filling material layer on the sidewall of the memory cell region.
In the above scheme, the shape of the stress buffering structure is the same as that of the conductive plug.
In the above scheme, the minimum structural dimension of the stress buffering structure is greater than or equal to the minimum structural dimension of the conductive plug.
In the above scheme, the preset distance is in the range of 5-20 μm.
In the above scheme, the filling material layer includes a TEOS layer.
The embodiment of the invention also provides a preparation method of the three-dimensional memory, which comprises the following steps:
forming a plurality of storage unit areas which are arranged at intervals;
filling and forming a filling material layer between the memory cell regions;
etching the filling material layer to form a stress buffer structure hole; the stress buffer structure hole comprises a part which is arranged at a preset distance from the side wall of at least one memory cell area;
filling the stress buffer structure holes to form a stress buffer structure; the stress buffer structure is used for buffering the stress influence of the filling material layer on the side wall of the memory unit area;
etching the filling material layer, and forming a conductive plug hole which penetrates through the filling material layer and exposes the gate layer in the memory unit region; and/or, the filling the stress buffering structure hole and the filling the conductive plug hole of the three-dimensional memory to form a conductive plug are carried out in the same process, and the conductive plug is conductively connected with the grid layer of the three-dimensional memory.
In the above aspect, the shape of the stress buffering structure hole is the same as the shape of the conductive plug hole.
In the above aspect, the minimum structural dimension of the stress buffering structure is greater than or equal to the minimum structural dimension of the conductive plug hole.
In the above scheme, the preset distance is in the range of 5-20 μm.
In the above scheme, the filling material layer includes a TEOS layer.
The embodiment of the invention also provides a photoetching mask plate which is applied to the etching process of the conductive plug hole of the three-dimensional memory and comprises the following steps:
the first pattern area corresponds to a preset forming position of a conductive plug of the three-dimensional memory;
a second pattern region corresponding to a preset forming position of a stress buffer structure of the three-dimensional memory; the stress buffer structure is positioned in a filling material layer filled between the memory cell areas of the three-dimensional memory and comprises a part which is arranged at a preset distance from the side wall of at least one memory cell area; the stress buffer structure is used for buffering the stress influence of the filling material layer on the side wall of the storage unit area;
the exposure setting in the first pattern area is the same as the exposure setting in the second pattern area.
In the above scheme, the shape of the second pattern region is the same as the shape of the first pattern region.
In the above solution, the minimum feature size of the second pattern region is greater than or equal to the minimum feature size of the first pattern region.
In the above scheme, the preset distance is in the range of 5-20 μm.
The three-dimensional memory and the preparation method thereof and the photoetching mask provided by the embodiment of the invention are provided; wherein the three-dimensional memory comprises: a plurality of memory cell regions arranged at intervals; a filling material layer filled between the memory cell regions for electrically isolating the memory cell regions; a conductive plug penetrating the filling material layer and electrically connected with the gate layer in the memory unit region; and a stress buffer structure formed in the step of forming the conductive plug, wherein the stress buffer structure is located in the filling material layer and comprises a part which is arranged at a preset distance from the side wall of at least one memory cell region so as to buffer the stress influence of the filling material layer on the side wall of the memory cell region. Therefore, the stress buffer structure is arranged between the storage unit areas, the large filling material layers are isolated, the stress of the filling material layers is relieved, the filling material layers are prevented from extruding the storage unit areas, and the product yield is finally improved; the stress buffer structure is formed in the forming process of the conductive plug of the three-dimensional memory, so that the process steps are saved, and the preparation cost is saved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram illustrating a layout of memory cell regions of a three-dimensional memory according to the related art;
FIG. 2 is a cross-sectional view of a three-dimensional memory structure according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating an arrangement of memory cell regions of a three-dimensional memory according to an embodiment of the invention;
fig. 4 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Fig. 1 is a schematic diagram illustrating a layout of a memory cell region of a three-dimensional memory according to the related art. As shown, memory cell regions are arranged at intervals on a substrate, thereby forming a memory array; several adjacent memory cell regions in the memory array form a memory plane, for example, as shown by oval boxes in fig. 1, four longitudinally arranged memory cell regions form a memory plane. A step region is formed around the memory cell region; above the step region and between the memory cell regions, a filling material layer, such as a Tetraethylorthosilicate (TEOS) layer, is formed.
Due to process reasons, the filling material layer is easy to deform in a subsequent high-temperature annealing process, so that the memory cell region is extruded; as shown in fig. 1, both sides of the memory cell region are pressed and deformed in the direction of the arrow. Not only causes stress trouble to the memory cell area, but also directly influences the alignment precision in the subsequent photoetching process and reduces the product yield.
Based on this, the embodiment of the invention provides a three-dimensional memory; please refer to fig. 2. As shown, the three-dimensional memory includes: a plurality of memory cell regions arranged at intervals; a filling material layer 12 filled between the memory cell regions for electrically isolating the memory cell regions; a conductive plug (conductive plug is not formed in the direction shown in the drawing, for example, and thus is not shown) extending through the filling material layer 12 and electrically connected to the gate layer 112 in the memory cell region; and a stress buffering structure 13 formed in the conductive plug forming process, wherein the stress buffering structure 13 is located in the filling material layer 12 and includes a portion spaced apart from a sidewall of at least one memory cell region by a predetermined distance d, so as to buffer a stress influence of the filling material layer 12 on the sidewall of the memory cell region.
As can be understood, the embodiment of the invention separates the bulk filling material layer by arranging the stress buffer structure in the filling material layer, relieves the stress of the filling material layer, avoids the extrusion of the filling material layer on the memory cell area, and finally improves the yield of products; the stress buffer structure is formed in the forming process of the conductive plug of the three-dimensional memory, so that the process steps are saved, and the preparation cost is saved.
In one embodiment, the plurality of memory cell regions arranged at intervals are formed by dividing a stacked structure 11; the stacked structure 11 is formed on a substrate 10.
Here, the substrate 10 may be a semiconductor substrate; specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
The stacked structure 11 may include a plurality of dielectric layers 111 and gate layers 112 arranged alternately.
The material of the dielectric layer 111 includes, but is not limited to, silicon oxide, silicon nitride layer, silicon oxynitride, etc.; as a specific implementation manner, the material of the dielectric layer 111 is SiO2. The material of the gate layer 112 includes, but is not limited to, metal tungsten (W).
The memory cell region is a memory region on the substrate 10 and insulated and isolated from each other. The memory cell area may also be referred to as an array memory area; the shape of each memory cell region is, for example, a rectangle or a square. The memory cell region includes a plurality of channel structures formed in Channel Holes (CH) and at least one Array Common Source (ACS). The CH penetrates through the stacked structure 11, and the channel structure provides a channel for the flow of carriers for each stacked gate layer; the drain electrode of the memory cell region can be positioned at the top of the CH and is connected with the channel structure; the ACS is the source of the memory cell area. In practical application, the circulation path of the current in the three-dimensional memory is as follows: CH top drain-CH inner channel structure-lower select transistor channel layer SEG-substrate-ACS.
The filling material layer 12 is filled between the memory cell regions to electrically isolate the memory cell regions; therefore, the filler material layer 12 may also be referred to as a space insulating layer. The material of the filling material layer 12 is an insulating material, and the dielectric constant is, for example, 4 or more; and may specifically comprise a silicon oxide material, including TEOS for example.
The lower surface of the filler material layer 12 is in contact with the upper surface of the substrate 10; the upper surface of the filler material layer 12 is located above the upper surface of the memory cell region (specifically, the upper surface of the stacked structure 11), and it should be understood that the above includes the case where the two are coplanar, i.e., the filler material layer 12 provides a flat top surface for the device structure after dividing the memory cell region. In one embodiment, a step region is formed around the memory cell region, and the filling material layer 12 is filled on the step region and on the substrate 10 between the memory cell regions.
The stress buffering structure 13 is located in the filling material layer 12, and particularly may be located in a portion of the filling material layer 12 that is not filled above the step region; in other words, the functional structure of the three-dimensional memory, specifically the stacked structure of the step region, is not located between the lower surface of the stress buffer structure 13 and the upper surface of the substrate 10. In the structure shown in fig. 2, although the lower surface of the stress buffering structure 13 is in direct contact with the upper surface of the substrate 10; however, in other embodiments, the stress buffering structure 13 may not be in contact with the substrate 10, and the filler material layer 12 or other insulating material may be included between the stress buffering structure 13 and the substrate 10; the stress buffering structure 13 is preferably insulated from the substrate 10.
The stress buffer structure 13 is located in the filling material layer 12 between the memory cell regions, and obviously, the forming position of the stress buffer structure 13 is not coincident with the forming position of the memory cell region on the substrate 10; specifically, the stress buffer structure 13 is not formed in a channel via hole in the memory cell region, nor in a gate slit (a position where ACS is formed) in the memory cell region.
The forming process of the conductive plug of the three-dimensional memory can be integrally divided into two parts: etching and filling; etching the filling material layer, forming a conductive plug hole at a preset forming position of the conductive plug, wherein the conductive plug hole penetrates through the filling material layer and exposes the gate layer in the memory cell region; the step of filling specifically includes filling a conductive material in the conductive plug hole to form a conductive plug. The step of forming the stress buffering structure 13 in the step of forming the conductive plug of the three-dimensional memory may be completely the same as the step of forming the conductive plug of the three-dimensional memory, or the step of forming the stress buffering structure 13 may be partially the same as the step of forming the conductive plug of the three-dimensional memory. Specifically, in the step of etching the filling material layer to form the conductive plug hole at the preset forming position of the conductive plug of the three-dimensional memory, a stress buffer structure hole may be further etched and formed at a position spaced by a preset distance from the sidewall of at least one memory cell region; and/or, the stress buffering structure can be formed by filling the stress buffering structure hole during the step of filling the conductive plug hole to form a conductive plug. It is to be understood that, in this embodiment, the material of the stress buffering structure 13 is the same as the material of the conductive plug of the three-dimensional memory, for example, both comprise tungsten. In other embodiments, all or part of the material of the stress buffering structure 13 may also be adjusted according to actual needs, that is, a part of the process for filling the stress buffering structure hole is added in the step of filling the part in the process of forming the conductive plug, so that all or part of the material different from the conductive plug is formed in the stress buffering structure hole. The stress buffering structure 13 may also be referred to as a dummy conductive plug structure.
In a specific embodiment, the shape of the stress buffering structure 13 is the same as the shape of the conductive plug; for example, the stress buffering structure and the conductive plug are both cylindrical in shape.
In order to be compatible with the process of the conductive plug, the minimum structure size of the stress buffering structure 13 is greater than or equal to the minimum structure size of the conductive plug. Preferably, the minimum structural dimension of the stress buffering structure 13 is equal to the minimum structural dimension of the conductive plug; for example, in the embodiment where the conductive plug is cylindrical in shape, the stress buffering structure 13 is cylindrical with a cross-sectional diameter equal to the diameter of the conductive plug. In addition, as for the relationship between the depth of the stress buffering structure 13 and the depth of the conductive plug, the present embodiment is not particularly limited.
In one embodiment, the predetermined distance d is in a range of 5-20 μm.
In an embodiment, the stress buffering structures 13 are distributed in a matrix within the filling material layer 12. Fig. 3 shows a schematic layout of a memory cell region of a three-dimensional memory. As shown, the stress buffer structures are distributed in a matrix within the layer of filling material (specifically TEOS), in particular between at least two adjacent memory cell regions GB. In the matrix, the distance between the stress buffer structure closest to the side wall of the memory cell region and the side wall is the preset distance d. The arrangement density of the stress buffering structures can be adjusted according to the size of the filling material layer and the material property (mainly the stress magnitude of the material) of the filling material layer; in one embodiment, the distance between two adjacent stress buffering structures may be equal to the structural size of the stress buffering structure; for example, in the embodiment where the conductive plug is cylindrical in shape, the distance between two adjacent stress buffering structures may be equal to the cross-sectional diameter of the stress buffering structure.
The above is only one preferred embodiment of the distribution of the stress buffering structure; it should be noted that, the embodiment of the present invention does not exclude the case that the stress buffering structure only includes one stress buffering structure distributed between at least two adjacent memory cell regions, and the stress buffering structure is disposed at a predetermined distance from the sidewall of at least one memory cell region (preferably, the stress buffering structure is disposed at the predetermined distance from the sidewall of two adjacent memory cell regions adjacent to each other); in other embodiments, the number and the arrangement direction of the stress buffering structures are not limited.
Fig. 2 to 3 only show that the stress buffering structures are located on two sides of the memory cell region along the length direction of the memory plane (i.e. the longitudinal direction in fig. 3), which is related to the layout of the memory cell region in practical applications. The memory cell region is generally provided with a step region at a sidewall in a width direction (i.e., a lateral direction in fig. 3) of the memory plane, that is, a conductive plug conductively connected to the gate layer is mainly distributed outside the sidewall in the lateral direction of the memory cell region; in the transverse direction, the area of the filling material layer is not large due to the existence of the step region, and in this case, the stress buffer structure may be disposed only on both sides of the memory cell region in the longitudinal direction in fig. 3.
In a specific embodiment, the filler material layer comprises a TEOS layer.
The embodiment of the invention also provides a preparation method of the three-dimensional memory; refer specifically to FIG. 4. As shown, the method comprises the steps of:
etching the filling material layer, and forming a conductive plug hole which penetrates through the filling material layer and exposes the gate layer in the memory unit region; and/or, the filling the stress buffering structure hole and the filling the conductive plug hole of the three-dimensional memory to form a conductive plug are carried out in the same process, and the conductive plug is conductively connected with the grid layer of the three-dimensional memory.
As can be understood, the embodiment of the invention separates the bulk filling material layer by arranging the stress buffer structure in the filling material layer, relieves the stress of the filling material layer, avoids the extrusion of the filling material layer on the memory cell area, and finally improves the yield of products; the stress buffer structure is formed in the forming process of the conductive plug of the three-dimensional memory, so that the process steps are saved, and the preparation cost is saved.
In an embodiment, the method further comprises: providing a substrate; forming a stack layer on the substrate; and etching the stacked layer to form the plurality of memory unit areas arranged at intervals.
Here, the substrate may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
The stacked layers may be the same as the stacked structure 11 in the above-described embodiment, or may be different from the stacked structure 11. Specifically, the stacked layer and the stacked structure 11 may be structures on the surface of the substrate in the same or different processes. The stacked layer is not limited to the case of including a plurality of dielectric layers and dummy gate layers which are alternately arranged; the embodiment of the application does not exclude the situation that a plurality of alternately arranged dielectric layers and gate layers are directly formed on the substrate, namely, the gate layers are formed by refilling gate materials without removing the dummy gate layers subsequently.
The material of the stress buffer structure is the same as that of the conductive plug of the three-dimensional memory, for example, the stress buffer structure and the conductive plug of the three-dimensional memory both comprise tungsten.
In a specific embodiment, the shape of the stress buffering structure hole is the same as the shape of the conductive plug hole; for example, both circular in cross-section.
In a specific embodiment, the minimum structural dimension of the stress buffering structure is equal to or greater than the minimum structural dimension of the conductive plug aperture.
In one embodiment, the predetermined distance is in a range of 5-20 μm.
In a specific embodiment, the filler material layer comprises a TEOS layer.
The embodiment of the invention also provides a photoetching mask plate which is applied to the etching process of the conductive plug hole of the three-dimensional memory and comprises the following steps:
the first pattern area corresponds to a preset forming position of a conductive plug of the three-dimensional memory;
a second pattern region corresponding to a preset forming position of a stress buffer structure of the three-dimensional memory; the stress buffer structure is positioned in a filling material layer filled between the memory cell areas of the three-dimensional memory and comprises a part which is arranged at a preset distance from the side wall of at least one memory cell area; the stress buffer structure is used for buffering the stress influence of the filling material layer on the side wall of the storage unit area;
the exposure setting in the first pattern area is the same as the exposure setting in the second pattern area.
Here, the structure of the photolithography mask may refer to the memory cell region layout of the three-dimensional memory in fig. 3. And the position of the stress buffer area corresponds to the second pattern area on the photoetching mask plate.
It can be understood that the exposure setting in the first pattern area is the same as the exposure setting in the second pattern area, which means that the first pattern area and the second pattern area are both hollow patterns so that the corresponding area is an exposure area, or the first pattern area and the second pattern area are both shielding patterns so that the corresponding area is a non-exposure area; here, whether the first pattern region and the second pattern region are hollow patterns or shielding patterns depends on whether the photoresist covering the corresponding region is a positive photoresist or a negative photoresist.
In one embodiment, the second pattern region has the same shape as the first pattern region.
In one embodiment, the minimum feature size of the second pattern region is equal to or greater than the minimum feature size of the first pattern region.
In one embodiment, the predetermined distance is in a range of 5-20 μm.
It should be noted that the embodiment of the three-dimensional memory provided by the invention, the embodiment of the preparation method of the three-dimensional memory and the embodiment of the photoetching mask belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict. It should be further noted that, in the three-dimensional memory provided by the embodiment of the present invention, the technical feature combinations thereof can already solve the technical problems to be solved by the present invention; therefore, the three-dimensional memory provided by the embodiment of the present invention is not limited by the method for manufacturing the three-dimensional memory provided by the embodiment of the present invention, and any three-dimensional memory manufactured by the method for manufacturing the three-dimensional memory structure provided by the embodiment of the present invention is within the protection scope of the present invention.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (11)
1. A three-dimensional memory, comprising:
a plurality of memory cell regions arranged at intervals;
a filling material layer filled between the memory cell regions for electrically isolating the memory cell regions;
a conductive plug penetrating the filling material layer and electrically connected with the gate layer in the memory unit region; and the number of the first and second groups,
a stress buffer structure formed in the step of forming the conductive plug, the stress buffer structure being located in the filling material layer and including a portion spaced apart from a sidewall of at least one memory cell region by a predetermined distance to buffer a stress influence of the filling material layer on the sidewall of the memory cell region; the minimum structure size of the stress buffering structure is equal to the minimum structure size of the conductive plug; the stress buffer structures are distributed between at least two adjacent storage unit areas in a matrix mode, and the distance between the two adjacent stress buffer structures is equal to the structural size of the stress buffer structures.
2. The three-dimensional memory according to claim 1, wherein the stress buffering structure has a shape identical to a shape of the conductive plug.
3. The three-dimensional memory according to claim 1, wherein the preset distance is in a range of 5-20 μm.
4. The three-dimensional memory according to claim 1, wherein the filler material layer comprises a Tetraethylorthosilicate (TEOS) layer.
5. A method of fabricating a three-dimensional memory, the method comprising:
forming a plurality of storage unit areas which are arranged at intervals;
filling and forming a filling material layer between the memory cell regions;
etching the filling material layer to form a stress buffer structure hole; the stress buffer structure hole comprises a part which is arranged at a preset distance from the side wall of at least one memory cell area;
filling the stress buffer structure holes to form a stress buffer structure; the stress buffer structure is used for buffering the stress influence of the filling material layer on the side wall of the memory unit area;
the method further includes forming a conductive plug conductively connected with a gate layer of the three-dimensional memory; the minimum structure size of the stress buffering structure is equal to the minimum structure size of the conductive plug; the stress buffer structures are distributed between at least two adjacent storage unit areas in a matrix form, and the distance between the two adjacent stress buffer structures is equal to the structural size of the stress buffer structures;
etching the filling material layer, and forming a conductive plug hole which penetrates through the filling material layer and exposes the gate layer in the memory unit area; and/or the filling the stress buffering structure hole is performed in the same process as the filling of the conductive plug hole of the three-dimensional memory to form a conductive plug.
6. The method of claim 5, wherein the stress buffering structure hole has a shape that is the same as a shape of the electrically conductive plug hole.
7. The method of claim 5, wherein the predetermined distance is in the range of 5-20 μm.
8. The method of claim 5, wherein the filler material layer comprises a TEOS (tetraethylorthosilicate) layer.
9. A photoetching mask plate is applied to an etching process of a three-dimensional memory conductive plug hole, and is characterized by comprising the following steps:
the first pattern area corresponds to a preset forming position of a conductive plug of the three-dimensional memory;
a second pattern region corresponding to a preset forming position of a stress buffer structure of the three-dimensional memory; the minimum feature size of the second pattern area is equal to the minimum feature size of the first pattern area; the space between two adjacent second pattern areas is equal to the structure size of the second pattern areas; the stress buffer structure is positioned in a filling material layer filled between the memory cell areas of the three-dimensional memory and comprises a part which is arranged at a preset distance from the side wall of at least one memory cell area; the stress buffer structures are distributed between at least two adjacent storage unit areas in a matrix form; the stress buffer structure is used for buffering the stress influence of the filling material layer on the side wall of the storage unit area;
the exposure setting in the first pattern area is the same as the exposure setting in the second pattern area.
10. The lithographic reticle of claim 9, wherein the second pattern region has a shape that is the same as a shape of the first pattern region.
11. The reticle of claim 9, wherein the predetermined distance is in a range of 5-20 μ ι η.
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| CN111403389B (en) * | 2020-03-18 | 2023-05-12 | 长江存储科技有限责任公司 | Three-dimensional memory device structure and forming method |
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| US9793139B2 (en) * | 2015-10-29 | 2017-10-17 | Sandisk Technologies Llc | Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines |
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