CN110648978A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN110648978A
CN110648978A CN201910547770.0A CN201910547770A CN110648978A CN 110648978 A CN110648978 A CN 110648978A CN 201910547770 A CN201910547770 A CN 201910547770A CN 110648978 A CN110648978 A CN 110648978A
Authority
CN
China
Prior art keywords
metal layer
semiconductor chip
rear surface
solder
mounting substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910547770.0A
Other languages
English (en)
Inventor
山田文生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Device Innovations Inc
Original Assignee
Sumitomo Electric Device Innovations Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Device Innovations Inc filed Critical Sumitomo Electric Device Innovations Inc
Publication of CN110648978A publication Critical patent/CN110648978A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60015—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using plate connectors, e.g. layer, film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)

Abstract

本发明涉及半导体器件及其制造方法。公开了一种半导体器件，其包括安装基板、半导体芯片、后表面金属层、AuSn焊料层和焊料阻挡金属层。半导体芯片被安装在安装基板上，并且包括前表面和后表面，以及发热元件。后表面金属层包含金(Au)。AuSn焊料层位于安装基板和后表面之间，以将半导体芯片固定到安装基板。焊料阻挡金属层位于后表面和安装基板之间，并且位于除了其中形成发热元件的加热区域之外的非加热区域中。焊料阻挡金属层包括NiCr、Ni和Ti中的至少一种，并且延伸到半导体芯片的边缘。空隙被设置在焊料阻挡金属层和AuSn焊料层之间。

Description

半导体器件及其制造方法
本申请基于并要求于2018年6月26日提交的日本专利申请No.2018-121381的优先权的权益，该申请通过引用的方式整体并入在本文中。
技术领域
本公开涉及一种半导体器件和制造半导体器件的方法。
背景技术
通常，利用银(Ag)印膏或金-锡(AuSn)将以面朝上的方式安装的单片微波集成电路(MMIC)焊料固定到封装件。当使用AuSn焊料时，在半导体芯片和封装件之间的AuSn焊料被熔化，并且在半导体芯片的后表面上形成的金(Au)和在封装件的前表面上形成的Au被固定。AuSn焊料具有较弱的热导率，并且因此优选的AuSn焊料是薄的。另外，当气泡(空隙)进入AuSn焊料的内部时，显著增加从半导体芯片到封装件的热阻。因此，通过清洗半导体芯片而以小厚度形成AuSn焊料，并且在使用AuSn焊料进行安装中以这样的方式来执行安装使得气泡不进入AuSn焊料。
然而，即使执行了清洗，但由于制造中的变化也难以完全去除气泡。当在半导体芯片中形成的场效应晶体管(FET)的一部分下方存在气泡时，由于FET的热量生成而引起的温度上升变得大于假设，并且可能恶化器件的操作寿命。
JP2015-070052A公开了一种在安装半导体芯片时通过使用减压炉去除熔融焊料中的气泡以防止由于气泡而引起的不利影响的方法。JP-H10-223808A公开了一种方法，其中在不重叠半导体芯片的后表面上的FET的有源区的位点处形成凹槽，并且AuSn焊料内部的气泡在管芯键合期间通过清洗被捕获在该凹槽中。
发明内容
本公开提供了一种半导体器件。该半导体器件包括安装基板、半导体芯片、后表面金属层、AuSn焊料层、和焊料阻挡金属层。半导体芯片被安装在安装基板上。半导体芯片包括面向安装基板的后表面、与后表面相反的前表面、以及在前表面上形成的至少一个发热元件。后表面金属层被形成在半导体芯片的后表面上。后表面金属层包含金(Au)。AuSn焊料层位于安装基板和半导体芯片的后表面之间，以通过后表面金属层将半导体芯片固定到安装基板。焊料阻挡金属层位于半导体芯片的后表面和安装基板之间，并且焊料阻挡金属层位于除了其中形成发热元件的加热区域之外的非加热区域中。焊料阻挡金属层包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种，并且延伸到半导体芯片的第一边缘。空隙被设置在焊料阻挡金属层和AuSn焊料层之间。
本公开提供了一种制造半导体器件的方法。该方法包括：在半导体芯片的后表面上形成种子金属层，半导体芯片包括第一区域和第二区域，第一区域包括半导体发热元件，第二区域不包括半导体发热元件；在种子金属层上形成包含金(Au)的后表面金属层；在所述第二区域内，在后表面金属层上形成包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种的焊料阻挡金属层，以延伸到半导体芯片的边缘；以及在使后表面金属层与AuSn焊料层接触的情况下，来清洗安装基板上的半导体芯片。
本公开还提供了另一种制造半导体器件的方法。该方法包括：在半导体芯片的后表面上形成包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种的焊料阻挡金属层，该半导体芯片第一区域和第二区域，第一区域包括半导体发热元件，第二区域不包括半导体发热元件；在焊料阻挡金属层上形成包含金(Au)的后表面金属层；在所述第二区域内，在延伸到所述半导体芯片的边缘的区域中从后表面金属层暴露焊料阻挡金属层；在使后表面金属层与AuSn焊料层接触的情况下，来清洗安装基板上的半导体芯片。
附图说明
从以下参考附图对本公开的实施例的详细说明，将更好地理解上述和其他目的、方面和优点，在附图中：
图1A是示意性地图示根据第一实施例的半导体器件的半导体芯片的正面的视图；
图1B是图示图1A中图示的半导体芯片的后表面的视图；
图1C是图示根据第一实施例的半导体器件的横截面的视图；
图2A至图2J是用于描述根据第一实施例的半导体芯片安装方法中的相应的工艺的视图；
图3A是示意地图示根据第二实施例的半导体器件的半导体芯片的正面的视图；
图3B是图示图3A中图示的半导体芯片的后表面的视图；
图3C是图示根据第二实施例的半导体器件的横截面的视图。
具体实施方式
[要由本公开解决的问题]
JP2015-070052A中公开的方法需要抽空设备以通过真空过程去除气泡。如果AuSn焊料在清洗期间进入凹槽，则JP-H10-223808A中公开的方法可能无法捕获气泡。
[本公开的效果]
根据本公开，能够减少在半导体芯片中形成的发热元件的区域的后表面上的焊料内部的气泡的发生。
[本公开的实施例的描述]
将描述本公开的实施例。根据本公开的一个实施例的半导体器件包括安装基板、半导体芯片、后表面金属层、AuSn焊料层、和焊料阻挡金属层。半导体芯片被安装在安装基板上。半导体芯片包括面向安装基板的后表面、与该后表面相反的前表面、以及在前表面上形成的至少一个发热元件。后表面金属层被形成在半导体芯片的后表面上。后表面金属层包含金(Au)。AuSn焊料层位于安装基板和半导体芯片的后表面之间，以通过后表面金属层将半导体芯片固定到安装基板。焊料阻挡金属层位于半导体芯片的后表面和安装基板之间，且位于除了其中形成发热元件的加热区域之外的非加热区域中。焊料阻挡金属层包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种，并且延伸到半导体芯片的第一边缘。在焊料阻挡金属层和AuSn焊料层之间提供有空隙。
根据该实施例，AuSn焊料层中出现的空隙能够被收集到与AuSn焊料具有不良润湿性的焊料阻挡金属层的周边，并且这些空隙能够被排出到外部。因此，能够减少在半导体芯片中形成的热量生成元件的区域的后表面上的AuSn焊料层中出现的气泡的发生。因此，该实施例能够有效地散发从半导体芯片传递的热量。
作为一个实施例，焊料阻挡金属层可以被形成在后表面金属层上并被形成在安装基板和后表面金属层之间。根据该实施例，焊料阻挡金属层以突出的形状被形成在后表面电极层上，并且因此能够提高焊料中出现的气泡的收集效率。
作为一个实施例，后表面金属层可以被形成在种子金属层上，该种子金属层被形成在半导体芯片的后表面上。根据该实施例，能够通过选择性电解电镀形成后表面金属层，并且其易于调节后表面电极的厚度。在该实施例中，种子金属层可以被形成为焊料阻挡金属层，种子金属层可以包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种，以及焊料阻挡金属层可以在其中后表面金属层被去除的部分处被暴露。根据该配置，种子金属层能够用作焊料阻挡金属层，并且因此其能够减少在半导体芯片的后表面上形成的金属层的总的数目。
作为一个实施例，焊料阻挡金属层可以从半导体芯片的与第一边缘相对的第二边缘线性地延伸到第一边缘。根据该实施例，易于将在焊料阻挡金属层的周边处收集的气泡排出到半导体芯片的外部。
作为一个实施例，安装基板可以是容纳半导体芯片的封装件的底部材料。根据该实施例，当将半导体芯片安装在封装件的底部材料上时，从半导体芯片传递的热量能够通过封装件的底部材料有效地散发。
根据本公开的一个实施例的制造半导体器件的方法包括：在半导体芯片的后表面上形成种子金属层，该半导体芯片包括第一区域和第二区域，该第一区域包括半导体发热元件，并且该第二区域不包括半导体发热元件；在种子金属层上形成包含金(Au)的后表面金属层；在所述第二区域内，在后表面金属层上形成包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种的焊料阻挡金属层，以延伸到半导体芯片的边缘；在使后表面金属层与AuSn焊料层接触的情况下，清洗安装基板上的半导体芯片。
根据该实施例，AuSn焊料层中出现的空隙能够被收集到与AuSn焊料具有不良润湿性的焊料阻挡金属层的周边，并且空隙能够被排出到外部。因此，能够减少在半导体芯片中形成的发热元件的区域的后表面上的焊料中出现的气泡的发生。因此，该实施例能够有效地散发从半导体芯片传递的热量。另外，焊料阻挡金属层以突出的形状被形成在后表面电极层上，因此能够提高焊料中出现的气泡的收集效率。
根据本公开的另一实施例的制造半导体器件的方法包括：在半导体芯片的后表面上形成包含镍-铬(NiCr)、镍(Ni)、和钛(Ti)中的至少一种的焊料阻挡金属层，半导体芯片包括第一区域和第二区域，该第一区域包括半导体发热元件，并且该第二区域不包括半导体发热元件；在焊料阻挡金属层上形成包含金(Au)的后表面金属层；在所述第二区域内，在延伸到半导体芯片的边缘的区域中从后表面金属层暴露焊料阻挡金属层；在使后表面金属层与AuSn焊料层接触的情况下，来清洗安装基板上的半导体芯片。
根据该实施例，AuSn焊料层中出现的空隙能够被收集到与AuSn焊料具有不良的润湿性的焊料阻挡金属层的周边，并且空隙能够被排出到外部。因此，能够减少在半导体芯片中形成的发热元件的区域的后表面上的焊料中出现的气泡的发生。因此，该实施例能够有效地散发从半导体芯片传递的热量。
[本公开的实施例的细节]
在下文中，将参考附图描述本公开的半导体器件的实施例和制造半导体器件的方法。在以下描述中，向其给出相同附图标记的配置即使在其他附图中也被视为相同的配置，并且可以省略其描述。注意的是，本发明不限于这些实施例，并且包括了在所附权利要求中，以及在其等同范围内中描述的一系列配置中的所有修改。另外，本发明包括任意实施例的组合，只要组合相对于多个实施例是可能的即可。
[第一实施例]
图1A是示意性地图示根据第一实施例的半导体器件2的半导体芯片1的前表面的视图，并且图1B是示出图1A中图示的半导体芯片1的后表面的视图。图1C是图示根据第一实施例的半导体器件2的横截面的视图，并且图示了当在安装基板100上安装图1A和图1B中图示的半导体芯片2时的横截面。如图1A至图1C所示，半导体器件2包括半导体芯片1、种子金属层50、后表面金属层60、金属层70、AuSn焊料层90、和安装基板100。半导体芯片1具有碳化硅(SiC)基板10和砷化镓外延层20。在下面的描述中，MMIC被举例说明为半导体芯片1，但是半导体芯片1不限于此。
MMIC是集成电路，其中在半导体基板上设置一个或多个射频电路块，并且通过半导体制造过程整体上形成有源元件和无源元件。在图1A中图示的半导体芯片1的示例中，其图示了其中在约1mm×约3mm的碳化硅(SiC)基板10上形成的砷化镓外延层20中形成包括初级放大器21、中间级放大器22、和远端级放大器23的多级放大器的示例。放大器21至23中的每一个由作为有源元件的FET 24和无源元件构成，并且放大器21至23中的每一个通过传输线25连接。
在半导体芯片1中，FET 24在操作期间变为发热元件，并因此在设置有FET 24的放大器21至23的位点中的发热的量是最大的，并且发热量在仅提供传输线25的位置处小。在图1A中，包括发热元件的区域被图示在A中，并且不包括发热元件的区域被图示在B中。不包括发热元件的区域B包括半导体芯片的***部分，以及多级放大器21至23之间的区域。如果当通过使用AuSn焊料层90将半导体芯片1的后表面安装在安装基板100上时气泡出现在区域A中，则不能有效地散发从作为发热元件的FET 24传递的热量，因此区域A的温度变高，电路特征恶化，以及可能缩短半导体器件的操作寿命
然而，在该实施例中，半导体芯片1的后表面被镀有种子金属层50和后表面金属层60，该后表面金属层60被形成在种子金属层50上并且由金(Au)形成。另外，在该实施例中，在后表面金属层60上设置有由其与AuSn焊料层90的有较弱润湿性的镍-铬(NiCr)、镍(Ni)、和钛(Ti)中的任何一种形成的金属层70。如图1B所图示的，金属层70的一对条部70a从半导体芯片1的一个边缘1a通过半导体芯片1的后表面上的级间区域(区域B)延伸到与一个边缘1a相对的另一个边缘1b。如上所述，当从半导体芯片1的后表面观察时，金属层70被暴露在后表面金属层60上。
通过使用AuSn焊料层90将半导体芯片1安装在安装基板100上。安装基板100是容纳半导体芯片1的封装件的底部材料，并且是由例如铜(Cu)形成的，但可以是由其他材料形成。由于NiCr、Ni、和Ti与AuSn焊料层90具有较弱润湿性，因此当将半导体芯片1安装在安装基板100上时，AuSn焊料层90的AuSn焊料被翻转。因此，如图1C中图示的，在金属层70的条部70a的周边处出现空隙C。另外，在安装半导体芯片1时在安装基板100上执行清洗，并且因此在AuSn焊料层90中出现的气泡被收集到空隙C中并且沿着朝向半导体芯片1的边缘1a、1b形成的空隙C排出到外部。
根据上述配置，能够减少在与区域A相对应的后表面金属层60上出现的气泡。此外，空隙C出现在区域B中，并且因此从后表面金属层60到安装基板100的热量传递恶化，并且区域B的温度上升。然而，诸如FET的发热元件没有被设置在区域B中，并且因此不会缩短半导体芯片1的操作寿命。
[半导体芯片安装方法]
接下来，将描述作为制造半导体器件2的方法的半导体芯片安装方法。图2A至图2J是描述根据第一实施例的半导体芯片安装方法中的相应的工艺的视图。图2A图示了前表面处理工艺，图2B图示了光致抗蚀剂涂敷工艺，图2C图示了支撑基板附接工艺，图2D图示了后表面抛光工艺，图2E图示了种子金属层形成工艺，图2F图示了后表面金属层电镀工艺，图2G图示了焊料阻挡金属层形成工艺，图2H图示了焊料阻挡金属层图案化工艺，图2I图示了扩展胶带附着工艺，以及图2J图示了切割工艺，并且相应的工艺被顺序地执行。注意的是，在图2A至图2J中，为了便于观察，相应的构成构件的厚度关系被设定为与实际厚度关系不同。另外，图1C用于描述管芯键合工艺。
(前表面处理工艺)
在前表面处理工艺中，如图2A中所图示的，在具有厚度约为500μm的半导体基板10的前表面上形成诸如GaAs的外延层20，在外延层20中形成有源元件，以及通过绝缘层在外延层20上形成无源元件、传输线等，从而形成构成MMIC的多个半导体芯片1。通过使用现有的半导体制造技术来制备这些元件。例如，如图1A中所图示的，形成了多级放大器21至23，以及连接这些放大器21至23的传输线25。
(光致抗蚀剂涂敷工艺)
接下来，如图2B所图示的，为了保护在基板10的前表面上形成的各个元件，将光致抗蚀剂30涂覆到基板的前表面(在外延层20上)，并且将蜡(未图示)涂覆到光致抗蚀剂30上。
(支撑基板附接工艺)
接下来，如图2C所说明的，为了处理基板10的(与外延层20相对的)后表面，使前表面(外延层20)面对由玻璃形成的支撑基板40并附接到其上。
(后表面抛光工艺)
接下来，如图2D所图示的，利用研磨机来抛光基板10的后表面，使得基板10具有预定的厚度。当用于前表面和后表面金属层60上形成的信号线的金属图案形成了穿过基板10的微带线时，调节基板10的厚度以将线的特征阻抗设定为期望值。注意的是，前表面和后表面金属层60上的地电位的金属图案经由通孔(未被图示)而彼此电连接。在该工艺中，例如，将基板10抛光至约100μm的厚度。
(种子金属层形成工艺)
接下来，如图2E所图示的，作为种子金属层50，由NiCr和Au的两层构成的种子金属层50通过整个表面溅射被形成在SiC基板10的后表面上。种子金属层50被用于在后续工艺中通过可选的电解电镀形成后表面金属层60。例如，以200nm的厚度和2000nm的厚度分别形成种子金属层50的NiCr和Au。
(后表面金属层电镀工艺)
如图2F所图示的，在基板10中，以正由各自具有预定的宽度D1的划线进行分区的状态来形成多个半导体芯片。在形成种子金属层50之后，在种子金属层50的整个表面上提供光致抗蚀剂，并且根据覆盖划线之间的宽度D1同时留下半导体芯片区域的光致抗蚀剂61对光致抗蚀剂进行图案化。由Au形成的后表面金属层60通过可选的电解电镀形成在暴露于例如厚度为10μm的半导体芯片的后表面的种子金属层50上。在形成后表面金属层60之后去除光致抗蚀剂61。
(焊料阻挡金属层形成过程)
接下来，如图2G所图示的，在去除光致抗蚀剂61之后，例如，通过溅射在后表面金属层60的整个表面上形成与AuSn焊料具有较弱润湿性的NiCr，以提供厚度约为50nm的金属层70。然后，在金属层70上图案化光致抗蚀剂71。
(焊料阻挡金属层图案化工艺)
接下来，通过使用光致抗蚀剂71作为掩模来蚀刻金属层70，并且如图2H所图示的，金属层70的各自具有大约100μm的宽度的线状条部70a被留在后表面金属层60上。如图1B所说明的，金属层70的条部70a在半导体芯片1的区域B中从半导体芯片1的一个边缘1a延伸到另一个边缘1b。该工艺如下执行。也就是说，如图2G所图示的，利用光致抗蚀剂71掩蔽其中要被留下由NiCr形成的金属层70的区域，对金属层70进行湿法蚀刻，并且然后去除光致抗蚀剂71。
(扩展带接合工艺)
接下来，如图2I所图示的，将基板10的后表面附接到扩展带80，去除前表面上的蜡(未图示)和光致抗蚀剂30，并且从支撑基板40上剥离掉基板。注意的是，在去除前表面上的蜡(未图示)和光致抗蚀剂30并且从支撑基板40上剥离掉基板10之后，基板10的后表面可以附接到扩展带80。在该工艺中，基板10没有被切割，因此相应的半导体芯片1被不分离。
(切割工艺)
接下来，如图2J所图示的，半导体芯片1通过在基板10的前表面上的切割而被分离。通过使用具有比划线宽度D1更窄的宽度D2的切割刀片沿着划线(例如在划线宽度D1内)来形成切割。另外，从扩展带80剥离掉半导体芯片1，从而获得单独的半导体芯片1。
(管芯键合工艺)
接下来，如图1C所图示的，半导体芯片1中的每个被管芯键合到例如布线基板或由封装件的底部材料(金属材料)形成的安装基板100上。管芯键合如下被执行。即，AuSn焊料层90预先以球形或片状(薄膜形状)被设置在安装基板100上，例如在设定为320℃的氮气(N2)环境中，AuSn焊料层90被熔化在安装基板100上，以及半导体芯片1在安装基板100上被清洗(摩擦)(在彼此上被摩擦)。
此时，如上所述，由NiCr形成的金属层70与AuSn焊料层90具有不良的润湿性，并且在安装期间空隙C可以被形成在金属层70的部分中。当由于清洗而引起的在AuSn焊料中出现的气泡到达金属层70时，气泡沿着线状金属层70被排出到芯片的外部。此外，熔化的AuSn焊料层90与Au具有良好的润湿性，并且在半导体芯片1的后表面金属层60的Au与安装基板100上的Au之间的均匀的厚度中扩散。此时，AuSn焊料的厚度变为约10μm。据此，由于气泡消失在半导体芯片1的区域A的后表面上，所以提高了散热效率，抑制了电路特征的恶化，以及能够实现半导体器件的长操作寿命。
[第二实施例]
在本公开中，当通过使用AuSn焊料层90将后表面金属层60固定到安装基板100时，通过与AuSn焊料层90的润湿性差的金属层70的图案收集在AuSn焊料层90中出现的气泡，并且该气泡被排出到半导体芯片1的外部。据此，当从半导体芯片1的后表面观察时，金属层70的图案可以从后表面金属层60暴露。在第一实施例中，种子金属层50和后表面金属层60依次被形成在基板10的后表面上，并且金属层70在后表面金属层60上被图案化，从而暴露金属层70。
在第二实施例中，半导体器件2a的种子金属层50的材料被设定为由与AuSn焊料层90具有不良的润湿性的NiCr、Ni和Ti中的任何一种构成的材料，并且种子金属层50被设置有焊料阻挡金属层的功能，如图3A至3C所示。据此，在第二实施例中，种子金属层50用作第一实施例的金属层70，并且半导体器件2a不包括金属层70。此外，在种子金属层50上形成的后表层金属层60被部分地去除以暴露种子金属层50的一对条部50a。其中种子金属层50被暴露的区域的条部50a在半导体芯片1的区域B内在半导体芯片1的边缘1a、1b之间延伸。与金属层70的功能相对应的、从后表面金属层60暴露的种子金属层50的条部50a的功能与第一实施例中的功能相同，因此将省略其描述。
在上文中，已经描述了根据本公开的实施例的半导体器件和半导体芯片安装方法，但是各自与AuSn焊料层90具有不良润湿性的金属层70的条部70a和种子金属层50的条部50a的图案不限于线形，并且可以是格子形状或其他形状。

Claims (8)

1.一种半导体器件，所述半导体器件包括：
安装基板；
半导体芯片，所述半导体芯片被安装在所述安装基板上，所述半导体芯片包括面向所述安装基板的后表面、与所述后表面相反的前表面、以及在所述前表面上形成的至少一个发热元件；
后表面金属层，所述后表面金属层被形成在所述半导体芯片的所述后表面上，所述后表面金属层包含金(Au)；
AuSn焊料层，所述AuSn焊料层位于所述安装基板和所述半导体芯片的所述后表面之间，以通过所述后表面金属层将所述半导体芯片固定到所述安装基板；以及
焊料阻挡金属层，所述焊料阻挡金属层位于所述半导体芯片的所述后表面和所述安装基板之间，并且所述焊料阻挡金属层位于除了形成所述发热元件的加热区域之外的非加热区域中，所述焊料阻挡金属层包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种并且延伸到所述半导体芯片的第一边缘，
其中，在所述焊料阻挡金属层和所述AuSn焊料层之间提供有空隙。
2.根据权利要求1所述的半导体器件，其中，
所述焊料阻挡金属层被形成在所述后表面金属层上以及被形成在所述安装基板和所述后表面金属层之间。
3.根据权利要求1或权利要求2所述的半导体器件，其中，
所述后表面金属层被形成在种子金属层上，所述种子金属层被形成在所述半导体芯片的所述后表面上。
4.根据权利要求3所述的半导体器件，其中，
所述种子金属层被形成为所述焊料阻挡金属层，所述种子金属层包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种，并且
在去除了所述后表面金属层的部分处暴露所述焊料阻挡金属层。
5.根据权利要求1至4中任一项所述的半导体器件，其中，
所述焊料阻挡金属层从所述半导体芯片的与所述第一边缘相对的第二边缘线性地延伸到所述第一边缘。
6.根据权利要求1至5中任一项所述的半导体器件，其中，
所述安装基板是容纳所述半导体芯片的封装件的底部材料。
7.一种半导体器件的制造方法，包括：
在半导体芯片的后表面上形成种子金属层，所述半导体芯片包括第一区域和第二区域，所述第一区域包括半导体发热元件，所述第二区域不包括所述半导体发热元件；
在所述种子金属层上形成包含金(Au)的后表面金属层；
在所述第二区域内，在所述后表面金属层上形成包含镍-铬(NiCr)、镍(Ni)、和钛(Ti)中的至少一种的焊料阻挡金属层以延伸到所述半导体芯片的边缘；以及
在使所述后表面金属层与AuSn焊料层接触的情况下，清洗在安装基板上的所述半导体芯片。
8.一种半导体器件的制造方法，包括：
在半导体芯片的后表面上形成包含镍-铬(NiCr)、镍(Ni)和钛(Ti)中的至少一种的焊料阻挡金属层，所述半导体芯片包括第一区域和第二区域，所述第一区域包括半导体发热元件，所述第二区域不包括所述半导体发热元件；
在所述焊料阻挡金属层上形成包含金(Au)的后表面金属层；
在所述第二区域内，在延伸到所述半导体芯片的边缘的区域中从所述后表面金属层暴露所述焊料阻挡金属层；以及
在使所述后表面金属层与AuSn焊料层接触的情况下，清洗在安装基板上的所述半导体芯片。
CN201910547770.0A 2018-06-26 2019-06-24 半导体器件及其制造方法 Pending CN110648978A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-121381 2018-06-26
JP2018121381A JP7168280B2 (ja) 2018-06-26 2018-06-26 半導体装置、および、半導体チップの搭載方法

Publications (1)

Publication Number Publication Date
CN110648978A true CN110648978A (zh) 2020-01-03

Family

ID=68980936

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910547770.0A Pending CN110648978A (zh) 2018-06-26 2019-06-24 半导体器件及其制造方法

Country Status (3)

Country Link
US (2) US11031365B2 (zh)
JP (1) JP7168280B2 (zh)
CN (1) CN110648978A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114446911A (zh) * 2020-11-06 2022-05-06 三菱电机株式会社 半导体装置、芯片焊盘及半导体装置的制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0793269A1 (fr) * 1996-02-28 1997-09-03 Koninklijke Philips Electronics N.V. Dispositif semiconducteur incluant une puce munie d'une ouverture de via et soudée sur un support, et procédé de réalisation de ce dispositif
CN1190798A (zh) * 1997-02-07 1998-08-19 日本电气株式会社 半导体器件及其制造方法
CN101185153A (zh) * 2005-05-26 2008-05-21 飞思卡尔半导体公司 半导体封装及其形成方法
CN106463426A (zh) * 2014-06-27 2017-02-22 索尼公司 半导体器件及其制造方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5034170A (zh) * 1973-07-27 1975-04-02
JPS63312613A (ja) * 1987-06-15 1988-12-21 Nec Corp 単板コンデンサ−
DE69426090T2 (de) * 1993-04-27 2001-03-01 Nec Corp., Tokio/Tokyo Verfahren zur Herstellung einer optische Halbleitervorrichtung
JP3461632B2 (ja) * 1995-08-28 2003-10-27 三菱電機株式会社 半導体レーザ装置
DE19536463C2 (de) * 1995-09-29 2002-02-07 Infineon Technologies Ag Verfahren zum Herstellen einer Mehrzahl von Laserdiodenbauelementen
US6342442B1 (en) * 1998-11-20 2002-01-29 Agere Systems Guardian Corp. Kinetically controlled solder bonding
JP3689637B2 (ja) * 2000-12-25 2005-08-31 シャープ株式会社 半導体装置およびその製造方法
JP3882712B2 (ja) * 2002-08-09 2007-02-21 住友電気工業株式会社 サブマウントおよび半導体装置
US7247514B2 (en) * 2003-04-11 2007-07-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for producing the same
KR100975521B1 (ko) * 2003-10-04 2010-08-12 삼성전자주식회사 발광 소자 조립체
JP3994980B2 (ja) * 2004-03-29 2007-10-24 株式会社日立製作所 素子搭載用基板及びその製造方法並びに半導体素子実装方法
US7462861B2 (en) * 2004-04-28 2008-12-09 Cree, Inc. LED bonding structures and methods of fabricating LED bonding structures
US7864398B2 (en) * 2004-06-08 2011-01-04 Gentex Corporation Electro-optical element including metallic films and methods for applying the same
TWI514522B (zh) * 2005-03-18 2015-12-21 Dowa Electronics Materials Co 副載置片及其製造方法
JP2006261551A (ja) * 2005-03-18 2006-09-28 Toyota Motor Corp 半導体モジュール及びその製造方法
JP5214844B2 (ja) * 2005-03-29 2013-06-19 日本オクラロ株式会社 光半導体装置
US7348212B2 (en) * 2005-09-13 2008-03-25 Philips Lumileds Lighting Company Llc Interconnects for semiconductor light emitting devices
JP4634230B2 (ja) * 2005-06-17 2011-02-16 株式会社オートネットワーク技術研究所 回路基板、電子部品及び電気接続箱
US7626275B2 (en) * 2005-12-16 2009-12-01 Mitsubishi Electric Corporation Semiconductor device
JP2007227464A (ja) * 2006-02-21 2007-09-06 Sanyo Electric Co Ltd 半導体装置及び半導体装置の製造方法
JP2007294899A (ja) * 2006-03-31 2007-11-08 Dowa Electronics Materials Co Ltd 半田層及びそれを用いた電子デバイス接合用基板並びに電子デバイス接合用サブマウント
JP2008091768A (ja) * 2006-10-04 2008-04-17 Sharp Corp 半導体レーザ装置および電子機器
JP2013125768A (ja) * 2011-12-13 2013-06-24 Japan Oclaro Inc はんだ接合デバイス及び受信モジュール
US8970010B2 (en) * 2013-03-15 2015-03-03 Cree, Inc. Wafer-level die attach metallization
SG11201601300TA (en) * 2013-08-29 2016-03-30 Mitsui Chemicals Tohcello Inc Adhesive film and method for manufacturing semiconductor device
JP6365919B2 (ja) 2013-09-27 2018-08-01 富士電機株式会社 半導体装置の製造方法
JP6305127B2 (ja) * 2014-03-12 2018-04-04 三菱電機株式会社 半導体レーザ光源
DE102016117826B4 (de) * 2016-09-21 2023-10-19 Infineon Technologies Ag Elektronikmodul und herstellungsverfahren dafür
JP6512231B2 (ja) * 2017-01-27 2019-05-15 トヨタ自動車株式会社 半導体装置
JP6901196B2 (ja) * 2017-05-09 2021-07-14 住友電工デバイス・イノベーション株式会社 半導体モジュール、及び半導体モジュールの製造方法
JP6355092B1 (ja) * 2017-05-11 2018-07-11 パナソニックＩｐマネジメント株式会社 はんだ合金およびそれを用いた接合構造体

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0793269A1 (fr) * 1996-02-28 1997-09-03 Koninklijke Philips Electronics N.V. Dispositif semiconducteur incluant une puce munie d'une ouverture de via et soudée sur un support, et procédé de réalisation de ce dispositif
US5844321A (en) * 1996-02-28 1998-12-01 U.S. Philips Corporation Semiconductor device comprising a chip which is provided with a via opening and is soldered on a support, and method of realizing this device
CN1190798A (zh) * 1997-02-07 1998-08-19 日本电气株式会社 半导体器件及其制造方法
JPH10223808A (ja) * 1997-02-07 1998-08-21 Nec Corp 半導体装置
CN101185153A (zh) * 2005-05-26 2008-05-21 飞思卡尔半导体公司 半导体封装及其形成方法
CN106463426A (zh) * 2014-06-27 2017-02-22 索尼公司 半导体器件及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114446911A (zh) * 2020-11-06 2022-05-06 三菱电机株式会社 半导体装置、芯片焊盘及半导体装置的制造方法

Also Published As

Publication number Publication date
JP7168280B2 (ja) 2022-11-09
US20190393182A1 (en) 2019-12-26
JP2020004806A (ja) 2020-01-09
US20210242162A1 (en) 2021-08-05
US11031365B2 (en) 2021-06-08

Similar Documents

Publication Publication Date Title
US5770468A (en) Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere
US6759599B2 (en) Circuit board, method for manufacturing same, and high-output module
US6440822B1 (en) Method of manufacturing semiconductor device with sidewall metal layers
CA1201537A (en) Semiconductor structures and manufacturing methods
US20230369272A1 (en) Hybrid device assemblies and method of fabrication
EP1304740A2 (en) Circuit board, method for manufacturing same, and high-output module
KR102653704B1 (ko) 반도체 장비 및 제조방법
US20210242162A1 (en) Method of manufacturing semiconductor device
EP1274125A2 (en) Circuit board, method for manufacturing same, and high-output module
JPS5990946A (ja) 半導体構造及び製造方法
JPH11238870A (ja) 半導体装置とその製造方法
KR20220027191A (ko) 열 유도 휘어짐이 감소된 반도체 구조물
JP2019207984A (ja) 半導体装置およびその製造方法
JP7332130B2 (ja) 半導体デバイスの製造方法、半導体装置の製造方法、半導体デバイス、及び半導体装置
JPH07176760A (ja) Ｐｈｓ構造を有するウエハおよびその製造方法
JP2010186962A (ja) 半導体パッケージおよびその作製方法
JP3463790B2 (ja) 配線基板
JP2697683B2 (ja) 半導体装置及びその製造方法
CN113284866A (zh) 半导体装置及其制造方法
CA1213679A (en) Semiconductor structures and manufacturing methods
JP2001176761A (ja) 薄層基板半導体装置及びその製造方法
JP2006216672A (ja) 半導体装置及び半導体装置の製造方法
JPH0870069A (ja) 半導体装置
KR20180023529A (ko) 반도체 패키지의 제조방법
JPH09260400A (ja) 化合物半導体素子およびその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination