CN110620646B - Synchronous signal recovery method and system for quantum key distribution system - Google Patents
Synchronous signal recovery method and system for quantum key distribution system Download PDFInfo
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- H04B10/70—Photonic quantum communication
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- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
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- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
- H04L9/0819—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s)
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
- H04L9/0852—Quantum cryptography
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Abstract
The invention discloses a method and a system for recovering a synchronous signal for a quantum key distribution system, which relate to the technical field of quantum communication.A terminal device S1 negotiates with a terminal device B through a classical channel, informs the terminal B of a signal parameter to be sent, and starts to send first-stage training data after appointing a delay time; s2, configuring a phase-locked loop at the terminal B to generate a clock with the same frequency as the signal light, waiting for the appointed delay time, then counting the time interval of two adjacent signal lights, and completing the frequency synchronization with the terminal A according to the time interval; and S3, after the B-end equipment completes frequency synchronization, informing the A-end to enter a second synchronization stage, and realizing the frequency and position synchronization of the B-end and A-end synchronization signals. The beneficial effects of the invention are: 1. synchronous light is eliminated, and the design cost is reduced; 2. the quantum key generation rate is improved; 3. the power consumption and wiring difficulty of the equipment are reduced; 4. the reliability of the equipment is improved; 5. the security of key generation is improved.
Description
Technical Field
The invention relates to the technical field of quantum communication, in particular to a synchronous signal recovery method and a synchronous signal recovery system for a quantum key distribution system.
Background
Current Quantum Key Distribution (QKD) systems employ a scheme in which synchronous light and signal light are transmitted in the same optical fiber. Namely, one semiconductor Laser (Syn-Laser) is used for periodically emitting low-frequency synchronous light, and then another or a plurality of semiconductor lasers (Sig-lasers) are used for emitting high-frequency signal light (the frequency of the signal light is integral multiple of the synchronous light) according to the result of quantum state coding of a quantum communication source end. The light intensity of the synchronous light is very strong, and the light intensity of the signal light is single photon level. After optical signals generated by the two light sources are multiplexed by combining optical fibers, the optical signals are transmitted to quantum key generation equipment at the opposite end in the same optical fiber to generate a quantum key. The system structure is shown in figure 1:
fig. 1 is a scheme suitable for general engineering applications. The scheme is mainly realized in the following three ways:
1. the synchronous light and the signal light use different wavelengths respectively, and the synchronous light and the signal light are staggered in time by defining a strict quantum frame format.
2. The synchronous light and the signal light respectively use different wavelengths, the isolation between the two signals is kept by methods such as filtering, and the strict quantum frame format does not need to be defined to ensure that the two signals are staggered in time.
3. The synchronization light and the signal light use the same wavelength, and are temporally shifted by defining a strict quantum frame format.
Taking scheme 1 as an example, a scheme of general engineering application is illustrated: it is assumed that the frequency of the synchronization light emitted from the a-side (transmitting side) in the system is fsyn (corresponding to a period Tsyn). The frequency of the quantum signal light emitted from the a terminal is fsig (the corresponding period is Tsig). The synchronous light and the signal light enter an optical fiber to be transmitted to a B end (receiving end) after being combined by the optical fibers. The relationship between the synchronization light and the signal light is shown in fig. 2, and the time interval between two adjacent synchronization lights is Tsyn. The time interval between two adjacent quantum signal lights is Tsig. The time difference between the synchronization light and the first signal light corresponding to it is also Tsig.
After quantum signal light and synchronous light are transmitted to quantum equipment at the B end through optical fibers, the synchronous light and the signal light are separated. The synchronous light enters a time position conversion chip (TDC) after being subjected to broadening and level conversion by a delay circuit and is used as a beacon (namely a quantum frame synchronous beacon) for quantum signal light position operation. The signal light is in a single-photon level, most signals are lost after being transmitted through the long-distance optical fiber, the lost serial numbers are distributed randomly, the rest signals capable of reaching the B-end equipment enter the single-photon detector and are converted into electric signals, the electric signals are also sent to the TDC chip, the relative position relation between the signals and the synchronous light is calculated, and then the next key generation is carried out. The relationship between the signal light entering the detector at the B-end and the synchronization light is shown in fig. 3.
In fig. 3, due to the loss of a large amount of quantum signal light in the transmission process, signal light at many positions is not received and cannot participate in coding. But the time interval between any signal light and the corresponding sync light must be an integer multiple of Tsig.
Therefore, the main disadvantages of the prior art are:
1. the generation of synchronous light and signal light needs a semiconductor laser respectively, so that the hardware design cost, the equipment power consumption and the equipment complexity are increased, and the equipment reliability is reduced.
2. The light intensity of the synchronous light is very strong, and the signal light at the adjacent position is easily interfered, so that a no light area needs to be arranged to filter the signal light interfered by the synchronous light, and the corresponding cost is to reduce the code rate of the quantum key.
The technical problem to be solved is as follows:
1. after the sync-light laser is removed, the B-side device cannot mark which quantum communication frame the received signal light belongs to (i.e., the sync-light queue and relative position). Without solving this problem, it is difficult to perform universally applicable quantum key generation.
2. The elimination of the synchronous light can improve the difficulty of discovering the quantum communication link through line silent interception, so that the mode system analysis, the subsequent protocol analysis and the quantum attack are performed, and the security of an actual quantum key distribution system is better guaranteed.
Disclosure of Invention
In order to achieve the above object, the present invention provides a method and system for recovering a synchronization signal for a quantum key distribution system, aiming at eliminating the problem of synchronization light in the conventional quantum communication scheme.
The technical scheme is that the synchronous signal recovery method for the quantum key distribution system comprises the following steps,
s1, an A-side device negotiates with a B-side device through a classical channel, informs a B-side of a signal parameter to be sent according to a defined quantum frame format, and starts to send first-stage training data after appointing a delay time; the training data at this stage is signal light of a given frequency;
after receiving the command frame, the B-end equipment sends a response frame and initializes a delay chip; after the A-side equipment receives the response frame, calculating the link communication delay between the A-side equipment and the B-side equipment, and then calculating the optimal signal sending time; the frequency of signal light sent by the A-side equipment in the training stage is fsig;
wherein, calculating the communication time difference between the two ends of the AB by calculating the communication time delay of the link, and then calculating the time difference with the appointed delay time to obtain the optimal signal sending time;
s2, after the terminal B receives the command frame sent by the terminal A and gives a response frame, configuring a phase-locked loop PLL to generate a clock with the same frequency as the signal light, waiting for the delay time appointed in the S1, then counting the number Nsig of the received signal light, and starting to count the time interval of two adjacent signal lights by using a time position conversion chip TDC when receiving the first signal light; the terminal B completes the frequency synchronization with the terminal A according to the time interval;
s3, after the frequency synchronization of the B-end equipment is finished, informing the A-end to enter a second synchronization stage, and then generating a synchronization pulse with the frequency of fsyn to a time position conversion chip TDC by using a clock with the synchronized frequency; after receiving the notification, the end a starts to send signal light at the frequency fsyn; the time interval between the signal light sent by the A end and the synchronous signal inside the signal light is tsyn;
after receiving the signal light pulse, the time position conversion chip TDC at the B end gives a first time difference Tb between a synchronous electric signal generated by the B end and a received signal photoelectric signal, the B end equipment records Tb, continuously counts a second Tb and so on; after Tb statistics is completed, after data quantity which can meet system error requirements of calculation results is calculated, the preferable statistic quantity is at least 1MB data quantity, all the counted Tb is analyzed and compared with tsyn, and then time difference td between a synchronous electric signal generated by the B end and a synchronous signal generated by the A end can be calculated, namely td = Tb-tsyn; and the B end adjusts the delay value of the delay chip, reduces or increases the sending delay of the synchronous signal, and realizes the frequency and position synchronization of the synchronous signal of the B end and the A end, thereby recovering the original synchronous signal to realize the calibration of the quantity subframe.
Preferably, after entering the normal working state, the B-side counts the time interval of two adjacent signal lights again according to the S2, and dynamically synchronizes the frequencies of the B-side and the a-side.
Preferably, said time interval of one unit is at least 2 μ s.
Preferably, the signal parameters in S1 include a synchronization signal frequency fsyn, a signal light frequency fsig, and a time interval tsyn between the signal light and its corresponding synchronization signal.
Preferably, in S2, the time interval between two adjacent signal lights is counted, and the statistical method includes:
the time interval between any two adjacent signal lights is Tn, wherein n is an integer greater than 1, and the average period Tavgn between any two signal lights is obtained according to Tn;
counting the Navg of the Tavgn by the programmable device at the B end, and accumulating the Tavgn to obtain SUMagg = SUM (Tavgn);
after the statistics of Tavgn is completed, tavg = SUMagvg/Navg can be obtained; tavg is the period of the signal light generated by the current A end;
and the programmable device at the B end adjusts the phase of a feedback link of the phase-locked loop PLL through the internal delay phase-locked loop DLL according to the value of Tavg, and then the frequency synchronization with the A end can be completed.
The specific steps may be that, in S201, the time interval between the first signal light and the second signal light is t1, because the time interval between each two adjacent signal lights is an integral multiple of Tsig, tsig is the reciprocal of fsig, and the reciprocal of frequency is the period, the average period Tavg1 between the first signal light and the second signal light can be obtained as t1/n1;
s202, the average period Tavg2 between the second signal light and the third signal light is t2/n2; the average period Tavg3 between the third signal light and the fourth signal light is t3/n3, and so on;
s203, the programmable device at the B terminal accumulates the calculated Tavg1, tavg2, \8230;, tavgn to obtain a SUMavg, and counts the number Navg; after the data quantity which can meet the system error requirement of the calculation result is counted, preferably after the data with the magnitude of at least 1MB is counted, the average value Tavg can be obtained; i.e., tavg = SUMavg/Navg; tavg is the actual period of the signal light emitted by the current A end;
and S204, the programmable device at the B end adjusts the phase of a feedback link of the PLL through an internal DLL according to Tavg, and then the frequency synchronization with the A end can be completed.
The invention also provides a system for realizing the synchronous signal recovery method for the quantum key distribution system, which is characterized by comprising an A end and a B end which are communicated with each other, wherein the A end comprises an A end programmable device and a signal light laser which forms a control loop with the A end programmable device; the B end comprises a B end programmable device, a delay chip, a time position conversion chip TDC and a single photon detector, and the B end programmable device is sequentially connected with the delay chip and the time position conversion chip TDC to form a communication loop;
the A-end programmable device and the B-end programmable device form a communication channel through a classical link, and the signal light laser of the A-end is respectively connected with the time position conversion chip TDC and the B-end programmable device through single photon detectors and sends detector signals to the two.
Preferably, the programmable device at the end B comprises a frequency synchronization logic module, a Delay Locked Loop (DLL), a Phase Locked Loop (PLL) and a synchronous signal logic module, and the frequency synchronization logic module is communicated with the programmable device at the end A through a classical link; the frequency synchronization logic module is connected with a delay phase-locked loop (DLL) and a phase-locked loop (PLL) to form a control path, and a feedback link for mutual communication is arranged between the delay phase-locked loop (DLL) and the PLL;
the phase-locked loop PLL and the synchronous signal logic module form a communication channel; the synchronous signal logic module sends a synchronous signal and a delay chip control signal to the delay chip; the time delay chip transmits the phase-modulated synchronous signal to the time position conversion chip TDC; and the TDC of the time position conversion chip feeds back information to the synchronous signal logic module.
The technical scheme provided by the invention has the beneficial effects that: 1. synchronous light is eliminated, and design cost is reduced; 2. the quantum key generation rate is improved; 3. the power consumption and wiring difficulty of the equipment are reduced; 4. the reliability of the equipment is improved; 5. the security of key generation is improved.
Drawings
Fig. 1 is a structure of a current quantum key distribution system in the background art of the present invention.
Fig. 2 is a schematic diagram illustrating a relationship between an a-side synchronization light and a signal light according to the background art of the present invention.
Fig. 3 is a schematic diagram of the relationship between the B-side synchronization light and the signal light in the background art of the present invention.
Fig. 4 is a synchronization signal recovery subsystem structure according to an embodiment of the present invention.
Fig. 5 is a signal light statistics diagram in the first training phase according to an embodiment of the invention.
Fig. 6 shows a positional relationship between the signal light and the synchronization signal provided by the TDC chip at B-end according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. Of course, the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1
Referring to fig. 1 to 6, the present invention provides a method and a system for recovering a synchronization signal for a quantum key distribution system, where a position relationship between a signal light generated by an a-side device and a quantum frame starting point (i.e., an original synchronization signal position) is an integer multiple of Tsig, and a typical value of a signal light received by a B-side is only one hundredth to one thousandth of magnitude, but a time interval between any two received signal lights is certainly an integer multiple of Tsig. Therefore, after the synchronization light is removed, the start position of each sub-frame (i.e. the original synchronization signal position) can be calculated according to the received signal light. The block diagram of the system is shown in fig. 4.
The specific process of synchronization signal recovery is as follows:
1. the device at the a end negotiates with the device at the B end through a classical channel, and according to a defined quantum frame format, notifies the B end of the frequency fsyn of a synchronization signal to be sent, the frequency fsig of a signal light, and a time interval tsyn between the signal light and the corresponding synchronization signal, and starts to send the training data at the first stage after stipulating 2s (if the link is long, the time can be extended appropriately). And after receiving the command frame, the B-end equipment sends a response frame and initializes the delay chip. After the A-end equipment receives the response frame, the link communication delay between the A-end equipment and the B-end equipment is calculated, and then the optimal signal sending time is calculated. The frequency of the signal light sent by the a-side device in the training phase is fsig.
2. After the terminal B receives the command frame sent by the terminal A and gives a response frame, a phase-locked loop PLL is configured to generate a clock with the same frequency as the signal light, the counting time of 2s is waited, then the number Nsig of the received signal light is counted, and the time interval of two adjacent signal lights is counted by using a TDC chip when the first signal light is received. The statistical process is shown in fig. 5.
In fig. 5, the time interval between the first signal light and the second signal light is t1, and the time interval between each adjacent signal light is an integral multiple of Tsig, so that the average period Tavg1 between the first signal light and the second signal light is t1/3. Similarly, the average period Tavg2 between the second signal light and the third signal light is t2/2. The average period Tavg3 between the third signal light and the fourth signal light is t3/4, and so on. And the FPGA accumulates the calculated Tavg1, tavg2, \8230;, tavgn to obtain a SUMagvg, and counts the Navg. After a sufficient amount of data is counted, the mean value Tavg can be obtained. I.e. Tavg = SUMavg/Navg. Tavg is the actual period of the signal light emitted by the current a terminal. And the FPGA at the B end adjusts the phase of a feedback link of the phase-locked loop PLL according to Tavg through the internal delay phase-locked loop DLL to complete the frequency synchronization with the A end.
3. After the frequency synchronization is completed, the device at the end B informs the end A to enter a second synchronization stage, and then a clock after the frequency synchronization is used for generating a synchronization pulse with the frequency fsyn to the TDC chip. After receiving the notification, the a-side starts to transmit the signal light at the frequency fsyn. The distance between the signal light sent by the a-terminal and the synchronization signal inside the signal light is as reported in step 1 tsyn. After receiving the signal light pulse, the TDC chip at the B-side provides a first time difference Tb (as shown in fig. 6) between the synchronous electrical signal generated at the B-side and the received signal photoelectric signal. And the FPGA at the B end records Tb, continuously counts the second Tb, and so on. After a sufficient amount of Tb is counted, the FPGA analyzes all the counted Tb and compares the Tb with tsyn, so that a time difference td between a synchronous electric signal generated by the B end and a synchronous signal generated by the A end can be calculated, namely td = Tb-tsyn. The B end adjusts the delay value of the delay chip, reduces or increases the sending delay of the synchronous signal, and then the frequency and position synchronization of the synchronous signal of the B end and the A end can be realized, thereby successfully recovering the original synchronous signal to realize the calibration of the quantity subframe.
Furthermore, because the stability of the electronic device is affected by the environment to generate deviation, after the electronic device enters a normal working state, the B end can calculate the frequency deviation of the two ends again according to the step 2 as required, then adjust the phase of the phase-locked loop PLL, and dynamically synchronize the frequencies of the B end and the A end.
Referring to fig. 4, the system comprises an a end and a B end which are communicated with each other, wherein the a end comprises an a end FPGA and a signal light laser which forms a control loop with the a end FPGA; the FPGA at the B end is sequentially connected with the delay chip and the time position conversion chip TDC; the FPGA at the A end and the FPGA at the B end form a communication channel through a classical link, the signal light laser at the A end is connected with a single-photon detector through a communication optical fiber, and the single-photon detector is respectively connected with the TDC of the time position conversion chip and the FPGA at the B end and sends detector signals to the TDC and the FPGA;
the FPGA at the end B comprises a frequency synchronization logic module which is communicated with the FPGA at the end A through a classical link, the frequency synchronization logic module is connected with a delay phase-locked loop (DLL) and a phase-locked loop (PLL) to form a control channel, the delay phase-locked loop (DLL) and the PLL are provided with feedback links which are communicated with each other, and the PLL and the synchronization signal logic module form a communication channel; the synchronous signal logic module sends a synchronous signal and a delay chip control signal to the delay chip; the time delay chip transmits the phase-modulated synchronous signal to the time position conversion chip TDC; and the TDC of the time position conversion chip feeds back information to the synchronous signal logic module.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. A synchronization signal recovery method for a quantum key distribution system includes,
s1, an A-end device negotiates with a B-end device through a classical channel, a signal parameter to be sent is notified to the B-end according to a defined quantum frame format, and a first-stage training data is sent after a delay time is appointed;
after receiving the command frame, the B-end equipment sends a response frame and initializes a delay chip; after the A-end equipment receives the response frame, calculating the link communication delay between the A-end equipment and the B-end equipment, and then calculating the optimal signal sending time; the frequency of signal light sent by the A-end equipment in the training stage is fsig;
s2, after the terminal B receives the command frame sent by the terminal A and gives a response frame, configuring a phase-locked loop PLL to generate a clock with the same frequency as the signal light, waiting for the delay time appointed in the S1, then counting the number Nsig of the received signal lights, and starting to count the time interval of two adjacent signal lights by using a time position conversion chip TDC when the first signal light is received; the terminal B completes the frequency synchronization with the terminal A according to the time interval;
s3, after the frequency synchronization of the B-end equipment is finished, the A-end is informed to enter a second synchronization stage, and then a clock with the synchronized frequency is used for generating a synchronization pulse with the frequency of fsyn to a time position conversion chip TDC; after receiving the notification, the end A starts to send signal light at the frequency fsyn; the time interval between the signal light sent by the A end and the synchronous signal inside the signal light is tsyn;
after receiving the signal light pulse, the time position conversion chip TDC at the B end gives a first time difference Tb between a synchronous electric signal generated by the B end and a received signal photoelectric signal, the B end equipment records Tb, continuously counts a second Tb and so on; analyzing all the counted Tb, comparing with tsyn, and calculating a time difference td between a synchronous electric signal generated by the B end and a synchronous signal generated by the A end, namely td = Tb-tsyn; and the B end adjusts the delay value of the delay chip, reduces or increases the sending delay of the synchronous signal, and realizes the frequency and position synchronization of the synchronous signal of the B end and the A end, thereby recovering the original synchronous signal to realize the calibration of the quantity subframe.
2. The method according to claim 1, wherein after entering a normal operating state, the B-side dynamically synchronizes the frequencies of the B-side and the a-side according to the time interval of the two adjacent signal lights counted by the S2.
3. The synchronization signal recovery method for a quantum key distribution system according to claim 1, wherein the time interval of one unit is at least 2 μ s.
4. The method for recovering the synchronization signal of the quantum key distribution system as claimed in claim 1, wherein the signal parameters in S1 include a synchronization signal frequency fsyn, a signal light frequency fsig, and a time interval tsyn between the signal light and its corresponding synchronization signal.
5. The method for recovering the synchronization signal of the quantum key distribution system according to any one of claims 1 to 4, wherein in the step S2, the time interval between two adjacent signal lights is counted, and the counting method is as follows:
the time interval between any two adjacent signal lights is Tn, wherein n is an integer greater than 1, and the average period Tavgn between any two signal lights is obtained according to Tn;
counting the Navg of the Tavgn by the programmable device at the B end, and accumulating the Tavgn to obtain SUMagg = SUM (Tavgn);
after the statistics of Tavgn is completed, obtaining Tavg = SUMagg/Navg; tavg is the period of the signal light generated by the current A terminal;
and the programmable device at the B end adjusts the phase of a feedback link of the phase-locked loop PLL through the internal delay phase-locked loop DLL according to the Tavg value, and completes the frequency synchronization with the A end.
6. A system for realizing the synchronous signal recovery method for the quantum key distribution system according to any one of claims 1 to 5, characterized by comprising an A terminal and a B terminal which are communicated with each other, wherein the A terminal comprises an A terminal programmable device and a signal light laser which forms a control loop with the A terminal programmable device; the B end comprises a B end programmable device, a delay chip, a time position conversion chip TDC and a single photon detector, and the B end programmable device is sequentially connected with the delay chip and the time position conversion chip TDC to form a communication loop;
the A-end programmable device and the B-end programmable device form a communication channel through a classical link, and the signal light laser of the A-end is respectively connected with the time position conversion chip TDC and the B-end programmable device through single photon detectors and sends detector signals to the two.
7. The system for realizing the synchronization signal recovery method for the quantum key distribution system according to claim 6, wherein the B-side programmable device comprises a frequency synchronization logic module, a Delay Locked Loop (DLL), a Phase Locked Loop (PLL) and a synchronization signal logic module, and the frequency synchronization logic module is communicated with the A-side programmable device through a classical link; the frequency synchronization logic module is connected with a delay phase-locked loop (DLL) and a phase-locked loop (PLL) to form a control path, and a feedback link for mutual communication is arranged between the delay phase-locked loop (DLL) and the PLL;
the phase-locked loop PLL and the synchronous signal logic module form a communication channel; the synchronous signal logic module sends a synchronous signal and a delay chip control signal to the delay chip; the time delay chip transmits the phase-modulated synchronous signal to the time position conversion chip TDC; and the TDC of the time position conversion chip feeds back information to the synchronous signal logic module.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009014601A1 (en) * | 2007-07-20 | 2009-01-29 | Magiq Technologies, Inc. | Qkd system with common-mode dithering |
| CN108075886A (en) * | 2016-11-15 | 2018-05-25 | 上海国盾量子信息技术有限公司 | A kind of automatic timing adjusting method and device for quantum key distribution system |
| CN108206716A (en) * | 2016-12-20 | 2018-06-26 | 科大国盾量子技术股份有限公司 | Synchronous method and device and dissemination system applied to quantum key distribution system |
| CN108737074A (en) * | 2017-04-13 | 2018-11-02 | 科大国盾量子技术股份有限公司 | A kind of information synchronization method and device |
-
2018
- 2018-11-05 CN CN201811306726.2A patent/CN110620646B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009014601A1 (en) * | 2007-07-20 | 2009-01-29 | Magiq Technologies, Inc. | Qkd system with common-mode dithering |
| CN108075886A (en) * | 2016-11-15 | 2018-05-25 | 上海国盾量子信息技术有限公司 | A kind of automatic timing adjusting method and device for quantum key distribution system |
| CN108206716A (en) * | 2016-12-20 | 2018-06-26 | 科大国盾量子技术股份有限公司 | Synchronous method and device and dissemination system applied to quantum key distribution system |
| CN108737074A (en) * | 2017-04-13 | 2018-11-02 | 科大国盾量子技术股份有限公司 | A kind of information synchronization method and device |
Non-Patent Citations (1)
| Title |
|---|
| Anton Plenkin等.Comparative analysis of single-photon synchronization algorithms in the quantum key distribution system.《 2017 IEEE East-West Design & Test Symposium (EWDTS)》.2017, * |
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