CN110611504A - Charge pump circuit with improved dynamic matching performance - Google Patents
Charge pump circuit with improved dynamic matching performance Download PDFInfo
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- CN110611504A CN110611504A CN201810685104.9A CN201810685104A CN110611504A CN 110611504 A CN110611504 A CN 110611504A CN 201810685104 A CN201810685104 A CN 201810685104A CN 110611504 A CN110611504 A CN 110611504A
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- charge pump
- pump circuit
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- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
The invention discloses a charge pump circuit with improved dynamic matching performance, which comprises a source switch charge pump circuit and a bias circuit, wherein the bias circuit is used for biasing a middle node A, B of a switch and a current source in the source switch charge pump circuit, so that when the switch is disconnected, a node A, B is not floated, and the current source can be quickly turned off. According to the invention, by adding the circuit for biasing the intermediate node of the switch and the current source, a floating node is avoided when the switch is disconnected, the current source can be quickly switched off, and the dynamic matching performance is improved.
Description
Technical Field
The invention relates to a charge pump circuit for improving dynamic matching performance, and belongs to the field of charge pump circuits.
Background
Charge Pump (Charge Pump) circuits are widely used in phase-locked frequency synthesizers, which have the following advantages: has infinite capture range, provides infinite dc gain, requires only passive filters, and can be used in combination with a PFD (phase frequency detector). As shown in fig. 1, the charge pump is basically composed of two current sources (a current source Iup and a current source Idn) and two switches (a switch SW1 and a switch SW2), wherein a control signal of the switch is a PFD output signal, and the current sources charge and discharge the loop filter through the switches under the control of the PFD.
The non-ideal factors of the charge pump circuit with the structure mainly comprise: current mismatch (static and dynamic mismatch), charge injection, charge sharing, and charge feedthrough, which can severely impact the performance of the PLL frequency synthesizer system. Especially, the switch in fig. 1 is directly connected to the output node, and the charge injection/clock feedthrough effect is very serious. To alleviate these effects, a source switch charge pump is widely used, and as shown in fig. 2, the charge injection/clock feedthrough effect can be greatly alleviated by placing the switch transistor at the source of the current source MOS transistor without directly contacting the output node.
Simple source-switched charge pumps, while mitigating the charge injection/clock feedthrough effect, do not address the problem of charge-discharge current matching. Even though the current source for charging and discharging under the static state reaches good matching through design, when the switch is disconnected, the middle node of the switch and the current source floats, the current source cannot be quickly switched off, and a longer dynamic change process can occur to the current. Matching this dynamic current needs to be done in both the time and current dimensions, which is difficult.
Disclosure of Invention
The invention provides a charge pump circuit with improved dynamic matching performance, which avoids floating nodes when a switch is disconnected by adding a circuit for biasing the middle nodes of the switch and a current source, and the current source can be quickly switched off, thereby improving the dynamic matching performance.
A charge pump circuit with improved dynamic matching performance includes a source-switched charge pump circuit and further includes a biasing circuit for biasing the intermediate node A, B of the switches and current source in the source-switched charge pump circuit so that when the switches are open, node A, B is not floating and the current source can be quickly turned off.
Preferably, the bias circuit comprises an NMOS transistor M5 and a PMOS transistor M6, a drain of the NMOS transistor M5 is connected to a middle node a of a switch and a current source in the source switch charge pump circuit, a gate of the NMOS transistor M5 is connected to an external bias up, a source of the NMOS transistor M5, a source of the PMOS transistor M6 and an external bias vbias are connected, a gate of the PMOS transistor M6 is connected to an external bias dnb, and a drain of the PMOS transistor M6 is connected to a middle node B of the switch and the current source in the source switch charge pump circuit.
Preferably, the source switch charge pump circuit comprises a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3 and an NMOS transistor M4, wherein a source of the PMOS transistor M1 is connected to an external power supply VDD, a gate of the PMOS transistor M1 is connected to the input end upb, and a drain of the PMOS transistor M1 is connected to a source of the PMOS transistor M2 and a drain of the NMOS transistor M5; the grid electrode of the PMOS tube M2 is connected with an external bias biasp, and the drain electrode of the PMOS tube M2, the drain electrode of the NMOS tube M3 and an output node cpout are connected; the grid electrode of the NMOS tube M3 is connected with an external bias biasn, and the source electrode of the NMOS tube M3 is connected with the drain electrode of the NMOS tube M4 and the drain electrode of the PMOS tube M6; the grid electrode of the NMOS tube M4 is connected with the input end dn, and the source electrode of the NMOS tube M4 is grounded.
The invention reserves the characteristic of a source switch charge pump, the switch is not directly connected with the output node, and the charge injection/clock feed-through effect is lightened. Meanwhile, floating nodes when the switch is disconnected are eliminated, the turn-off speed of the current source is accelerated, and therefore the dynamic matching performance is improved. In other words, the circuit for biasing the middle node of the switch and the current source is added on the basis of the source switch charge pump, so that a floating node when the switch is disconnected is avoided, the current source can be quickly switched off, and the dynamic matching performance is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional charge pump circuit;
FIG. 2 is a schematic diagram of a source switch charge pump;
fig. 3 is a schematic diagram of a basic structure of a charge pump circuit according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 3, a charge pump circuit for improving dynamic matching performance includes a source-switched charge pump circuit, and further includes a biasing circuit for biasing switches (e.g., SW1 and SW2) and an intermediate node A, B of a current source in the source-switched charge pump circuit so that when the switches are turned off, node A, B does not float and the current source can be turned off rapidly. The source switch charge pump circuit comprises two switch MOS tubes and two current source MOS tubes, wherein the switch MOS tubes are respectively arranged at the source electrodes of the current source MOS tubes and are not in direct contact with the output node, so that the charge injection/clock feed-through effect can be greatly reduced.
Preferably, the bias circuit comprises an NMOS transistor M5 and a PMOS transistor M6, a drain of the NMOS transistor M5 is connected to a middle node a of a switch and a current source in the source switch charge pump circuit, a gate of the NMOS transistor M5 is connected to an external bias up, a source of the NMOS transistor M5, a source of the PMOS transistor M6 and an external bias vbias are connected, a gate of the PMOS transistor M6 is connected to an external bias dnb, and a drain of the PMOS transistor M6 is connected to a middle node B of the switch and the current source in the source switch charge pump circuit.
Preferably, the source switch charge pump circuit comprises a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3 and an NMOS transistor M4, wherein a source of the PMOS transistor M1 is connected to an external power supply VDD, a gate of the PMOS transistor M1 is connected to the input end upb, and a drain of the PMOS transistor M1 is connected to a source of the PMOS transistor M2 and a drain of the NMOS transistor M5; the grid electrode of the PMOS tube M2 is connected with an external bias biasp, and the drain electrode of the PMOS tube M2, the drain electrode of the NMOS tube M3 and an output node cpout are connected; the grid electrode of the NMOS tube M3 is connected with an external bias biasn, and the source electrode of the NMOS tube M3 is connected with the drain electrode of the NMOS tube M4 and the drain electrode of the PMOS tube M6; the grid electrode of the NMOS tube M4 is connected with the input end dn, and the source electrode of the NMOS tube M4 is grounded.
The invention reserves the characteristic of a source switch charge pump, the switch is not directly connected with the output node, and the charge injection/clock feed-through effect is lightened. Meanwhile, floating nodes when the switch is disconnected are eliminated, the turn-off speed of the current source is accelerated, and therefore the dynamic matching performance is improved. In other words, the circuit for biasing the intermediate node of the switch and the current source is added on the basis of the source switch charge pump, so that a floating node when the switch is disconnected is avoided, the current source can be quickly turned off (for example, the turning off can be realized below 0.1-1 microsecond), and the dynamic matching performance is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (3)
1. A charge pump circuit for improved dynamic matching performance comprising a source-switched charge pump circuit, further comprising a biasing circuit for biasing the intermediate node A, B of the switches and current source in the source-switched charge pump circuit so that when the switches are open node A, B does not float and the current source is able to turn off quickly.
2. The charge pump circuit for improving dynamic matching performance as claimed in claim 1, wherein said bias circuit comprises an NMOS transistor M5 and a PMOS transistor M6, the drain of said NMOS transistor M5 is connected to the middle node a of the switch and current source in the source-switched charge pump circuit, the gate of said NMOS transistor M5 is connected to the external bias up, the source of said NMOS transistor M5, the source of said PMOS transistor M6 and the external bias vbias are connected, the gate of said PMOS transistor M6 is connected to the external bias dnb, and the drain of said PMOS transistor M6 is connected to the middle node B of the switch and current source in the source-switched charge pump circuit.
3. The charge pump circuit for improving dynamic matching performance of claim 2, wherein the source switch charge pump circuit comprises a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3 and an NMOS transistor M4, the source of the PMOS transistor M1 is connected to an external power supply VDD, the gate of the PMOS transistor M1 is connected to the input upb, and the drain of the PMOS transistor M1 is connected to the source of the PMOS transistor M2 and the drain of the NMOS transistor M5; the grid electrode of the PMOS tube M2 is connected with an external bias biasp, and the drain electrode of the PMOS tube M2, the drain electrode of the NMOS tube M3 and an output node cpout are connected; the grid electrode of the NMOS tube M3 is connected with an external bias biasn, and the source electrode of the NMOS tube M3 is connected with the drain electrode of the NMOS tube M4 and the drain electrode of the PMOS tube M6; the grid electrode of the NMOS tube M4 is connected with the input end dn, and the source electrode of the NMOS tube M4 is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810685104.9A CN110611504A (en) | 2018-06-16 | 2018-06-16 | Charge pump circuit with improved dynamic matching performance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810685104.9A CN110611504A (en) | 2018-06-16 | 2018-06-16 | Charge pump circuit with improved dynamic matching performance |
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| CN110611504A true CN110611504A (en) | 2019-12-24 |
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| CN201810685104.9A Pending CN110611504A (en) | 2018-06-16 | 2018-06-16 | Charge pump circuit with improved dynamic matching performance |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316977B1 (en) * | 2000-07-14 | 2001-11-13 | Pmc-Sierra, Inc. | Low charge-injection charge pump |
| JP2009038468A (en) * | 2007-07-31 | 2009-02-19 | Sony Corp | Current control circuit and current control device |
| US20090121759A1 (en) * | 2007-11-13 | 2009-05-14 | Qualcomm Incorporated | Fast-switching low-noise charge pump |
| CN101610082A (en) * | 2009-07-16 | 2009-12-23 | 哈尔滨工业大学 | Be applied to the source switch-type charge pump in the phase-locked loop |
| CN102158075A (en) * | 2011-03-16 | 2011-08-17 | 东南大学 | Charge pump circuit in charge pump phase-locking loop |
| CN107749709A (en) * | 2017-12-06 | 2018-03-02 | 西安智多晶微电子有限公司 | A kind of charge pump for fpga chip |
-
2018
- 2018-06-16 CN CN201810685104.9A patent/CN110611504A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316977B1 (en) * | 2000-07-14 | 2001-11-13 | Pmc-Sierra, Inc. | Low charge-injection charge pump |
| JP2009038468A (en) * | 2007-07-31 | 2009-02-19 | Sony Corp | Current control circuit and current control device |
| US20090121759A1 (en) * | 2007-11-13 | 2009-05-14 | Qualcomm Incorporated | Fast-switching low-noise charge pump |
| CN101610082A (en) * | 2009-07-16 | 2009-12-23 | 哈尔滨工业大学 | Be applied to the source switch-type charge pump in the phase-locked loop |
| CN102158075A (en) * | 2011-03-16 | 2011-08-17 | 东南大学 | Charge pump circuit in charge pump phase-locking loop |
| CN107749709A (en) * | 2017-12-06 | 2018-03-02 | 西安智多晶微电子有限公司 | A kind of charge pump for fpga chip |
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