CN110609583A - Circuit for stabilizing grid voltage of driving tube by buzzer - Google Patents
Circuit for stabilizing grid voltage of driving tube by buzzer Download PDFInfo
- Publication number
- CN110609583A CN110609583A CN201910788662.2A CN201910788662A CN110609583A CN 110609583 A CN110609583 A CN 110609583A CN 201910788662 A CN201910788662 A CN 201910788662A CN 110609583 A CN110609583 A CN 110609583A
- Authority
- CN
- China
- Prior art keywords
- nmos
- buzzer
- tube
- grid
- nmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000087 stabilizing effect Effects 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a circuit for stabilizing a grid voltage of a driving tube of a buzzer, which comprises a logic control circuit, an NMOS tube MN1 and an NMOS tube MN 2. The input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the output N2 of the logic control circuit is connected to the grid of the NMOS tube MN2, the drain of the NMOS tube MN1 is connected to a power line, the source of the NMOS tube MN1 is connected to the grid G of an NMOS driving tube of the buzzer, the substrate of the NMOS tube MN1 is connected to the ground line, the drain of the NMOS tube MN2 is connected to the grid G of the NMOS driving tube of the buzzer, the source of the NMOS tube MN2 is connected to the ground line, and the substrate of the NMOS tube MN2 is connected to the ground line. The invention controls the opening time of the grid electrodes of the NMOS tubes MN1 and MN2 through the logic control circuit, and plays a role in preventing the grid electrode voltage of the NMOS driving tube of the buzzer from dropping along with the power supply voltage. The circuit has the advantages of simple structure and low cost.
Description
Technical Field
The invention relates to the field of buzzer circuits, in particular to a circuit for stabilizing grid voltage of a driving tube by a buzzer.
Background
As shown in fig. 6, in the conventional gate driving circuit of the buzzer driving tube, when the voltage of the power line drops, the gate voltage of the buzzer driving tube drops along with the voltage of the power line, so that the driving capability of the buzzer driving tube is insufficient, and even the output frequency of the buzzer is unstable.
Disclosure of Invention
The invention provides a circuit for stabilizing grid voltage of a driving tube of a buzzer, which solves the problem that the grid voltage of the driving tube of the buzzer is reduced along with the voltage of a power line when the voltage of the power line is reduced, and prevents the driving capability of the driving tube of the buzzer from being insufficient and even causing the instability of the output frequency of the buzzer when the voltage of the power line is reduced.
In order to solve the above technical problem, the present invention provides a circuit for stabilizing a gate voltage of a driving transistor of a buzzer, including a logic control circuit, an NMOS transistor MN1, and an NMOS transistor MN 2. The input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the output N2 of the logic control circuit is connected to the grid of the NMOS tube MN2, the drain of the NMOS tube MN1 is connected to a power line, the source of the NMOS tube MN1 is connected to the grid G of an NMOS driving tube of the buzzer, the substrate of the NMOS tube MN1 is connected to the ground line, the drain of the NMOS tube MN2 is connected to the grid G of the NMOS driving tube of the buzzer, the source of the NMOS tube MN2 is connected to the ground line, and the substrate of the NMOS tube MN2 is connected to the ground line.
Preferably, the source terminal and the drain terminal of the NMOS transistor MN1 and MN2 are reversed.
The invention has the following beneficial effects: the circuit for stabilizing the grid voltage of the driving tube of the buzzer controls the opening time of the grids of two NMOS tubes MN1 and MN2 through the logic control circuit, and plays a role in preventing the grid voltage of the NMOS driving tube of the buzzer from falling along with the power voltage. The circuit has the advantages of simple structure and low cost.
Drawings
Fig. 1 is a schematic structural diagram of a circuit for stabilizing a gate voltage of a driving tube of a buzzer according to the invention.
Fig. 2 is a circuit timing diagram for stabilizing the gate voltage of the driving tube of the buzzer according to the first embodiment of the invention.
FIG. 3 is a circuit timing diagram for a buzzer to stabilize the driving tube gate voltage according to a second embodiment of the present invention.
FIG. 4 is a circuit timing diagram for a buzzer to stabilize the driving tube gate voltage according to a third embodiment of the present invention.
FIG. 5 is a circuit timing diagram for a buzzer to stabilize the driving tube gate voltage according to a fourth embodiment of the present invention.
Fig. 6 is a schematic diagram of the background art.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the circuit for stabilizing the gate voltage of the driving transistor of the buzzer provided by the present invention includes an edit control circuit, an NMOS transistor MN1, and an NMOS transistor MN 2. The input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the output N2 of the logic control circuit is connected to the grid of the NMOS tube MN2, the drain of the NMOS tube MN1 is connected to a power line, the source of the NMOS tube MN1 is connected to the grid G of an NMOS driving tube of the buzzer, the substrate of the NMOS tube MN1 is connected to the ground line, the drain of the NMOS tube MN2 is connected to the grid G of the NMOS driving tube of the buzzer, the source of the NMOS tube MN2 is connected to the ground line, and the substrate of the NMOS tube MN2 is connected to the ground line.
The first embodiment of the present invention: the working sequence is shown in fig. 2, and referring to fig. 1, F is the frequency signal generated inside the chip, when the level of F changes to open the driving tube of the NMOS of the buzzer, that is, at the beginning of t1, the output N1 of the logic control circuit is at low level, the NMOS transistor MN1 is kept at off state, the output N2 of the logic control circuit changes from high level to low level, the NMOS transistor MN2 changes from on state to off state, the gate G of the buzzer NMOS driving transistor is kept at low level, at the end of t1, the output N1 of the logic control circuit changes from low to high, and since the NMOS transistor MN2 is turned off, therefore, the power supply charges the grid G of the buzzer NMOS driving tube through the MOS tube MN1, the buzzer NMOS driving tube is turned on, when the power supply voltage drops below the grid voltage of the buzzer NMOS driving tube, since the NMOS transistor MN1 is turned off, the gate voltage of the buzzer NMOS driver transistor does not drop along with the power supply voltage.
Second embodiment of the invention: the working sequence is as shown in fig. 3, with reference to fig. 1, F is a frequency signal generated inside the chip, when the level of F changes to open the buzzer NMOS driving tube, the output N1 of the logic control circuit changes from low level to high level, the NMOS tube MN1 changes from off state to on state, the output N2 of the logic control circuit changes from high level to low level, and the NMOS tube MN2 changes from on state to off state, so that the power supply charges the gate G of the buzzer NMOS driving tube through the MOS tube MN1, the buzzer NMOS driving tube is turned on, and when the power supply voltage drops below the gate voltage of the buzzer NMOS driving tube, the gate voltage of the buzzer NMOS driving tube does not drop along with the power supply voltage because the NMOS tube MN1 is turned off.
Third embodiment of the invention: as shown in fig. 4, with reference to fig. 1, F is a frequency signal generated inside the chip, when the level of F changes to turn on the NMOS transistor of the buzzer, i.e. at the beginning of t1, the output N1 of the logic control circuit is at a high level, the NMOS transistor MN1 changes from an off state to an on state, the output N2 of the logic control circuit is at a low level, and the NMOS transistor MN2 remains at an on state, at this time, since the NMOS transistor MN1 and the NMOS transistor MN2 are both in an on state, the magnitude of the current charging the gate G of the NMOS transistor of the buzzer is related to the resistance values of the NMOS transistor MN1 and the NMOS transistor MN2, and the sum of the resistance values of the NMOS transistor MN1 and the NMOS transistor MN2 cannot be too small, which causes a large drop of the power supply inside the chip, at the end of t1, the output N2 of the logic control circuit changes from a high level to a low level, the NMOS transistor MN2 changes from an on state to an off state, so that the power supply charges the gate G of the NMOS transistor MN1 of the buzzer through the, the opening degree of the buzzer NMOS driving tube is increased, and when the power voltage drops to be lower than the grid voltage of the buzzer NMOS driving tube, the grid voltage of the buzzer NMOS driving tube cannot drop along with the power voltage because the NMOS tube MN1 is cut off.
Fourth embodiment of the invention: the working sequence is shown in fig. 5, and referring to fig. 1, F is the frequency signal generated inside the chip, when the level of F changes to open the driving tube of the NMOS of the buzzer, that is, at the beginning of t1, the output N1 of the logic control circuit changes from low level to high level, the NMOS transistor MN1 changes from off state to on state, the output N2 of the logic control circuit changes from high level to low level, the NMOS transistor MN2 changes from on state to off state, therefore, the power supply charges the grid G of the buzzer NMOS driving tube through the MOS tube MN1, the buzzer NMOS driving tube is turned on, at the end of t1, the output N1 of the logic control circuit changes from high level to low level, the NMOS transistor MN1 changes from on state to off state, when the power voltage drops below the gate voltage of the buzzer NMOS driving transistor, since the NMOS transistor MN1 is turned off, the gate voltage of the buzzer NMOS driver transistor does not drop along with the power supply voltage.
The fourth embodiment of the present invention is an improved embodiment of the second embodiment of the present invention, and similarly, the first embodiment of the present invention and the third embodiment of the present invention can also be improved, that is, after the gate G of the NMOS driver of the buzzer is charged, the NMOS transistor MN1 is turned off quickly, and when the power voltage drops, the leakage of the gate of the NMOS driver of the buzzer is reduced.
In summary, the circuit for stabilizing the gate voltage of the driving transistor of the buzzer provided by the invention controls the turn-on time of the gates of the two NMOS transistors MN1 and MN2 through the logic control circuit, so as to prevent the gate voltage of the NMOS driving transistor of the buzzer from dropping along with the power voltage. The circuit has the advantages of simple structure and low cost.
The above description is only an example of the present invention, and is not intended to limit the present invention, and it is obvious to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (2)
1. A circuit for stabilizing grid voltage of a driving tube by a buzzer comprises a logic control circuit, an NMOS tube MN1 and an NMOS tube MN 2. The input F of the logic control circuit is a frequency signal, the output N1 of the logic control circuit is connected to the grid of an NMOS tube MN1, the output N2 of the logic control circuit is connected to the grid of the NMOS tube MN2, the drain of the NMOS tube MN1 is connected to a power line, the source of the NMOS tube MN1 is connected to the grid G of an NMOS driving tube of the buzzer, the substrate of the NMOS tube MN1 is connected to the ground line, the drain of the NMOS tube MN2 is connected to the grid G of the NMOS driving tube of the buzzer, the source of the NMOS tube MN2 is connected to the ground line, and the substrate of the NMOS tube MN2 is connected to the ground line.
2. The circuit for stabilizing the gate voltage of the driving tube of the buzzer as claimed in claim 1, wherein the source terminal and the drain terminal of the NMOS tube MN1 and MN2 are reversed without affecting the normal operation of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910788662.2A CN110609583A (en) | 2019-08-26 | 2019-08-26 | Circuit for stabilizing grid voltage of driving tube by buzzer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910788662.2A CN110609583A (en) | 2019-08-26 | 2019-08-26 | Circuit for stabilizing grid voltage of driving tube by buzzer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110609583A true CN110609583A (en) | 2019-12-24 |
Family
ID=68889996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910788662.2A Pending CN110609583A (en) | 2019-08-26 | 2019-08-26 | Circuit for stabilizing grid voltage of driving tube by buzzer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110609583A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111091803A (en) * | 2020-01-20 | 2020-05-01 | 无锡十顶电子科技有限公司 | Buzzer driving circuit with electromagnetic coil detection function |
| CN111161697A (en) * | 2020-01-21 | 2020-05-15 | 无锡十顶电子科技有限公司 | Solenoid detection circuitry based on bee calling organ |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110204929A1 (en) * | 2008-08-21 | 2011-08-25 | Mitsubishi Electric Corporation | Drive circuit of power semiconductor device |
| CN102498668A (en) * | 2009-09-15 | 2012-06-13 | 三菱电机株式会社 | Gate drive circuit |
| JP2013026262A (en) * | 2011-07-15 | 2013-02-04 | Fujitsu Semiconductor Ltd | Drive circuit and semiconductor integrated circuit |
| US20130194025A1 (en) * | 2012-01-31 | 2013-08-01 | Fujitsu Semiconductor Limited | Driving method and driving circuit of schottky type transistor |
| CN109272976A (en) * | 2018-10-25 | 2019-01-25 | 无锡十顶电子科技有限公司 | A kind of buzzer drive circuit |
| CN210742767U (en) * | 2019-08-26 | 2020-06-12 | 无锡十顶电子科技有限公司 | Circuit for stabilizing grid voltage of driving tube by buzzer |
-
2019
- 2019-08-26 CN CN201910788662.2A patent/CN110609583A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110204929A1 (en) * | 2008-08-21 | 2011-08-25 | Mitsubishi Electric Corporation | Drive circuit of power semiconductor device |
| CN102498668A (en) * | 2009-09-15 | 2012-06-13 | 三菱电机株式会社 | Gate drive circuit |
| JP2013026262A (en) * | 2011-07-15 | 2013-02-04 | Fujitsu Semiconductor Ltd | Drive circuit and semiconductor integrated circuit |
| US20130194025A1 (en) * | 2012-01-31 | 2013-08-01 | Fujitsu Semiconductor Limited | Driving method and driving circuit of schottky type transistor |
| CN109272976A (en) * | 2018-10-25 | 2019-01-25 | 无锡十顶电子科技有限公司 | A kind of buzzer drive circuit |
| CN210742767U (en) * | 2019-08-26 | 2020-06-12 | 无锡十顶电子科技有限公司 | Circuit for stabilizing grid voltage of driving tube by buzzer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111091803A (en) * | 2020-01-20 | 2020-05-01 | 无锡十顶电子科技有限公司 | Buzzer driving circuit with electromagnetic coil detection function |
| CN111161697A (en) * | 2020-01-21 | 2020-05-15 | 无锡十顶电子科技有限公司 | Solenoid detection circuitry based on bee calling organ |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR930003926B1 (en) | Semiconductor integrated circuit | |
| CN109088532B (en) | Current type segmented gate drive circuit with active clamp | |
| US8847661B2 (en) | Level shift device | |
| US20100061164A1 (en) | Fail-safe high speed level shifter for wide supply voltage range | |
| CN108429445B (en) | Soft start circuit applied to charge pump | |
| US10700604B2 (en) | High performance switch devices and methods for operating the same | |
| US6873186B2 (en) | Level shift circuit | |
| US9397557B2 (en) | Charge pump with wide operating range | |
| CN110609583A (en) | Circuit for stabilizing grid voltage of driving tube by buzzer | |
| US20030193348A1 (en) | Level shifting circuit | |
| US9292024B2 (en) | Power gating circuit | |
| CN108551252B (en) | High-voltage grid driving circuit sharing input capacitance | |
| CN108233701B (en) | Buck-boost voltage conversion circuit | |
| KR20090104362A (en) | Inverter Circuit | |
| US4468576A (en) | Inverter circuit having transistors operable in a shallow saturation region for avoiding fluctuation of electrical characteristics | |
| CN108011502B (en) | Circuit for preventing non-monotonous working state signal of voltage reduction regulating circuit | |
| CN210742767U (en) | Circuit for stabilizing grid voltage of driving tube by buzzer | |
| CN114553204B (en) | Driving circuit and method of high-side N-type power MOS | |
| US8736311B2 (en) | Semiconductor integrated circuit | |
| CN115189683A (en) | Drive circuit for low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment | |
| CN210780723U (en) | Circuit for stably driving grid voltage of tube based on buzzer | |
| CN107086863B (en) | Driving circuit for power switch | |
| US8207755B1 (en) | Low leakage power detection circuit | |
| CN100492246C (en) | Method and structure of forming reference voltage | |
| KR102034903B1 (en) | Cmos inverter circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |