CN110609463A - Laser radar multi-pulse time interval measuring system based on FPGA - Google Patents

Abstract

The invention discloses a laser radar multi-pulse time interval measuring system based on an FPGA (field programmable gate array), which comprises a control unit and a timing unit; the control unit is communicated with an external host and controls the timing unit; the timing unit comprises a gating signal generation module, a time identification module and a time delay chain tap type TDC. The gate control signal generation module combines the start signal start and the stop signal stop into a multi-pulse signal gate which can be correctly measured by the TDC and inputs the multi-pulse signal gate into the TDC delay chain, and a first-stage latch unit of the TDC is connected to the time discrimination unit and is used for searching a first rising edge and all falling edges of the gate signal and storing corresponding TDC results. The invention can use single TDC to complete the measurement of a plurality of pulse time intervals in the laser radar, thereby greatly saving the resource occupation of FPGA and the scale of external circuits.

Description

Laser radar multi-pulse time interval measuring system based on FPGA

Technical Field

The invention relates to the technical field of digital measurement, in particular to a multi-pulse time interval measuring system for a pulse laser radar.

Background

Time measurement techniques are used to measure the time intervals of multiple events or to determine the specific time at which a single event occurs, and are of great use in the fields of communications, aerospace, radar, and the like. A common device for high-precision time measurement is a time-to-digital converter (TDC), and the carrier thereof includes an ASIC and an FPGA.

At present, a plurality of TDC schemes realized by using an FPGA (field programmable gate array) can only measure the time interval from the starting time to the occurrence of a single event, and if the time interval of two or more event times is to be measured, a plurality of TDCs can only be used for respectively measuring the events, which occupies doubled resources.

For pulsed lidar, the following two scenarios are considered: firstly, in order to improve the measurement precision, a plurality of laser pulses are continuously sent, so that a plurality of echo pulses are received; secondly, due to penetration and other reasons, the number of echo pulses of one laser beam may be many. The time interval between a plurality of echo pulses is measured, the starting event is the moment of laser emission, the ending event is a plurality of echo pulses of the laser, therefore, a plurality of ending events use the same signal line on a circuit, only the occurrence time is spaced, the situation that the same event continuously occurs for a plurality of times can be understood, the traditional TDC scheme can only measure the occurrence time of the first echo pulse, but cannot measure the time interval of each pulse relative to the starting event.

Disclosure of Invention

In view of the above, the present invention provides a system for measuring the time interval of multiple echo pulses of a laser radar based on an FPGA, which is capable of measuring the time interval of multiple echo pulses of the laser radar by using a single TDC.

The technical scheme for realizing the invention is as follows:

the whole system comprises a control unit and a timing unit.

In a first aspect, a control unit communicates with an external host and controls a timing unit. The control unit comprises a configuration register, a state register, a result register and a measurement control state machine. The configuration register receives the measurement configuration information written by the external host, including the number of pulses expected to be measured, measurement enable, and measurement mode. Two groups of result registers are provided, and after each measurement is completed, the result registers are switched to the other group of result registers, so that the effective time of the measurement result in the continuous measurement is prolonged by the ping-pong mode. The status register stores the number of pulses actually obtained by this measurement and which set of result registers is currently active. The measurement control state machine controls the whole measurement process according to the requirements of the configuration register, including the resetting of the timing unit, the generation of an INT signal for informing a host after the measurement is finished, the switching of the result register and the updating of the state register.

In a second aspect, the timing unit comprises a gating signal generation module, the time of dayA discrimination module and a delay chain tap type TDC. The gate signal generation module combines a start signal start (a laser emission pulse, a rising edge represents a start time) and a stop signal stop (a pulse represents an echo time) of a plurality of echo pulses into a signal to be measured gate which can be correctly encoded by the TDC, and then inputs the signal to be measured gate into a delay chain of the TDC to measure time. The time discriminating module is used for extracting the starting time and each ending time, corresponding to the first rising edge (starting time) and each falling edge (ending time) in the gate signal, and storing the result of the TDC at the moment into the result register. The time delay chain tap type TDC measures the pulse width of an input signal, and the measured pulse width is T-K T_clk+T_start-T_stopK is the output of the coarse grain counter, T_clkTo synchronize the cycles of the clock, T_startAnd T_stopThe values obtained by coding the delay chain at the starting time and the ending time.

The gate signal is a multi-pulse signal, which is reset to low level and changed to high level after the rising edge of start arrives, and each pulse of stop will generate a reverse pulse from '1' to '0' in the gate signal. The waveform to be measured can be correctly coded by a delay chain of the TDC, so that one TDC can complete the measurement of a plurality of echo pulses.

The principle of the time discrimination module is that a D trigger D after a gate signal is input into a TDC first-stage delay unit is detected₁Due to D₁Triggered by system clock, the effective time is one synchronous clock period, so the edge detection of gate can be converted into D₁Detection of the value at two clock cycles. To ensure D₁The change of the gate signal can be correctly reflected, and the pulse width of high and low levels in the gate signal is required to be more than one synchronous clock period. Here, START _ LOCK, CNTD, TDC _ DONE are used to represent the respective states, and the detection steps are as follows:

step 1: after reset, the START _ LOCK, CNTD, TDC _ DONE clear 0, gate signals are low, and the delay chains of each stage are all low, so D₁Is '0'; after the start pulse comes, the gate signal is at high level, D₁From '0' to '1', START _ LOCK is set to 1 at this time, indicating that the START signal is detected, and the result of the current TDC is recorded into the result register.

Step 2: until the stop pulse arrives, gate remains at '1', so D1 is also at '1'; when stop pulse comes, D changes from '1' to '0' due to gate₁Also becomes '0'; thus when START _ LOCK is '1' and D₁When changing from '1' to '0', the value of the CNTD register is added by 1 to indicate the number of stop pulses currently detected, and the result of the current TDC is recorded in the result register.

And step 3: after the end of the stop pulse, the gate becomes '1' again, and then D1 also becomes '1' accordingly, so that when a new stop pulse arrives, step 2 is entered again.

And 4, step 4: as the measurement proceeds, the timing unit repeats in step 2-3, and when the value of CNTD is equal to the number of pulses expected in the configuration register, or the coarse grain counter of TDC issues a time-out signal, the timing unit sets TDC _ DONE to '1', informing the control unit that the measurement is completed.

The delay chain tapped TDC is composed of a coarse grain counter, a delay chain, a latch array and an encoder. The coarse-grained counter STARTs counting after START _ LOCK is '1' in the time identification unit; the encoder scheme is a multi-stage adder array, counting the number of '1's in the latch unit. If the total number of the delay chain and the latch unit is M stages, the output of the encoder is N, the average delay time of each stage of the delay unit is 1LSB, and T is_start＝N*LSB，T_stop(M-N) × LSB. In order to ensure that the full adder can correctly encode, only one changing edge is required on the delay chain, namely, the pulse widths of high and low levels in the gate signal are greater than the delay length of the delay chain. The time discrimination module has similar requirements on the gate signal, and the delay length of the delay chain is slightly larger than one synchronous clock period, so that the gate signal only needs to meet the requirements of an encoder finally.

The invention has the beneficial effects that: the invention can complete the measurement of a plurality of pulse time intervals in the laser radar by using a single TDC, greatly saves the resource occupation of an FPGA and the scale of an external circuit, and has important application value in the field of laser radar and related time measurement.

Drawings

FIG. 1 is a block diagram illustrating the general components of one embodiment of the present invention.

FIG. 2 is a state transition diagram of the timing control logic of the present invention.

Fig. 3 is a schematic diagram of a gate signal generated by the gating signal generation module.

Detailed Description

The invention is described in detail below by way of example with reference to the accompanying drawings.

The embodiment uses Xilinx Spartan6 to realize the laser radar multi-echo pulse time interval measuring system, and the specific model is XC6SLX9-2tqg 144. Fig. 1 is a block diagram of the general composition of a system for measuring the multi-echo pulse time interval of a laser radar based on an FPGA according to the present invention, as shown in fig. 1, which includes two parts, namely a control unit and a timing unit.

In this embodiment, the state register and the configuration register of the control unit are implemented by using a distributed ram, and the entities of the state register and the configuration register are a D flip-flop and an addressing logic in an FPGA. The measurement enable bit in the configuration register passes through an inverter and then 'or' goes up the global reset signal, and finally is connected to the reset terminal of the timing unit, so that when the measurement enable bit is 0, the timing unit is in a reset state, and further the measurement is not performed any more.

The result register is realized by BRAM embedded in the FPGA and is configured into a simple dual-port mode, the host end is read only, the FPGA end is written only, the data bit width of the FPGA end is configured into 32 bits, and the depth is 256. A BRAM of 256 depths corresponds to 8-bit address lines, denoted A₀-A₇Since the result registers are divided into two groups, address line A is led out₇As chip selects for these two sets of registers, A₇When 0, it represents the first set of result registers, A₇A second set of result registers is indicated at 1. And A is₀-A₆The result is stored in corresponding position of BRAM, and it is known that the first stop pulse corresponding to address 0x00 when the start arrivesGo to 0x01, and so on. Thus, each set of result registers can hold 128 data, so the number of stop pulses that can be identified is 127, and expanding the result registers increases the maximum number of stop pulses that the system can record.

The timing control state machine has 3 states: state _ RST, State _ START, State _ WRITE _ DONE, the STATE transition diagram of which is as in FIG. 2. The STATE _ RST is in an idle STATE, in which an INT signal notifying the host is pulled low, and enters a STATE _ START STATE when a timer START _ LOCK signal is detected to be '1'; in the STATE _ START STATE, when detecting that the timing unit TDC _ DONE is '1', entering the STATE _ WRITE _ DONE STATE; in the STATE _ WRITE _ DONE STATE, a jump is made immediately to the STATE _ RST STATE, while performing the following operations: pulling the INT signal high; writing CNTD and A to status register₇A value of (d); a is to be₇Negating, thereby switching the current result register to another set; if continuous measurement is not enabled, register measurement enable bit 0 will be configured. The INT signal or the global reset signal is connected to the timing unit, so that the timing unit is reset after one measurement is finished. So far, the reset part of the timing unit is also completed, and the reset part is composed of a global reset signal, an INT signal and a signal obtained by inverting a measurement enable bit, and the three signals are subjected to OR logic.

A schematic diagram of the gate signal generated by the gate signal generating module is shown in fig. 3, and in order to achieve the illustrated effect, the following implementation scheme is used in the present embodiment. A D trigger is used, the clk end is connected with a start signal, the data end is connected with '1', the clr end is connected with a reset signal of the timing unit, and therefore the Q end of the D trigger is kept to be '1' after the rising edge of the start signal occurs. The stop signal passes through a not gate and then passes through an AND gate together with the Q end of the D flip-flop to obtain the required gate signal.

The moment discrimination module detects a D trigger D after a gate signal is input into a TDC first-stage delay unit₁Due to D₁Triggered by system clock, the effective time is one synchronous clock period, so the edge detection of gate can be converted into D₁Detection of values in two clock cyclesIn this example, 1 register (D flip-flop) is used to store D₁The value of the last cycle, called D₀Through D₀，D₁The combination of (1) can carry out edge detection on the gate, and the truth table is as follows: "01", rising edge; a "10" falling edge; low level "00"; "01" high. To ensure D₁The change of the gate signal can be correctly reflected, and the pulse width of high and low levels in the gate signal is required to be more than one synchronous clock period. START _ LOCK, CNTD, TDC _ DONE are used here to represent the respective states; the measurement steps are as follows:

step 1: after resetting, the above START _ LOCK, CNTD, TDC _ DONE, WE clear 0, gate signal are '0', each stage of delay chain is low level, D₀D₁Has a value of "00"; after the start pulse comes, the gate signal is at high level, D₀D₁Becomes "01"; thus when D is₀D₁To "01", and START _ LOCK is 0, set START _ LOCK to 1, indicating that the START signal was detected, save the result of the current TDC to the result register, at which time CNTD is 0, so the result of START is saved to the 0x00 address of the result register.

Step 2: before the arrival of the stop pulse, the gate is kept at '1', D₀D₁Is "11"; when the stop pulse arrives, D due to the falling edge of gate₀D₁Is "10"; thus when START _ LOCK is '1' and D₀D₁If "10", the value of CNTD register is incremented by 1 to indicate the number of stop pulses currently detected, and the result of current TDC is stored in the corresponding address of the result register.

And step 3: after stop pulse ends, gate again becomes '1', D₀D₁Has a value of "11", so that when a new stop pulse arrives, step 2 is entered again.

And 4, step 4: as the measurement proceeds, the time discriminating module repeats step 2-3, and when the value of CNTD is equal to the expected number of pulses in the configuration register or the coarse granularity counter of TDC sends out a time-out signal, the timing unit sets TDC _ DONE to '1', and informs the control unit that the measurement is completed.

Persons in the relevant field know the basic implementation mode of the delay chain tap type TDC, and the delay chain tap type TDC comprises a coarse grain counter, a delay chain, a latch array and a coder. The TDC synchronization clock implemented in this embodiment is 250MHz, the delay chain is 58 stages, the delay time that can be covered by the measured delay chain is about 4292ps, and the corresponding latch array is 58 accordingly. The coarse-granularity counter STARTs counting after START _ LOCK in the time identification unit is '1', and generates an overtime signal after the preset time of 20 mu s is reached; to meet the timing requirements, the encoder scheme in this example is a three-level adder array: the first stage is provided with 8 adders, except the 8 th adder, each adder sums up 7 latch units to output 3-bit data, and the 8 th group sums up the remaining 10 latch units to obtain 4-bit data; the second stage is provided with two adders, and each adder respectively sums the outputs of the 4 adders of the first stage and outputs 5-bit data; the third stage has an adder that sums the results of the two adders in the second stage to output a final result of 6 bits. The encoder counts the number of '1' in the latch unit, if the delay chain and the latch unit have M stages in total, the output of the encoder is N, the average delay time of each stage of delay unit is 1LSB, then T_start＝N*LSB，T_stop(M-N) × LSB. This coding scheme is simple to implement, but requires only one edge change on the delay chain, i.e. the pulse width of the high and low levels in the gate signal should be greater than the delay length of the delay chain. In this example, it is required that the hold time of the high and low levels of the gate signal is at least 4292ps, that is, the pulse width of the stop pulse should be greater than 4292ps, the interval between two stop pulses should be greater than 8584ps, and the interval between start and stop should be 4292 ps.

In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A laser radar multi-pulse time interval measuring system based on FPGA is characterized by comprising a control unit and a timing unit;

the control unit is communicated with an external host and controls the timing unit; the control unit comprises a configuration register, a state register, a result register and a measurement control state machine;

the timing unit comprises a gating signal generation module, a time identification module and a time delay chain tap type TDC. The gating signal generation module combines the start signal start and the stop signals stop of the multiple echo pulses into a signal to be measured gate which can be correctly coded by the TDC; the time discrimination module is used for extracting the starting time and each ending time and storing the result of the TDC at the moment into a result register. The delay chain tap type TDC measures the pulse width of an input signal.

2. The lidar multi-pulse interval measurement system of claim 1, wherein the configuration register receives measurement configuration information written by an external host, including a number of pulses expected to be measured, measurement enable, measurement mode; the measurement mode comprises continuous measurement and single measurement, and when the continuous measurement is carried out, after one measurement is finished, the measurement control state machine enables the position 0 to be measured, so that the measurement is stopped until the host machine enables the position 1 to be measured again.

3. The lidar multi-pulse interval measurement system of claim 1, wherein the result registers are divided into two groups, designated A, B, operating in ping-pong mode.

4. The lidar multi-pulse time interval measurement system of claim 3, wherein the result register is located in a dual port BRAM internal to the FPGA.

5. The lidar multi-pulse interval measurement system of claim 1, wherein the timing control state machine has 3 states: STATE _ RST, STATE _ START, STATE _ WRITE _ DONE; the STATE _ RST is in an idle STATE, in which an INT signal notifying the host is pulled low, and enters a STATE _ START STATE when a timer START _ LOCK signal is detected to be '1'; in the STATE _ START STATE, when detecting that the timing unit TDC _ DONE is '1', entering the STATE _ WRITE _ DONE STATE; in the STATE _ WRITE _ DONE STATE, a jump is made immediately to the STATE _ RST STATE, while performing the following operations: pulling the INT signal high; writing the number of pulses measured this time and the group number of the current result register into a state register; switching the result registers to another set; if continuous measurement is not enabled, register measurement enable bit 0 will be configured.

6. The lidar multi-pulse interval measurement system of claim 1, wherein the gate signal generated by the gate signal generation module is a multi-pulse signal that is reset to a low level and then to a high level after a start rising edge, and each pulse of stop generates a reverse pulse from '1' to '0' in the gate signal.

7. The lidar multi-pulse interval measurement system of claim 6, wherein the time discrimination module is capable of detecting a first rising edge and all falling edges of the gate.

8. The lidar multi-pulse interval measurement system of claim 7, wherein the timing discrimination module detects edges of the gate using values of the TDC first stage latch unit at the present clock cycle and a previous clock cycle.

9. The lidar multi-pulse time interval measurement system of claim 8, wherein the detection method of the time discrimination module is as follows:

step 1: after resetting, three registers of START _ LOCK, CNTD and TDC _ DONE are cleared, D₀D₁Has a value of "00"; after the start pulse arrives, the gate has the first rising edge, D₀D₁Becomes "01"; thus when D is₀D₁When the result is "01" and START _ LOCK is 0, setting START _ LOCK to 1, indicating that the START signal is detected, and saving the result of the current TDC in the result register;

step 2: before arrival of stop pulse, D₀D₁Is "11"; when the stop pulse arrives, the gate has a falling edge, D₀D₁Becomes "10"; thus when START _ LOCK is '1' and D₀D₁When the value of (1) is '10', adding 1 to the value of the CNTD register to represent the number of stop pulses detected currently, and storing the result of the current TDC into a corresponding address of a result register;

and step 3: after stop pulse ends, gate again becomes '1', D₀D₁Is "11", so that when a new stop pulse arrives, step 2 is entered again;

and 4, step 4: as the measurement proceeds, the time discriminating module repeats step 2-3, and when the value of CNTD is equal to the expected number of pulses in the configuration register or the coarse granularity counter of TDC sends out a time-out signal, the timing unit sets TDC _ DONE to '1', and informs the control unit that the measurement is completed.