CN110597643A - Inter-core communication method, processor and electronic equipment - Google Patents
Inter-core communication method, processor and electronic equipment Download PDFInfo
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- CN110597643A CN110597643A CN201910814966.1A CN201910814966A CN110597643A CN 110597643 A CN110597643 A CN 110597643A CN 201910814966 A CN201910814966 A CN 201910814966A CN 110597643 A CN110597643 A CN 110597643A
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The embodiment of the application discloses an inter-core communication method, a processor and electronic equipment. The method comprises the following steps: the first core executes the information sending instruction; the message matrix unit responds to the message sending instruction to establish a data path between the first core and the second core; the second core executes the information reading instruction; if the fact that communication data sent by a first core are read is detected, feeding back notification information to the first core by a message matrix unit; the first core is in an instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time. The method realizes the communication between the cores by using the message matrix unit, and the message matrix unit can feed back the processing condition of the communication data in real time, so that the first core sending the data can know the processing condition of the data sent by the first core in real time.
Description
Technical Field
The present application relates to the field of electronic technologies, and in particular, to an inter-core communication method, a processor, and an electronic device.
Background
As the performance requirements of processors increase, more processes have more cores that can independently process data. For these multi-core processors, inter-core communication between cores and before cores is sometimes required. And the transmission is performed through the message queue in the related inter-core communication, so that real-time feedback that data processing cannot be performed is caused.
Disclosure of Invention
In view of the above problems, the present application provides an inter-core communication method, a processor, and an electronic device to improve the above problems.
In a first aspect, the present application provides an inter-core communication method, which is applied to an electronic device, where the electronic device at least includes a first core, a second core, and a message matrix unit, where the message matrix unit has interfaces for communicating with each core, and the message matrix unit is used for performing information interaction between the cores, and the method includes: the first core executes an information sending instruction to send the identification of the second core as a communication target and communication data to the message matrix unit; the message matrix unit responds to the information sending instruction to establish a data path between the first core and the second core; the second core executes an information reading instruction to read the communication data from the message matrix unit; if the fact that the communication data sent by the first core are read is detected, the message matrix unit feeds back notification information to the first core; the first core is in an instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
In a second aspect, the present application provides an electronic device, which at least includes a first processor, a second processor, and a message matrix unit, where the first processor includes at least a first core, the second processor includes at least a second core, the message matrix unit has an interface for communicating with each core, and the message matrix unit is used for information interaction between each core; the first core is used for executing an information sending instruction so as to send the identification of the second core as a communication target and communication data to the message matrix unit; the message matrix unit is used for responding to the information sending instruction to establish a data path between the first core and the second core; the second core is used for executing an information reading instruction to read the communication data from the message matrix unit; if the fact that the communication data sent by the first core is read is detected, the message matrix unit is further used for feeding back notification information to the first core; the first core is in an instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
In a third aspect, the present application provides a processor, including at least a first core, a second core, and a message matrix unit, where the message matrix unit has interfaces for communicating with the cores; the first core is used for executing an information sending instruction so as to send the identification of the second core as a communication target and communication data to the message matrix unit; the message matrix unit is used for responding to the information sending instruction to establish a data path between the first core and the second core; the second core is used for executing an information reading instruction to read the communication data from the message matrix unit; if the fact that the communication data sent by the first core is read is detected, the message matrix unit is further used for feeding back notification information to the first core; the first core is in an instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
In a fourth aspect, the present application provides an electronic device comprising a processor and a memory; one or more programs are stored in the memory and configured to be executed by the processor to implement the methods described above.
In a fifth aspect, the present application provides a computer readable storage medium having program code stored therein, wherein the method described above is performed when the program code is executed by a processor.
According to the inter-core communication method, the processor and the electronic device, the multi-core processor at least comprises a first core, a second core and a message matrix unit, and under the condition that the message matrix unit is provided with interfaces for communicating with the cores, the first core needing to send communication data in the cores executes an information sending instruction so as to send the identification of the second core serving as a communication target and the communication data to the message matrix unit. And the message matrix unit responds to the information sending instruction to establish a data path between the first core and the second core. Furthermore, the second core executes an information reading instruction to read the communication data from the message matrix unit, and then the message matrix unit feeds back notification information to the first core if it is detected that the communication data sent by the first core is read. And the first core is in a blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time. Therefore, by the mode, the communication between the cores can be realized by the message matrix unit, the message matrix unit can feed back the processing condition of the communication data in real time, the first core sending the data can know the processing condition of the data sent by the first core in real time, and the communication efficiency between the cores can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating an architecture of a multi-core processor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an arbitration module in a multi-core processor according to an embodiment of the present application;
fig. 3 is a flowchart illustrating an inter-core communication method according to an embodiment of the present application;
FIG. 4 is a diagram illustrating arbitration performed by an arbitration module in a multi-core processor according to an embodiment of the present application;
FIG. 5 is a flow chart illustrating a method for inter-core communication according to another embodiment of the present application;
FIG. 6 is a flow chart illustrating a method of inter-core communication according to yet another embodiment of the present application;
FIG. 7 is a schematic diagram illustrating an architecture of a multi-core processor according to an embodiment of the present application;
fig. 8 is a block diagram illustrating a structure of an inter-core communication apparatus according to an embodiment of the present disclosure;
fig. 9 is a block diagram illustrating an inter-core communication apparatus according to another embodiment of the present application;
fig. 10 is a block diagram illustrating an electronic device for executing an inter-core communication method according to an embodiment of the present application;
fig. 11 is a block diagram illustrating another electronic device for performing an inter-core communication method according to an embodiment of the present application;
fig. 12 is a storage unit according to an embodiment of the present application, configured to store or carry program code for implementing an inter-core communication method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
System-on-a-chip (SoC) refers to a technology for grouping all or part of necessary electronic circuits by integrating a complete System on a single chip. A complete system generally includes a Central Processing Unit (CPU), a memory, and peripheral circuits. System-on-chip technology is commonly applied to small, increasingly complex consumer electronic devices. For example, a system-on-chip of a sound detection device is a device that provides all users with audio reception, analog-to-digital converter (ADC), microprocessor, necessary memory, and input-output logic control on a single chip. The system-on-chip is also applicable to single-chip wireless products, such as bluetooth devices, supporting single-chip WLAN and cellular phone solutions.
With the development of technology, more systems on chip are beginning to adopt multi-core processors (multi-core CPUs). A multi-core processor is a processor that integrates two or more complete computing engines (cores) into one processor, and the processor can support multiple processors on a system bus, and a bus controller provides all bus control signals and command signals. In the research of the inventor, the inventor finds that, in a multi-core processor of a related system on a chip, inter-core communication between cores is performed in a message queue mode generally, and by the mode, waste of area is caused, and on the other hand, real-time feedback cannot be achieved.
Therefore, after finding the above problems in the research, the inventors have proposed an inter-core communication method, a processor, and an electronic device that can improve the above problems in the present application. Therefore, through the mode, the communication between the cores can be realized by the message matrix unit, and the message matrix unit can feed back the processing condition of the communication data in real time, so that the first core sending the data can know the processing condition of the data sent by the first core in real time.
The architecture of the electronic device according to the embodiment of the present application will be described first.
As shown in fig. 1, in the architecture of the electronic device shown in fig. 1, a plurality of cores such as core 0, core 1, core 2, and core 3 are exemplarily shown, and the electronic device further includes a message matrix unit. The cores are connected by a message MATRIX unit (MATRIX), which is used to realize the interconnection of the paths between the cores, and this is a fully connected network structure. The specific connection structure of the message matrix unit and the plurality of cores is shown in fig. 2. Also shown in fig. 2 are arbitration modules included in the message matrix unit, one for each core. It will be appreciated that the message matrix unit has interfaces for communicating with the various cores, wherein an arbitration block is used to arbitrate which particular core has communication authority when there are multiple cores that desire to communicate with the same core based on their own interface with the message matrix unit.
Note that a plurality of cores such as core 0, core 1, core 2, and core 3 may belong to the same processor, or may belong to different processors. For example, core 0 and core 1 belong to a first processor, while core 2 and core 3 belong to a second processor. Core 0 may also belong to a first processor, while core 1, core 2, and core 3 belong to a second processor.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 3, an inter-core communication method provided in an embodiment of the present application is applied to an electronic device, where the electronic device includes at least a first core, a second core, and a message matrix unit, and the message matrix unit has an interface for communicating with each core, and the method includes:
step S110: the first core executes an information transmission instruction to transmit the identification of the second core as a communication target and communication data to the message matrix unit.
In the embodiment of the application, each core in the multi-core processor is correspondingly configured with an identifier for uniquely identifying the identity of the core. In this way, when the first core serving as the communication data sender executes the information sending instruction, the parameter sent to the message matrix unit carries the identifier of the second core serving as the communication target and the communication data. It can be understood that, after receiving the identifier of the second core that is a communication target, the message matrix unit may determine that the communication target is to send communication data to the second core, and the communication data included in the parameter is data that needs to be sent to the second core.
It should be noted that, in this embodiment, the message matrix unit may implement data interaction with each core through an interface with each core. Specifically, the message matrix unit may determine which core is currently in communication with through a change in the level, and after detecting that the first core executes the information sending instruction, the corresponding message matrix unit updates the interface signal according to a parameter carried in the information sending instruction. As shown in fig. 4, there is an interface (Src _ bundle) between the arbitration modules corresponding to core 1, core 2, and core 3 and core 0. Wherein, Src _ bundle includes the following three interface signals:
and the Src _ vldx is used for representing that the core x is executing an information sending instruction, and the level of the Src _ vldx is pulled high when the core x has a message to send, wherein x represents that the core x sends the message to the arbitration module.
Src _ msgx [31:0] where x represents the specific message sent from core x to the arbitration module, including core x to send.
Src _ ackx, where x represents the message sent from the arbitration module to core x, the Src _ ackx level will be pulled high after core 0 receives the message, indicating that the message has been received.
Step S120: the message matrix unit responds to the information sending instruction to establish a data path between the first core and the second core.
It will be appreciated that if there are only two cores in a multi-core processor, then communication between the two cores may be freely triggered. That is, in this manner, when a first core, which is a communication data sender, desires to send data to a second core, which is a communication data receiver, the message matrix unit may directly establish a data path between the first core and the second core without detection. However, when the multi-core processor includes more cores in addition to the first core and the second core, the message matrix unit needs to perform arbitration to determine which core has the communication right. For example, as shown in fig. 4, the multi-core processor includes a core 0, a core 1, a core 2, and a core 3. If core 1, core 2, and core 3 all need to communicate with core 0 at the same time, the matrix module corresponding to core 0 needs to perform arbitration to determine which core 1, core 2, and core 3 can communicate with core 0.
Step S130: the second core executes the information reading instruction to read the communication data from the message matrix unit.
Step S140: and if the fact that the communication data sent by the first core is read is detected, the message matrix unit feeds back notification information to the first core.
The first core is in the instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
It should be noted that the instruction blocking state indicates that the core does not execute a subsequent information sending instruction, information reading instruction, or other instruction.
It should be noted that the first core and the second core in this embodiment may belong to the same processor, or may belong to different processors.
According to the inter-core communication method, under the condition that a multi-core processor at least comprises a first core, a second core and a message matrix unit, and the message matrix unit is provided with an interface for communicating with each core, the first core needing to send communication data in a plurality of cores can execute an information sending instruction so as to send the identification of the second core serving as a communication target and the communication data to the message matrix unit. The message matrix unit responds to the information sending instruction to establish a data path between the first core and the second core. Furthermore, the second core executes the information reading instruction to read the communication data from the message matrix unit, and then the message matrix unit feeds back notification information to the first core if the communication data sent by the first core is detected to be read. And the first core is in a blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time. Therefore, by the mode, the communication between the cores can be realized by the message matrix unit, the message matrix unit can feed back the processing condition of the communication data in real time, the first core sending the data can know the processing condition of the data sent by the first core in real time, and the communication efficiency between the cores can be improved.
Referring to fig. 5, an inter-core communication method provided in an embodiment of the present application is applied to a multi-core processor, where the multi-core processor at least includes a first core, a second core, and a message matrix unit, where the message matrix unit has an interface for communicating with each core, and the method includes:
step S210: the first core executes a first information transmission instruction to transmit, to the message matrix unit, an identification of the second core as a communication target, a data amount identification for characterizing a data amount of the remaining unsent communication data, and the communication data.
It should be noted that the data that can be transferred between the core and the message matrix unit each time is limited. In the process of the first communication between the core and the message matrix unit, the core needs to carry the identification of the second core serving as the communication target in addition to the actual communication data, so that the message matrix unit determines who the communication target is, and therefore when the data volume of the communication data is large, the first core needs to send all the communication data to the message matrix unit for multiple times. Then, in the case where transmission needs to be performed in multiple times, for the first information transmission instruction, it is referred to as a first information transmission instruction in this embodiment.
| ID | 31：20 | ID indicating target core |
| cnt | 19:16 | Indicating the number of subsequent data |
| val | 15:0 | Content of 16bit message |
The above table shows the instruction format of a 32-bit first message sending instruction. Wherein, the field ID is used to characterize the identification of the core as the communication target, and its corresponding "31: 20" characterizes that the address of the corresponding data stored in the memory is offset from the specified position by 20 bits to 31 bits. The field cnt is used for representing the number of the subsequent data which are left and not transmitted, wherein the data which are left for representing that 32 bits are left and not transmitted are left 1, and the corresponding '19: 16' represents that the address of the corresponding data stored in the memory is 16 bits to 19 bits from the specified position. The field val is used to represent the communication data carried by the current instruction, and its corresponding "15: 20" represents that the address of the corresponding data stored in the memory is 15 bits from the specified position to the offset. It can be understood that the first information sending instruction is implemented by writing specific data into a specific register, and when the processor detects that the specific register has a write operation, the instruction fetch unit of the first core is frozen according to the situation, so as to implement the instruction blocking function of the first core, and meanwhile, the value of the register of 32 bits is sent to the message matrix unit interface.
Step S220: the message matrix unit responds to the information sending instruction to establish a data path between the first core and the second core.
Step S230: the second core executes the first information reading instruction to read the communication data from the message matrix unit.
Correspondingly, when the second core as the communication target reads the message sent by the first information sending instruction executed by the first core, the second core executes the first information reading instruction.
It is to be understood that the instruction format of the first information reading instruction and the instruction format of the first information sending instruction are the same. The difference is that the first information reading instruction represents that specific data is written into a specific register, when the specific register is detected to have write operation, the instruction fetch unit of the second core is frozen according to the situation, so that the instruction blocking function of the second core is realized, and then the output 32-bit register value is obtained from the message matrix unit. The value taking unit may be understood as a unit that performs instruction execution in the core (for example, a unit that executes the first information reading instruction).
Step S240: and if the fact that the communication data sent by the first core is read is detected, the message matrix unit feeds back notification information to the first core.
The communication message of this feedback may allow the first core to determine that previously transmitted communication data has been read by the second core. The second core in the blocking state may exit the blocking state and continue executing subsequent instructions.
Step S250: and if the data quantity identification represents that the communication data is partial communication data, the first core executes at least one second information sending instruction so as to send the remaining unsent communication data to the message matrix unit.
Step S260: the second core executes at least one time of the second information reading instruction to read the communication data transmitted based on the second information transmission instruction from the message matrix unit.
It should be noted that, when the first core starts to execute one information transmission instruction (may be the first information transmission instruction or the second information transmission instruction) and receives the notification information about the execution result of the instruction, the first core may be in an instruction blocking state, that is, the subsequent information transmission instruction or another instruction may not be executed. In this manner, after the first core executes the second information sending instruction once, the first core may be in the instruction blocking state, and then after the communication data sent by the second information sending instruction is read by the second core, that is, after the second core executes the second information sending instruction once, the first core may execute the second information sending instruction next time to send subsequent communication data. Correspondingly, after the second information reading instruction is executed once by the second core, the second core is also in an instruction blocking state until the second information sending instruction is executed again by the first core.
It is understood that arbitration is required. When the first core starts to execute an information sending instruction once, under the condition that the information sending instruction is successfully arbitrated by the information matrix unit (namely, the first core is arbitrated to have communication authority), and the second core executes an information reading instruction once to read communication data sent by the information sending instruction this time, the instruction blocking state is released, so that the next instruction is executed. Therefore, the communication authority of the core (for example, a first core) is arbitrated for the message matrix unit, so that when a plurality of cores (for example, a third core sends a message to a request to send a message to a second core in addition to the first core) send the message to one core (for example, the second core) in sequence, message confusion caused by the fact that the plurality of cores send the message to one core at the same time can be avoided.
Step S270: and if the first core finishes sending all the communication data to the second core, the message matrix unit closes the data path. As a mode, if the message matrix unit receives a target message sent by the first core and indicating that data transmission is completed, it is determined that the first core completes sending all communication data to the second core.
The first information sending command, the second information sending command, the first information reading command, and the second information reading command referred to in the present application will be described below by way of an example.
Assuming that core 1 is to send a 48-bit message msg [47:0] to core 2, the specific communication process is as follows:
the core 1 executes a first information sending instruction, the parameter is {2,1, msg [15:0] }, then the message matrix unit modifies the interface signal according to the parameter {2,1, msg [15:0] } after the arbitration core 1 has the communication authority, and then the data path between the cores 2 corresponding to the core 1 core identifier "2" is opened subsequently.
Wherein, it is understood that "2" is the identification of the target core, "1" represents that 1 32bit data is not transmitted, and "msg [15:0 ]" represents the communication data of the finger of the register. Thereafter, core 2 executes a first information reading instruction to read {2,1, msg [15:0] }fromthe message matrix unit, and can further read the actual communication data according to the value of the register msg [15:0], and knows that core 1 has 32 bits of communication data to send based on the parameter of "1".
Furthermore, the core 1 receives the notification message fed back by the message matrix unit, and then continues to execute the second message sending instruction. Wherein, the parameter carried in the second information sending instruction is msg [47:32 ]. It is understood that the location of [31:16] in the first information transmission instruction stores two parameters of "2" and "1", so that the parameter carried by the second information transmission instruction is msg [47:32 ]. Then, after the second message sending command is arbitrated, the second core executes a second message reading command to read the communication data corresponding to msg [47:32 ].
It will be appreciated that core 1 will be in the instruction blocking state after sending the first information sending instruction, and core 1 in the instruction blocking state will not execute subsequent instructions. When the core 1 receives the notification message fed back by the message matrix unit, the instruction blocking state is released, so that the subsequent instruction, for example, the second information sending instruction, is further executed. Similarly, the core 2 may be in the instruction blocking state after the first information reading instruction, and the core 2 in the instruction blocking state may not execute the subsequent instruction until the core 1 sends the second information sending instruction, and the instruction blocking state may not be released so as to execute the second information reading instruction.
According to the inter-core communication method, the message matrix unit responds to the first information sending instruction to establish a data path between the first core and the second core. Furthermore, the second core executes the first information reading instruction to read the communication data from the message matrix unit, and then the message matrix unit feeds back notification information to the first core after detecting that the communication data sent by the first core is read. And the first core is in a blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
And after receiving the feedback notification information for the first time, the first core starts to execute a second information transmission instruction to transmit the remaining unsent communication data to the message matrix unit when the remaining communication data are unsent. Correspondingly, the second core executes at least one second information reading instruction to read the communication data sent based on the second information sending instruction from the message matrix unit. Therefore, through the mode, the communication between the cores can be realized by the message matrix unit, and the message matrix unit can feed back the processing condition of the communication data in real time, so that the first core sending the data can know the processing condition of the data sent by the first core in real time.
Referring to fig. 6, an inter-core communication method provided in an embodiment of the present application is applied to an electronic device, where the electronic device at least includes a first core, a second core, a third core, and a message matrix unit, where the message matrix unit has an interface for communicating with each core, the message matrix unit further includes an arbitration module, and each core corresponds to one arbitration module; the method comprises the following steps:
step S310: the first core executes an information transmission instruction to transmit the identification of the second core as a communication target and communication data to the message matrix unit.
Step S320: and if the message matrix unit receives the information sending instruction sent by the first core and the information sending instruction sent by the third core at the same time, and the target core corresponding to the information sending instruction sent by the third core is the second core, calling an arbitration module corresponding to the second core to arbitrate the communication authority of the first core.
Step S330: and if the first core is judged to have the communication authority, establishing a data path between the first core and the second core.
In the embodiment of the present application, there are various ways to determine the communication right.
As one mode, the step of invoking an arbitration module corresponding to the second core to arbitrate the communication permissions of the first core and the third core includes: calling an arbitration module corresponding to the second core to judge the communication priority of the communication of the third core of the first core, which is currently requested to communicate with the second core; and if the communication priority of the first core is higher than that of the third core, judging that the first core has the communication authority.
As another way, invoking an arbitration module corresponding to the second core to calculate a communication permission parameter of the third core of the first core requesting to communicate with the second core at present, so as to obtain a permission score; and if the authority score of the first core is the highest, judging that the first core has the communication authority. The communication authority parameters may include a communication priority, a data processing power consumption, and a priority of currently processed data. In this way, the message matrix unit may call the arbitration module to calculate the scores corresponding to the communication priority, the data processing power consumption, and the priority of the currently processed data of the first core, respectively, so as to obtain the authority score of the first core, and may calculate the scores corresponding to the communication priority, the data processing power consumption, and the priority of the currently processed data of the third core, so as to obtain the authority score of the third core.
Step S340: the second core executes the information reading instruction to read the communication data from the message matrix unit.
Step S350: and if the fact that the communication data sent by the first core is read is detected, the message matrix unit feeds back notification information to the first core.
The first core is in the instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
According to the inter-core communication method, the communication between the cores can be realized by the message matrix unit, and the message matrix unit can feed back the processing condition of the communication data in real time, so that the first core sending the data can know the processing condition of the data sent by the first core in real time. In addition, in this embodiment, the message matrix unit may further arbitrate, by the arbitration module, communication requests initiated by multiple cores and addressed to the same core, so as to avoid communication conflicts.
Referring to fig. 7, a processor 400 according to an embodiment of the present disclosure includes at least a first core 410, a second core 420, and a message matrix unit 430, where the message matrix unit 430 has an interface for communicating with each core.
The first core 410 is configured to execute an information sending instruction to send the communication data and the identification of the second core as a communication target to the message matrix unit.
In the embodiment of the application, each core in the processor is correspondingly provided with an identifier for uniquely identifying the identity of the core. In this way, when the first core serving as the communication data sender executes the information sending instruction, the parameter sent to the message matrix unit carries the identifier of the second core serving as the communication target and the communication data. It can be understood that, after receiving the identifier of the second core that is a communication target, the message matrix unit may determine that the communication target is to send communication data to the second core, and the communication data included in the parameter is data that needs to be sent to the second core.
The first core 410 may be in an instruction blocking state after executing the information sending instruction, where the instruction blocking state indicates that the core may not execute a subsequent information sending instruction, an information reading instruction, or other instructions.
A message matrix unit 430, configured to establish a data path between the first core and the second core in response to the information sending instruction.
And a second core 420 for executing an information reading instruction to read communication data from the message matrix unit.
The message matrix unit 430 is further configured to feed back notification information to the first core 410 if it is detected that the communication data sent by the first core 410 is read.
The first core 410 is in the instruction blocking state until receiving the notification information after sending the communication data to the message matrix unit 430 once, and the second core 420 is in the instruction blocking state until the communication data required to be transmitted to the second core 420 is transmitted to the message matrix unit 430 next time after reading the data to the message matrix unit once.
According to the processor, the communication between the cores can be realized by the message matrix unit, the message matrix unit can feed back the processing condition of the communication data in real time, and the first core sending the data can know the processing condition of the data sent by the first core in real time. In addition, in this embodiment, the message matrix unit may further arbitrate, by the arbitration module, communication requests initiated by multiple cores and addressed to the same core, so as to avoid communication conflicts.
Referring to fig. 8, an inter-core communication apparatus 500 provided in an embodiment of the present application operates in a multi-core processor, where the multi-core processor at least includes a first core, a second core, and a message matrix unit, where the message matrix unit has an interface for communicating with each core, and the apparatus 500 includes:
a sending instruction triggering unit 510, configured to trigger the first core to execute an information sending instruction, so as to send an identifier of the second core serving as a communication target and communication data to the message matrix unit;
a data path management unit 520, configured to trigger the message matrix unit to respond to the message sending instruction to establish a data path between the first core and the second core;
a read instruction triggering unit 530, configured to trigger the second core to execute an information read instruction, so as to read communication data from the message matrix unit;
the information processing unit 540 is configured to trigger the message matrix unit to feed back notification information to the first core if it is detected that the communication data sent by the first core is read;
the first core is in the instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
As one mode, the information sending instruction includes a first information sending instruction and a second information sending instruction, where the first information sending instruction also carries a data volume identifier, and the data volume identifier is used to represent the data volume of the remaining unsent communication data. In this way, the step of the sending instruction triggering unit 510, specifically configured to penalize the first core to execute the information sending instruction, so as to send the identifier of the second core as the communication target and the communication data to the message matrix unit, includes: the first core executes a first information transmission instruction to transmit the identification of the second core as a communication target, communication data, and the data amount identification to the message matrix unit. Correspondingly, in this manner, the information reading instruction includes a first information reading instruction for reading the communication data transmitted based on the first information transmission instruction, and a second information reading instruction for reading the communication data transmitted based on the second information transmission instruction.
In this manner, the sending instruction triggering unit 510 is further configured to trigger the first core to execute at least one second information sending instruction to send the remaining unsent communication data to the message matrix unit. The read instruction triggering unit 530 is further configured to trigger the second core to execute at least one second information reading instruction, so as to read, from the message matrix unit, the communication data sent based on the second information sending instruction.
The data path management unit 520 is further configured to close the data path if the first core completes sending all the communication data to the second core. In this manner, the data path management unit 520 is specifically configured to determine that the first core finishes sending all communication data to the second core when the message matrix unit receives a target message, which is sent by the first core and indicates that data sending is finished.
In one way, the message matrix unit further includes an arbitration module, and each core has one arbitration module. As shown in fig. 9, the data path managing unit 520 includes:
the arbitration module calls the subunit 521, which is used for responding to the information sending instruction by the message matrix unit and calling the arbitration module corresponding to the second core to arbitrate the communication authority of the first core;
a communication establishing subunit 522, configured to establish a data path between the first core and the second core if it is determined that the first core has the communication right. In this way, the arbitration module invokes the subunit 521, specifically to respond to the information sending instruction, and invokes an arbitration module corresponding to the second core to calculate communication permission parameters of a plurality of cores currently requesting to communicate with the second core, so as to obtain permission scores;
and if the authority score of the first core is the highest, judging that the first core has the communication authority.
It should be noted that the device embodiment and the method embodiment in the present application correspond to each other, and specific principles in the device embodiment may refer to the contents in the method embodiment, which is not described herein again.
An electronic device provided by the present application will be described with reference to fig. 10.
Referring to fig. 10, based on the inter-core communication method, another electronic device 200 including a processor 104 capable of performing the inter-core communication method is further provided in the embodiment of the present application. The electronic device 200 also includes a memory 104, and a network module 106. The memory 104 stores programs that can execute the content of the foregoing embodiments, and the processor 102 can execute the programs stored in the memory 104. The internal structure of the processor 102 may be as shown in fig. 1.
Processor 102 may include, among other things, one or more cores for processing data and a message matrix unit. The processor 102 interfaces with various components throughout the electronic device 200 using various interfaces and circuitry to perform various functions of the electronic device 200 and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 104 and invoking data stored in the memory 104. Alternatively, the processor 102 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 102 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 102, but may be implemented by a communication chip.
The Memory 104 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 104 may be used to store instructions, programs, code sets, or instruction sets. The memory 104 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The storage data area may also store data created by the terminal 100 in use, such as a phonebook, audio-video data, chat log data, and the like.
The network module 106 is configured to receive and transmit electromagnetic waves, and implement interconversion between the electromagnetic waves and electrical signals, so as to communicate with a communication network or other devices, for example, an audio playing device. The network module 106 may include various existing circuit elements for performing these functions, such as an antenna, a radio frequency transceiver, a digital signal processor, an encryption/decryption chip, a Subscriber Identity Module (SIM) card, memory, and so forth. The network module 106 may communicate with various networks, such as the internet, an intranet, a wireless network, or with other devices via a wireless network. The wireless network may comprise a cellular telephone network, a wireless local area network, or a metropolitan area network. For example, the network module 106 may interact with a base station.
Referring to fig. 11, based on the inter-core communication method, another electronic device 300 capable of performing the inter-core communication method is provided in the embodiment of the present application.
As shown in fig. 11, the electronic device 300 includes a first processor 310, a second processor 320, and a message matrix unit 330. The first processor 310 includes a first core 311, the second processor 320 includes a second core 321, and the first core 311 and the second core 321 perform information interaction through a message matrix unit 330. For a specific principle process of information interaction between the first core 311 and the second core 321 through the message matrix unit 330, reference may be made to the contents in the foregoing embodiments.
For example, the first core 311 may be configured to execute an information sending instruction to send the communication data and the identification of the second core as the communication target to the message matrix unit 330. A message matrix unit 330, configured to establish a data path between the first core 311 and the second core 321 in response to the information sending instruction. A second core 321, configured to execute an information reading instruction to read communication data from the message matrix unit 330.
If it is detected that the communication data sent by the first core 311 is read, the message matrix unit 330 is further configured to feed back notification information to the first core 311. The first core 311 is in the instruction blocking state until receiving the notification information after sending the communication data to the message matrix unit 330 for one time, and the second core 321 is in the instruction blocking state until the communication data required to be transmitted to the second core 31 is transmitted to the message matrix unit 330 next time after reading the data from the message matrix unit 330 for one time.
It should be noted that the first processor 310 may further include more cores besides the first core 311, and the second processor 320 may further include more cores besides the second core 321. And the cores in the first processor 310 may each perform information interaction with any one of the cores in the second processor 320 through the message matrix unit 330. Further, the electronic apparatus 300 may further include a memory, a network module, and the like, which are not shown in the drawings.
Referring to fig. 12, a block diagram of a computer-readable storage medium according to an embodiment of the present application is shown. The computer-readable medium 1100 has stored therein program code that can be called by a processor to perform the method described in the above-described method embodiments.
The computer-readable storage medium 1100 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 1100 includes a non-volatile computer-readable storage medium. The computer readable storage medium 1100 has storage space for program code 810 to perform any of the method steps of the method described above. The program code can be read from or written to one or more computer program products. The program code 1110 may be compressed, for example, in a suitable form.
To sum up, in the case that the multi-core processor includes at least a first core, a second core, and a message matrix unit, where the message matrix unit has interfaces for communicating with the cores, a first core that needs to send communication data among the cores may execute an information sending instruction to send an identifier of the second core and communication data, which are communication targets, to the message matrix unit. And the message matrix unit responds to the information sending instruction to establish a data path between the first core and the second core. Furthermore, the second core executes an information reading instruction to read the communication data from the message matrix unit, and then the message matrix unit feeds back notification information to the first core if it is detected that the communication data sent by the first core is read. And the first core is in a blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time. Therefore, by the mode, the communication between the cores can be realized by the message matrix unit, the message matrix unit can feed back the processing condition of the communication data in real time, the first core sending the data can know the processing condition of the data sent by the first core in real time, and the communication efficiency between the cores can be improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. An inter-core communication method is applied to an electronic device, the electronic device at least includes a first core, a second core and a message matrix unit, the message matrix unit has interfaces for communicating with each core, and the message matrix unit is used for information interaction between each core, and the method includes:
the first core executes an information sending instruction to send the identification of the second core as a communication target and communication data to the message matrix unit;
the message matrix unit responds to the information sending instruction to establish a data path between the first core and the second core;
the second core executes an information reading instruction to read the communication data from the message matrix unit;
if the fact that the communication data sent by the first core are read is detected, the message matrix unit feeds back notification information to the first core;
the first core is in an instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
2. The method according to claim 1, wherein the information sending instruction includes a first information sending instruction and a second information sending instruction, the first information sending instruction further carries a data volume identifier, the data volume identifier is used for representing a data volume of the remaining unsent communication data, and the second information sending instruction is used for triggering the first core to send the remaining unsent communication data;
the step of the first core executing an information sending instruction to send the identification of the second core as a communication target and communication data to the message matrix unit includes: the first core executes a first information sending instruction to send an identification of a second core as a communication target, communication data and the data volume identification to the message matrix unit;
the information reading instruction comprises a first information reading instruction and a second information reading instruction, the first information reading instruction is used for reading the communication data sent based on the first information sending instruction, and the second information reading instruction is used for reading the communication data sent by the second information sending instruction.
3. The method according to claim 2, wherein if the data volume identifies communication data characterizing the communication data as part, the step of feeding back notification information that the communication data is read to the first core by the message matrix unit further comprises:
the first core executes the second information sending instruction at least once to send the remaining unsent communication data to the message matrix unit;
the second core executes the second information reading instruction at least once to read the communication data transmitted based on the second information transmission instruction from the message matrix unit.
4. The method of claim 1, wherein the electronic device further comprises a third core, wherein the message matrix unit further comprises arbitration modules, and wherein each core corresponds to one of the arbitration modules; the step of the message matrix unit responding to the information sending instruction to establish a data path between the first core and the second core comprises:
if the message matrix unit receives the information sending instruction sent by the first core and the information sending instruction sent by the third core at the same time, and a target core corresponding to the information sending instruction sent by the third core is the second core, invoking an arbitration module corresponding to the second core to arbitrate the communication authority of the first core and the third core;
and if the first core is judged to have the communication authority, establishing a data path between the first core and the second core.
5. The method of claim 4, wherein the step of invoking an arbitration module corresponding to the second core to arbitrate the communication permissions of the first core and the third core comprises:
calling an arbitration module corresponding to the second core to judge the communication priority of the communication of the third core of the first core which currently requests to communicate with the second core;
and if the communication priority of the first core is higher than that of the third core, judging that the first core has the communication authority.
6. The method of claim 4, wherein the step of invoking an arbitration module corresponding to the second core to arbitrate the communication permissions of the first core and the third core comprises:
calling an arbitration module corresponding to the second core to calculate the communication permission parameters of the third core of the first core which currently requests to communicate with the second core, so as to obtain permission scores;
and if the authority score of the first core is the highest, judging that the first core has communication authority.
7. An electronic device is characterized by at least comprising a first processor, a second processor and a message matrix unit, wherein the first processor at least comprises a first core, the second processor at least comprises a second core, the message matrix unit is provided with interfaces for communicating with the cores, and the message matrix unit is used for information interaction among the cores;
the first core is used for executing an information sending instruction so as to send the identification of the second core as a communication target and communication data to the message matrix unit;
the message matrix unit is used for responding to the information sending instruction to establish a data path between the first core and the second core;
the second core is used for executing an information reading instruction to read the communication data from the message matrix unit;
if the fact that the communication data sent by the first core is read is detected, the message matrix unit is further used for feeding back notification information to the first core;
the first core is in an instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
8. The processor is characterized by at least comprising a first core, a second core and a message matrix unit, wherein the message matrix unit is provided with an interface for communicating with each core, and is used for information interaction among the cores;
the first core is used for executing an information sending instruction so as to send the identification of the second core as a communication target and communication data to the message matrix unit;
the message matrix unit is used for responding to the information sending instruction to establish a data path between the first core and the second core;
the second core is used for executing an information reading instruction to read the communication data from the message matrix unit;
if the fact that the communication data sent by the first core is read is detected, the message matrix unit is further used for feeding back notification information to the first core;
the first core is in an instruction blocking state after sending the communication data to the message matrix unit for one time until receiving the notification information, and the second core is in the instruction blocking state after reading the data to the message matrix unit for one time until the communication data required to be transmitted to the second core is transmitted to the message matrix unit next time.
9. An electronic device comprising a processor and a memory;
one or more programs are stored in the memory and configured to be executed by the processor to implement the method of any of claims 1-7.
10. A computer-readable storage medium, having program code stored therein, wherein the program code when executed by a processor performs the method of any of claims 1-7.
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