CN115114042A

CN115114042A - Storage data access method and device, electronic equipment and storage medium

Info

Publication number: CN115114042A
Application number: CN202110308805.2A
Authority: CN
Inventors: 吴臻志; 丁瑞强
Original assignee: Beijing Lynxi Technology Co Ltd
Current assignee: Beijing Lynxi Technology Co Ltd
Priority date: 2021-03-23
Filing date: 2021-03-23
Publication date: 2022-09-27

Abstract

The application discloses a storage data access method, a storage data access device, electronic equipment and a storage medium, and belongs to the technical field of computers. The storage data access method is applied to a first functional core in a many-core system, the many-core system comprises a plurality of functional cores, and the method comprises the following steps: receiving a first write-back request, wherein the first write-back request carries a first target global address of data to be written back; determining a target storage space pointed to by the first target global address; when the target storage space is in an unlocked state, setting the target storage space to be in a locked state until the data to be written back is successfully written back; wherein the target storage space is located in the first functional core, and in the locked state, access requests other than the first writeback request to the target storage space are denied. The method and the device can improve the operating efficiency of the many-core system.

Description

Storage data access method and device, electronic equipment and storage medium

Technical Field

The application belongs to the technical field of computers, and particularly relates to a storage data access method, a storage data access device, electronic equipment and a storage medium.

Background

The many-core system has a plurality of functional cores. In the related art, in the case where a plurality of functional cores in a many-core system need to access the same storage data, there is a problem of data delay, thereby making the operation of the many-core system inefficient.

Disclosure of Invention

An embodiment of the present application aims to provide a storage data access method, an apparatus, an electronic device, and a storage medium, which can solve a problem that a storage data access method in the related art has low operating efficiency of a many-core system due to data delay.

In order to solve the technical problem, the present application is implemented as follows:

in a first aspect, an embodiment of the present application provides a storage data access method, which is applied to a first functional core in a many-core system, and the method includes:

receiving a first write-back request, wherein the first write-back request carries a first target global address of data to be written back;

determining a target storage space pointed to by the first target global address;

when the target storage space is in an unlocked state, setting the target storage space to be in a locked state until the data to be written back is successfully written back;

wherein the target storage space is located in the first functional core, and in the locked state, access requests other than the first writeback request to the target storage space are denied.

In a second aspect, an embodiment of the present application provides a storage data access apparatus, which is applied to a first functional core in a many-core system, and the apparatus includes:

a first receiving module, configured to receive a first write-back request, where the first write-back request carries a first target global address of data to be written back;

a first determining module, configured to determine a target storage space to which the first target global address points;

the setting module is used for setting the target storage space to be in a locked state when the target storage space is in an unlocked state until the data to be written back is successfully written back;

In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program or instructions stored on the memory and executable on the processor, and when executed by the processor, the program or instructions implement the steps of the method according to the first aspect.

In a fourth aspect, embodiments of the present application provide a readable storage medium, on which a program or instructions are stored, which when executed by a processor implement the steps of the method according to the first aspect.

In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement the method according to the first aspect.

In an embodiment of the present application, a first functional core receives a first write-back request, where the first write-back request carries a first target global address of data to be written back; determining a target storage space pointed to by the first target global address; when the target storage space is in an unlocked state, setting the target storage space to be in a locked state until the data to be written back is successfully written back; wherein the target storage space is located in the first functional core, and in the locked state, access requests other than the first writeback request to the target storage space are denied. Therefore, the private storage space in the first functional core can be used as a shared storage space to be accessed by the second functional core and write data in, and different shared data can be dispersedly stored in the private storage spaces of different functional cores, so that the problems of long waiting time and uncertain waiting time when a plurality of functional cores access the global shared storage space respectively due to the fact that a large amount of shared data are stored in the global shared storage space are avoided, and the operating efficiency of the many-core system is improved.

Drawings

FIG. 1 is a flow chart of a method for accessing stored data according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a data interaction of a remote access write-back processing unit to which a method for accessing stored data provided by an embodiment of the present application can be applied;

fig. 3 is a schematic diagram of data interaction between a first functional core and a second functional core in a method for accessing stored data according to an embodiment of the present application;

fig. 4 is a schematic diagram of data interaction in a first functional core in a method for accessing stored data according to an embodiment of the present application;

fig. 5 is a schematic data interaction diagram of a dual-mode memory interface to which a storage data access method according to an embodiment of the present application can be applied;

fig. 6 is a block diagram of a storage data access device according to an embodiment of the present application;

fig. 7 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application are capable of operation in sequences other than those illustrated or described herein, and that the terms "first," "second," etc. are generally used in a generic sense and do not limit the number of terms, e.g., a first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.

The smallest unit with complete computing power that can be independently scheduled in a many-core system is called a functional core (referred to as a "core" for short), each functional core has its own storage computing resource, the same many-core system includes multiple functional cores, and the computation between the functional cores may need to be performed based on shared data. In the related art, the following two ways can be adopted to achieve that multiple functional cores acquire the same shared data:

in the application, when the functional core needs to acquire target data from the global shared storage space, a read request is sent to the global shared storage space through the shared memory bus, and the target data is transmitted through the shared memory bus.

Similarly, when a plurality of functional cores need to update the data in the global shared storage space, a write-back request needs to be sent to the global shared storage space through the shared memory bus, and the data to be updated is transmitted through the shared memory bus.

As can be seen from the above, in an application scenario where multiple functional cores simultaneously access a global shared memory space, it is necessary to determine, through contention arbitration, that one core obtains a use right, so that the core that obtains the use right obtains storage data from the global shared memory space through a shared memory bus, and other cores that do not obtain the use right need to continue waiting. In addition, data needs to be transmitted between the functional core and the global shared storage space through the shared memory bus, and the data delay time is not fixed or even unpredictable, so that the shared memory bus is easily congested, and the operating efficiency of the many-core system is obviously reduced.

In the second mode, the shared data is copied to the private storage space of each functional core that needs to use the shared data, and since the private storage space is only used by the functional core, the external functional core cannot access the private spaces of other functional cores.

As can be seen from the above, in this embodiment, when an algorithm (such as a large neural network) with shared data is executed, the shared data needs to be copied to the private memory of each functional core and updated, which is very wasteful of resources. Under the application scene of large arrays or large shared data, the private memory cannot meet the requirements of storage and operation efficiency, so that the application range of the many-core system is limited.

In order to solve the above technical problem, in the embodiment of the present application, the global address is converted into the corresponding private address, so that the external function core can access the private memory space of the other function core through the global address, and the data write-back is performed on the private memory space, so as to update the data stored in the private memory space. Therefore, on one hand, the shared data can be prevented from being copied to the private memory of each core, so that the resource waste is reduced, and the application range of a many-core system is expanded; on the other hand, a global shared storage space is not additionally arranged outside the functional core, so that the operation efficiency of the many-core system is improved.

The method for accessing stored data, the apparatus for accessing stored data, the electronic device, and the readable storage medium provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Referring to fig. 1, which is a flowchart of a storage data access method provided in an embodiment of the present application, the storage data access method can be applied to a first functional core in a many-core system, and as shown in fig. 1, the storage data access method may include the following steps:

step 101, receiving a first write-back request, wherein the first write-back request carries a first target global address of data to be written back.

And 102, determining a target storage space pointed by the first target global address.

103, when the target storage space is in an unlocked state, setting the target storage space to be in a locked state until the data to be written back is successfully written back; wherein the target storage space is located in the first functional core, and in the locked state, access requests other than the first writeback request to the target storage space are denied.

In the implementation, the functional cores may also be referred to as "cores" or "cores", where the functional cores are minimum units that can be independently scheduled and have complete computing power in the many-core system, each functional core has a respective storage computing resource, and the private storage spaces in each functional core have the same private address, for example: the number of the private storage spaces of the first functional core is N, the number of the N storage space identifiers in the first functional core is 0-N-1, the number of the private storage spaces of the second functional core is N, and the number of the N storage space identifiers in the second functional core is 0-N-1.

The above global address is unique in the many-core system, and can point to a target private storage space in the many-core system, which is located in a target functional core, for example: the global address is a combination of a core identifier of the first functional core and a storage space identifier of a target storage space in the first functional core.

In practical applications, a functional core may include multiple memory spaces, so that the multiple memory spaces in the functional core may be in different states, for example: one part is in a locked state and the other part is in an unlocked state, so that the part of the memory space in the unlocked state can still be accessed.

As an optional implementation manner, the first writeback request includes at least one of:

a writeback request sent by a first data path of the first functional core;

a writeback request sent by the second functional core;

wherein the second functional core is a functional core in the many-core system that is different from the first functional core.

The second functional core may be understood as any functional core in the many-core system except the first functional core, that is, a functional core external to the first functional core, and the number of the second functional cores may be one or more.

The write-back request sent by the first data path of the first functional core may be understood as follows: the first functional core updates data stored in the first functional core with the global address.

It should be noted that, in practical application, the first functional core may also directly perform private access on the data stored in the first functional core by using the private address to update the data stored in the private address in the first functional core, which is not limited herein.

In addition, the writeback request sent by the second functional core may be understood as follows: the external functional core performs global access to the data stored in the first functional core by using the global address to update the data stored in the first functional core at the private address corresponding to the global address.

In an implementation, the same memory space within the first functional core may respond to only one of global access and private access at the same time, for example: the memory space can be switched by mode switching to a first operating mode (which may also be referred to as "global mode") and/or to a second operating mode (which may also be referred to as "private mode") at a target. In the first working mode, converting the global address in the received access request into a private address, so as to access the data in the target storage space based on the private address (namely, in this working mode, only the global access to the target storage space is responded, and the private access can be denied); in the second working mode, the data in the target storage space is accessed based on the private address in the received access request (namely, in the working mode, only the private access to the target storage space is responded, and the response can be refused for the global access).

In addition, the private storage space (i.e., the memory slice) of the first functional core may include one or more private storage spaces, where in the case that there are multiple private storage spaces (i.e., memory slices) of the first functional core, one part of the private storage space may operate in a private mode, and another part of the private storage space may operate in a global mode, where the private storage space in the private mode is only accessible to the first functional core, and the private storage space in the global mode is only accessible to the second functional core.

The setting of the target storage space to the locked state until the data to be written back is successfully written back may specifically be: and setting a target storage space to be in a locked state so as to refuse subsequently received access to the target storage space, starting to write the data to be written back into the target storage space, and when the data to be written back is completely written into the target storage space, releasing the locked state of the target storage space so as to enable the functional core to acquire updated data from the target storage space.

The denial of subsequently received access to the target storage space may be: the access of the external function core except the first function core to the memory area corresponding to the first target global address in the target memory space is rejected; alternatively, denying subsequently received access to the target storage space may also be: during the locking period, the access of the local function core and the external function core except the first function core to the memory area corresponding to the first target global address in the target storage space is stored into the request message queue, and the request in the request message queue is processed after the write-back operation is completed, namely the access request is postponed until the locking state of the target storage space is released and then executed.

As an optional implementation, the method further comprises:

when the target storage space is in a locked state, performing at least one of the following operations:

rejecting the first writeback request;

and adding the first write-back request into a message queue so as to respond to the first write-back request when the target storage space is switched to an unlocked state.

The above-mentioned response to the first writeback request may have the same meaning as that of step 103, and is not described herein again.

In addition, the target storage space is in a locked state, and it can be understood that: there are other data to be written back that are being written into the target storage space, i.e. the data in the target storage space are being updated.

In this embodiment, in the process of updating the data in the target storage space, the first write-back request is rejected or the first write-back request is responded when the target storage space is switched to the unlocked state, so that the problem of data confusion caused by the fact that the target storage space simultaneously responds to the write-back requests or the read requests of a plurality of functional cores can be avoided, and the data reliability of the stored data access method can be improved.

As an optional embodiment, the setting the target storage space to a locked state until the data to be written back is successfully written back includes:

setting the target storage space to be in a locked state, and receiving the data to be written back;

updating the data in the target storage space according to the data to be written back;

after the updating is completed, releasing the locking state of the target storage space.

As an optional implementation manner, the determining a target storage space to which the first target global address points includes:

determining a third private address corresponding to the first target global address according to the mapping relation between the global address and the private address;

and determining a target storage space corresponding to the third private address in the first functional core.

The third private address indicates an initial write address of data to be written back in the private memory of the first functional core, so as to write back the data to be written back from the initial address. In addition, the setting of the target storage space corresponding to the third private address to the locked state may be understood as follows: and setting the memory chip where the third private address is located to be in a locking state.

In this embodiment, after the global address is converted into the private address, the private address is used to access the private memory of the first functional core, so as to update the data in the private memory. After the global address is converted into the private address, the process of accessing the private memory of the first function core by using the private address is the same as the process of accessing the private memory of the first function core by using the local function core in the prior art, and the description is omitted; the difference is that in the embodiment of the present application, the external functional core performs global access to the private memory of the functional core through the global address.

It should be noted that, in practical applications, there may be a plurality of write-back operations, and a resource lock needs to be set for each memory region targeted by each write-back operation, so that the memory region is in a locked state before completing data update. In this case, a lock address space recording area may be provided to record the memory area in a locked state in the lock address space recording area.

For example: the format of one record in the above-mentioned lock address space recording area may be the format shown in table 1 below:

TABLE 1

Initial memory address

Memory length

Requesting core number

Updated quantity

Other information

The memory start address may represent a start write address of data to be written back in the target storage space, the memory length may represent a data length of the data to be written back, the request core number may represent an identifier of a functional core that requests to write the data to be written back into the target storage space of the destination core, the updated number may represent a data length of the data to be written back that has been written into the target storage space, and the other information may be used to add additional information and the like.

In an implementation, the above-mentioned lock address space recording area may be located in the first functional core. In the process that the second functional core writes data into the target storage space pointed by the first target global address, the data to be written back can be sent to the first functional core in a time-sharing manner in the form of a data packet, and after the data in the data packet is successfully written back into the target storage space, the updated number (in byte (byte) units) of the data to be written back in the locked address space recording area is updated. In this way, when the update number is consistent with the data length of the data to be written back, it is determined that the data to be written back has been written back, and at this time, the locked state of the target storage space can be released, and the lock record of the target storage space can be deleted in the lock address space recording area.

It should be noted that the first functional core may further include a memory region that is not in the locked state, and the memory region that is not in the locked state can be accessed by the first functional core or other functional cores.

Further, the updating the data in the target storage space according to the data to be written back includes:

in the process of writing the data to be written back into the target storage space, acquiring the updated data length in the target storage space;

and when the length of the updated data in the target storage space is matched with the storage length of the data to be written back, determining that the updating is completed.

In an implementation, the first target global address may indicate an initial write address of the data to be written back, or after the first target global address is converted into the corresponding first private address, the initial write address of the data to be written back in the target storage space is represented by the first private address. At this time, the terminating address of the data to be written back may be obtained by calculating according to the data length of the data to be written back and the first private address, and the writing address of the data being written in the target storage space is obtained in real time, in this embodiment, the data length of the data to be updated in the target storage space matches the storage length of the data to be written back, which may be understood as: when the write address is consistent with the termination address of the data to be written back, it may be determined that the data to be written back completes the write back, that is, it is determined that the update is completed.

Of course, in actual use, the data amount of the data already written in the target storage space may also be obtained in real time through a counter, and in this embodiment, the length of the data that is updated in the target storage space matches the storage length of the data to be written back, which may be understood as: when the data volume of the data already written is the same as the data volume of the data to be written back, it may be determined that the data to be written back completes the write back, that is, it is determined that the updating is completed.

In this embodiment, whether the update is completed or not can be determined by comparing whether the length of the data whose update is completed in the target storage space is matched with the storage length of the data to be written back, so that the locked state of the target storage space can be released as soon as possible when the update is completed.

As an optional implementation manner, the first writeback request is an access request initiated by a second functional core in the many-core system, and the method further includes:

and sending a notification signaling to the second functional core, wherein the notification signaling is used for notifying the second functional core that the data to be written back is written back successfully.

In practical application, when the second functional core does not receive the notification signaling, the second functional core may retransmit the write-back request, and avoid that the second functional core mistakenly thinks that the write-back of the data to be written back is completed under the condition that the write-back of the data to be written back is not completed in time due to write-back failure, excessively long write-back time delay, refused write-back request, and the like, so as to improve the reliability of the stored data access method.

The following takes a remote access write-back processing unit, to which the storage data access method provided in the embodiment of the present application can be applied, as an example, to exemplify the storage data access method provided in the embodiment of the present application:

as shown in fig. 2, the first functional core includes: a routing module 21, a signaling buffer 22, a packet buffer 23, a remote access write-back processing unit 24, and a memory area 25, wherein the remote access write-back processing unit 24 includes: a lock address space entry 241 and control logic 242.

Specifically, the remote access write-back processing unit 24 is connected to the routing module 21 through the signaling buffer 22 and the packet buffer 23, respectively, the routing module 21 is configured to establish a communication connection with other functional cores through a network on chip, the DMA in the remote access write-back processing unit 24 is connected to the memory area 25, and the control logic 242 in the remote access write-back processing unit 24 is connected to the lock address space recording area 241 and the memory area 25, respectively.

In a specific implementation, the control logic 242 is configured to control operations such as querying, updating, adding, deleting, and the like of the lock records in the lock address space record area 241, and when the control logic 242 receives a global access request from an external functional core, it is able to analyze and obtain a destination address of the global access request, query whether a memory space corresponding to the destination address is in a lock state from the lock address space record area 241, and if the memory space is in the lock state, reject the global access request.

In implementation, the routing module 21 receives write-back request signaling sent by an external functional core through the network on chip, the write-back request signaling is transmitted to the control logic 242 through the signaling buffer, the control logic 242 converts the global address carried in the write-back request signaling into a private address, and according to the information carried in the write-back request signaling and the use condition of the storage space corresponding to the private address, etc., judging whether to overrule the write-back request signaling, if it is judged that the write-back request signaling is not overruled, the global address carried in the write-back request signaling may be converted into a private address, and the memory space corresponding to the private address in the memory area 25 is set to be in a locked state, the data packets received from the network on chip via the routing module 21 and the packet buffer 23 are then allowed to be written into the memory space of the memory area 25 corresponding to the private address.

It should be noted that in implementation, a Memory Access (DMA) subunit may be disposed between the packet buffer 23 and the Memory area 25, and the DMA subunit is controlled by the control logic 242 to control the DMA subunit to be in a normal operating state when the control logic 242 determines, based on the locked address space recording area 241, that the storage space of the data to be accessed is in an unlocked state, that is, the functional core is allowed to Access the storage space located in the Memory area 25 and in the unlocked state; in addition, when the control logic 242 determines that the storage space of the data to be written back is in the locked state based on the locked address space recording area 241, the DMA subunit is controlled to be in the access prohibited work state, that is, the functional core is denied access to the storage space located in the memory area 25 and in the locked state.

It should be noted that the arrow direction in the embodiment shown in fig. 2 indicates a transmission direction of signaling or data to be written back in the process that the requesting functional core requests to write data to be written back into the first functional core.

As an optional implementation, before the receiving the first writeback request, the method further comprises:

receiving a first read request, wherein the first read request carries a second target global address;

when it is determined that the target storage space indicated by the second target global address is located in the first function core and the target storage space is not in a locked state, a first private address corresponding to the second target global address is determined according to a mapping relation between the global address and the private address, and first target data corresponding to the first private address in the target storage space is transmitted.

In application, any functional core in the many-core system can acquire data from the private memory (including the target storage space) of the first functional core based on the conversion between the global address and the private address, and perform calculation according to the data to obtain a calculation result, and then update the data in the private memory of the first functional core according to the calculation result.

In other words, in this embodiment, any functional core in the many-core system can read and update data stored in the private memory of the first functional core based on the conversion between the global address and the private address, and can reject other access requests for accessing the private memory when the private memory of the first functional core is in the locked state, so as to avoid transmitting data before updating or not completing updating in the process of updating the data in the private memory of the first functional core, thereby improving data reliability.

In the embodiment of the application, in the process of updating the data in the private memory of the first functional core, the private memory of the first functional core is set to be in a locked state, so that the problem that the data in the many-core system is not uniform due to the fact that part of functional cores acquire the data before updating or incompletely updated from the private memory in the process of updating the data in the private memory is avoided.

As an optional implementation manner, the first read request, the first target data, the first write-back request, and the data to be written back are transmitted through a network on chip or a bus on chip, and any two functional cores in the many-core system are connected through the network on chip or the bus on chip.

For example: as shown in fig. 3, a request core 31 (i.e., a second functional core) and a destination core 32 (i.e., a first functional core) establish a communication connection through an on-chip/inter-chip network 33, where the request core 31 specifically includes: the first private memory 311, the first dual mode memory interface 312, the first route 313 and the data path 314, and the destination core 32 specifically includes: a second private memory 321, a second dual mode memory interface 322, and a second route 323. When the requesting core 31 needs to read the target data stored in the private memory 324 of the destination core 32, the data path 314 in the requesting core 31 sends a read request to the on-chip/inter-chip network 33 through the second dual-mode memory interface 322 and the first route 313, where the read request carries the core identifier of the requesting core 31 and the global address of the requested read data, the destination core 32 receives the read request from the on-chip/inter-chip network 33 through the second route 323, and when the second dual-mode memory interface 322 recognizes that the core identifier in the read request is not consistent with the core identifier of the destination core 32, the global address in the read request is converted into a private address, and the destination data stored in the private address in the second private memory 321 is transmitted to the on-chip/inter-chip network 33 through the second route 323, so that the requesting core 31 obtains the target data from the on-chip/inter-chip network 33 through the first route 313, thereby, the request core 31 obtains the target data from the private memory of the destination core 32.

It should be noted that, as shown in the embodiment shown in fig. 3, the arrow direction indicates the transmission direction of the signaling or the target data in the process that the requesting core 31 acquires the target data from the private memory 324 of the destination core 32.

In this embodiment, the request signaling and the data packet between the first functional cores are transmitted through the network on chip or the bus on chip, so that the waiting time can be reduced when a plurality of second functional cores access the private memory of the first functional core at the same time.

Of course, in a specific implementation, any two functional cores in the many-core system may also be connected through other networks, for example: a short-range communication network, etc., and is not particularly limited herein.

In addition, in an optional implementation manner, in a case that the number of the second functional cores is multiple, that is, multiple external functional cores respectively access the private storage space of the first functional core, the first functional core may further respond to the read requests of the multiple second functional cores one by one.

In addition, the mapping relationship between the global address and the private address may be: and in operation, the private address corresponding to the global address is inquired in the mapping table. Of course, it may also be a method of pre-storing the conversion relationship between the private address and the global address, so as to dynamically convert the global address into the corresponding private address in the running process.

Of course, the mapping relationship between the global address and the private address may further include: and determining a mapping relation according to the conversion relation between the global address and the private address.

As an optional embodiment, the mapping relationship between the global address and the private address is determined by:

under the condition that the many-core system comprises S chips, determining the mapping relation according to the global address corresponding to each private address based on the target function core where each global address indicates the corresponding private address and the target chip where the target function core is located;

alternatively, the first and second liquid crystal display panels may be,

and under the condition that the many-core system comprises 1 chip and the chips comprise a functional core array arranged in J rows and P columns, determining the mapping relation according to the global address corresponding to each private address based on the target functional core where each global address refers to the corresponding private address and the position of the target functional core in the whole column of the functional core.

In an optional implementation manner, the determining, based on the global address corresponding to each private address, the mapping relationship according to the global address corresponding to each private address by using the target function core where the corresponding private address is indicated and the target chip where the target function core is located may be understood as: the mapping relation comprises a conversion relation between the global address and the private address, and the conversion relation is realized by the target function core where the private address is located and the target chip where the target function core is located, wherein the target function core corresponds to the global address. In other words, it can also be understood as: the global address carries a corresponding private address, an identifier of a functional core where the private address is located, and an identifier of a chip where the functional core is located.

For example: under the condition that the many-core system comprises S chips, the mapping relation between the global address and the private address is determined by adopting the following formula:

p＝(qV+c)×N+k

wherein p represents a global address, k represents a private address, c represents an identifier of a functional core corresponding to k, q represents an identifier of a chip on which the functional core corresponding to c is located, N represents a total number of the private addresses in the functional core corresponding to k, and V represents a total number of the functional cores in each chip.

Of course, in the specific implementation, in addition to expressing the mapping relationship between the global address and the private address through the above formula, the mapping relationship between the global address and the private address may also be expressed in a manner of jointly composing the global address by combining and arranging the private address, the chip identifier, and the functional core identifier.

In another optional implementation manner, the determining the mapping relationship according to the global address corresponding to each private address based on the target function core where each global address refers to the corresponding private address and the position of the target function core in the whole column of the function core may be understood as: the global address carries the identification of the corresponding private address and the functional core where the private address is located, and the arrangement position of the functional core in the functional core array.

For example: in the case where the many-core system includes 1 chip and the chips include a functional core array arranged in J rows and P columns, the mapping relationship between the global address and the private address is determined using the following formula:

p＝(Px+y)×N+k

wherein p represents a global address, k represents a private address, x represents a row identifier of the functional core corresponding to k in the functional core array, y represents a column identifier of the functional core corresponding to k in the functional core array, and N represents a total number of private addresses in the functional core corresponding to k.

Of course, in the specific implementation, in addition to expressing the mapping relationship between the global address and the private address through the above formula, the mapping relationship between the global address and the private address may also be expressed in a manner of jointly composing the global address by combining and arranging the private address and the chip location.

In this embodiment, the preset address and the global address are associated through the chip identifier, the function core position, and the like, so that the global address and the private address can be mutually converted in the application according to the chip identifier, the function core position, and the like, and the process of determining the first private address corresponding to the second target global address is simplified.

As an optional implementation, the method further comprises:

receiving a second read request sent by a first data path, wherein the first data path is located in the first functional core, the second read request carries a second private address, and the second private address is located in the target storage space;

and when the target storage space is determined not to be in the locked state, transmitting second target data corresponding to the second private address in the target storage space to the first data path.

This embodiment is applied to: the first functional core reads an application scenario of data from the local private memory, and at this time, as long as a target storage space indicated by the second private address is not in a locked state, the first functional core may directly send the private address to the local private memory to access the private memory, and does not need to send a global address corresponding to the private address.

For example: as shown in fig. 4, the computing module in the first functional core 41 may send a read request to the private memory 413 of the first functional core through the dual-mode memory interface 412 through the data path 411, where the read request carries a private address of target data, so that the private memory 413 feeds back the target data stored in the private address to the computing module through the dual-mode memory interface 412 and the core data path 411.

It should be noted that, as shown in the embodiment shown in fig. 4, the arrow direction indicates the transmission direction of the signaling or the target data in the process that the first functional core 41 acquires the target data from the private memory 413 of the functional core.

It should be noted that, in this embodiment, the first data path in the first functional core sends the second read request carrying the private address to the target storage space of the first functional core, so that an implementation process of reading data from the target storage space is the same as a process of reading data from the local private memory by the functional core in the prior art, and is not described in detail herein.

It should be noted that, in practical applications, the first functional core may include a plurality of memory chips, so that there may be a case where a part of the memory chips in the first functional core is accessed by the functional core, and another part of the memory chips is accessed by the external functional core. However, the same memory slice can only respond to one of the local access request and the global access request (i.e., the first read request) at the same time.

As an optional implementation manner, the operation modes of the target storage space include a first operation mode and a second operation mode;

in the first working mode, rejecting a second read request to the target storage space until the first read request completes a response; in the second working mode, rejecting the first reading request to the target storage space until the second reading request completes the response;

the method further comprises at least one of:

determining a working mode of the target storage space according to a control instruction;

determining the operating mode to be the first operating mode in response to the first read request;

determining the operating mode to be the second operating mode in response to the second read request.

In an embodiment, the determining the operation mode of the target storage space according to the control command may be understood as: the working mode of the target storage space is determined according to the indication of the preset control instruction and is not influenced by the received access request.

In this embodiment, the working mode of the target storage space may be adjusted by a preset control instruction, so as to control whether data in the target storage space can be accessed only by the functional core or by other functional cores.

Situation one

In the case that the memory of the functional core operates in the global mode (i.e., the first operating mode), the memory can only be globally accessed by the external functional core, and the access of the functional core will be denied. In the global mode, a received read request carries a global address, the global address is recorded by a global address mapping table and is responsible for translating the global address to a private address, and finally the private address is adopted to access the memory.

It should be noted that, in the global mode, the memories of all the functional cores form a large-capacity logical memory, and when performing global access, it is not necessary to indicate which core of which chip the accessed memory is located in, and only a global address is needed to access the memory.

Situation two

In the case that the memory of the functional core operates in the private mode (i.e., the second operating mode), the memory can be accessed only locally by the functional core, and the global access of the external functional core is denied. In the private mode, the memory can only be accessed by the functional core, and therefore, the access delay is fixed and predictable.

In another embodiment, the operating mode is determined to be the first operating mode in response to the first read request; in response to the second read request, determining the operating mode as the second operating mode may be understood as: whether to operate in the first operating mode or the second operating mode is determined based on whether the received access request is a private request or a global request.

Specifically, rejecting the second read request to the target storage space until the first read request completes the response may be understood as: in the first working mode, only the global access of the target storage space is responded, and after all the global access responses are completed, the second working mode can be switched to, so that in the second working mode, the private access of the target storage space is responded; or, after all the global access responses are completed, the private access of the target storage space can be responded directly without mode switching.

Accordingly, the foregoing rejecting the first read request to the target storage space until the second read request completes the response may also be understood as: in the second working mode, only the private access of the target storage space is responded, and after all the private access responses are completed, the first working mode can be switched to, so that the global access of the target storage space is responded in the first working mode; or, after all the private access responses are completed, the global access of the target storage space can be responded directly without mode switching.

In this embodiment, the working mode of the target storage space may be determined according to the type of the received read request, so that the working mode of the target storage space is switched according to different read requests, so that the target storage space matches the received read request.

For example:

after the receiving of the first read request carrying the global address, the method further includes:

in response to the first read request, setting the target storage space to be in a first working mode, wherein in the first working mode, the target storage space rejects the access request of the first functional core until the second read request completes a response;

after the receiving a second read request carrying a private address, the method further comprises:

and in response to the second read request, setting the target storage space to be in a second working mode, wherein in the second working mode, the target storage space rejects the access request of an external function core until the second read request completes the response.

It should be noted that, if the target storage space receives both the local access request carrying the private address and the global access request carrying the global address at the same time, it may also select to respond to one of the local access request core global access requests by arbitration.

In other words, if other functional cores in the many-core system except the first functional core need to acquire or write data to the private memory of the first functional core, the conditions that need to be satisfied include: the read request or the write-back request sent by other functional cores carries a global address indicating a to-be-accessed storage space, the to-be-accessed storage space in the first functional core is in the first working mode, and the to-be-accessed storage space is in an unlocked state, and the to-be-accessed storage space represents a storage space in which to-be-acquired data or to-be-updated data is stored.

When the first functional core needs to obtain or write data into the private memory of the functional core, the conditions that need to be satisfied include: the storage space to be accessed is in an unlocked state, and the storage space to be accessed represents a storage space for storing data to be acquired or updated; in addition, in the first working mode, the read request or the write-back request sent by the first functional core carries a global address indicating a storage space to be accessed, or, in the second working mode, the read request or the write-back request sent by the first functional core carries a private address indicating the storage space to be accessed.

As an alternative embodiment, in the case that the receiving time difference between the first read request and the second read request is smaller than the preset time, responding to at least one of the first read request and the second read request is determined by arbitration or preset priority.

The preset time may be any time length such as 0.1s (second) and 1 second, and is not particularly limited herein.

The determining to respond to at least one of the first read request and the second read request according to the preset time may be: under the condition that the priority of the first read request is set to be higher than that of the second read request in advance, the first read request is responded preferentially, the second read request can be rejected, or the second read request is responded after the first read request is responded; and under the condition that the priority of the second read request is set to be higher than that of the first read request in advance, the second read request is responded preferentially, the first read request can be rejected, or the first read request is responded after the second read request is responded.

The following takes the example that the target storage space includes a dual-mode memory interface for switching the target storage space between a private mode and a global mode, and exemplifies the response process of the local access request and the global access request:

in this embodiment, the many-core system includes: a first functional core, a second functional core, and a network on chip 50 connecting the first functional core and the second functional core.

As shown in fig. 5, the first functional core includes: a data path 51, a memory 52, a routing module 53 and a dual-mode memory interface 54, wherein the routing module 53 is connected with the network-on-chip 50; the dual mode memory interface 54 comprises a target location parser 541, a mode switch 542, an address mapping table storage module 543, a request signaling packer 544, a request signaling unpacker 545, a data packer 546 and a data unpacker 547.

Specifically, the target location parser 541 is connected to the data path 51, the memory 52 mode switch 542, the address mapping table storage module 543, the request signaling packetizer 544, the request signaling depacketizer 545, the data packetizer 546 and the data depacketizer 547, and the mode switch 542, the address mapping table storage module 543, the request signaling packetizer 544, the request signaling depacketizer 545, the data packetizer 546 and the data depacketizer 547 are connected to the routing module 53.

It should be noted that the structure of the second functional core may be the same as that of the first functional core, and is not described herein again. In addition, the arrow direction in the embodiment shown in fig. 5 represents the transmission direction of the signaling or target data in the process that the memory 52 of the first functional core is accessed locally or globally.

In one case, if the dual-mode memory interface 54 is in the private mode, the destination location resolver 541 directly accesses the memory 52 according to the private address provided by the data generating unit in the data path 51, that is, the private address carrying the destination data in the second read request, and the memory 52 directly outputs the returned data packet of the destination data to the data path 51.

In another case, if the dual-mode memory interface 54 is in the global mode, when the data path 51 sends a read request to the target location resolver 541, the target location resolver 541 is configured to determine, according to the address mapping table stored in the address mapping table storage module 543, whether a destination address in the read request sent by the data path 51 is located in the local function core or in another function core located outside, so as to determine whether the read request needs to be generated as a local access request or a global access request.

If the destination address in the read request is located in the local functional core, it is determined that the read request is a local access request, and the memory 52 is directly accessed according to the private address in the local access request.

In addition, if the destination address in the read request is located in another external functional core, it is determined that the read request is a global access request, at this time, the target location parser 541 sends the request location in the global access request to the request signaling packetizer 544, the request signaling packetizer 544 packetizes a global access request signaling packet, and sends the global access request signaling packet to the routing module 53, and the routing module 53 sends the global access request signaling packet received from the request signaling packetizer 544 to the network-on-chip 50 to send the global access request signaling packet to a storage location of data to be read through the network-on-chip 50, so that when the target functional core where the storage location is located returns a data packet in response to the global access request signaling packet, the routing module 53 receives the return data packet from the network-on-chip 50 and unpacks the data packet by the data unpacker 547, to obtain target data (i.e. data that needs to be read by the functional core), the target location parser 541 further parses the target data, and sends the target data to the memory 52 or the data path 51 according to the parsed information.

Meanwhile, the routing module 53 is also responsible for receiving a global access request signaling packet sent from the external functional core to the local functional core from the network on chip 50, and unpacking the global access request signaling packet by the request signaling unpacker 545 to obtain information such as a global address and a data length of the global access request signaling packet. And transmits the information to the target location parser 541. Thus, the destination location parser 541 will translate the global address of the global access request into a private address to access the memory 52 via the private address, and return the access result (i.e. destination data) of the memory 52 to the data packer 546, so as to send the destination data to the network on chip 50 via the routing module 53 after the data packer 546 has formed a data packet, at this time, the requester of the destination data will receive the data packet of the destination data from the network on chip 50, specifically, in the requester of the destination data, the data packet received by the routing module will be unpacked in the data unpacker, and the relevant data packet will be sent to the destination location parser, the destination location parser will parse the data packet information to send the data in the data packet to the memory or data path according to the parsed information, the processing procedure of the requester of the destination data to the received destination data is the same as the processing procedure of the function core after receiving the data packet, and will not be described in detail herein.

In implementation, the format of the request signaling packet may be as shown in table 2 below:

TABLE 2

Wherein the signaling identifier is used to distinguish between different signaling; the target function core address is used for indicating the address of the function core where the memory storing the data to be accessed is located; the data starting global address represents a starting global address of the data to be accessed, and the starting global address plus the data length can represent an ending global address of the data to be accessed; under the condition that a plurality of functional cores access the storage space where the data to be accessed are located at the same time, the target position resolver can perform arbitration based on the priority to determine to respond to an access request signaling with the highest priority; additional information may be added through the additional information field described above.

It should be noted that the arrangement positions of the sub signals in the request signaling packet may be exchanged, and may further include other sub information besides the signaling identifier, the target function core address, the data starting global address, the priority, and the additional information field, which is not exhaustive here.

In addition, in implementation, the format of the data packet may be as shown in table 3 below:

TABLE 3

Wherein, the data packet identifier is used for distinguishing different data packets; the data body represents specific data (namely data to be accessed) in the data packet; in addition, the specific meanings of the target function core address, the data starting global address, the data length, and the additional information field may refer to the specific meanings of the target function core address, the data starting global address, the data length, and the additional information field in the request signaling packet format shown in table 2, respectively, and are not described herein again.

In the related art, when a set of weights is used for a plurality of pictures, the plurality of pictures are respectively input to a plurality of functional cores for respective processing, and in application, since the set of weights needs to be used for the plurality of functional cores and the private memory of each functional core can only be accessed by the functional core, all the functional cores which need to use the set of weights exist in the set of weights, so that pictures can be processed layer by layer.

In the embodiment of the present application, the set of weights may be stored in only 1 or a few functional cores (for example, only each weight value in the set of weights is respectively stored in a functional core that needs to use the weight value, and the functional core does not need to store the whole set of weights), and when one functional core needs to use an unstored weight value, the functional core may obtain the weight value from other functional cores that store the weight value in a global access manner.

As can be seen from the above, by the stored data access method provided in the embodiment of the present application, when an algorithm (such as a large neural network) with shared data is executed, the shared data does not need to be copied to the private memory of each functional core, so that resource waste can be reduced, the application range of a many-core system with a large array and shared data is wider, and a high-speed mode and a sparse mode can be simultaneously supported. In addition, different from the prior art that shared data needs to be transmitted through a shared memory central line, in the embodiment of the application, signaling and data of global access are transmitted through an on-chip network, an on-chip bus or an inter-chip network, so that the waiting time of signaling and data transmission can be reduced, and the operating efficiency of a many-core system can be improved.

In the embodiment of the present application, a first functional core receives and receives a first write-back request sent by a second functional core, where the first write-back request carries a first target global address of data to be written back; and in response to the first write-back request, setting a target storage space pointed by the first target global address to a locked state until the data to be written back is successfully written back, wherein the target storage space is located in the first functional core, in the locked state, the target storage space denies access to functional cores except the second functional core, and in an unlocked state, the target storage space can be accessed by any functional core in the many-core system. Therefore, the private storage space in the first functional core can be used as a shared storage space to be accessed by the second functional core and write data in, and different shared data can be dispersedly stored in the private storage spaces of different functional cores, so that the problems of long waiting time and uncertain waiting time when a plurality of functional cores access the global shared storage space respectively due to the fact that a large amount of shared data are stored in the global shared storage space are avoided, and the operating efficiency of the many-core system is improved.

It should be noted that, in the stored data access method provided in the embodiment of the present application, the execution subject may be a stored data access device, or a control module in the stored data access device for executing the stored data access method. In the embodiment of the present application, a method for executing load and store data access by a store data access device is taken as an example, and the store data access device provided in the embodiment of the present application is described.

Referring to fig. 6, which is a block diagram of a storage data access apparatus 600 according to an embodiment of the present application, where the storage data access apparatus 600 is applied to a first functional core in a many-core system, as shown in fig. 6, the storage data access apparatus 600 includes:

a first receiving module 601, configured to receive a first write-back request, where the first write-back request carries a first target global address of data to be written back;

a first determining module 602, configured to determine a target storage space pointed to by the first target global address;

a setting module 603, configured to set the target storage space to a locked state when the target storage space is in an unlocked state until the data to be written back is successfully written back; wherein the target storage space is located in the first functional core, and in the locked state, access requests other than the first writeback request to the target storage space are denied.

Optionally, the storage data access apparatus 600 further includes:

a second receiving module, configured to receive a first read request, where the first read request carries a second target global address;

and the first transmission module is used for determining a first private address corresponding to the second target global address according to the mapping relation between the global address and the private address when the target storage space indicated by the second target global address is determined to be located in the first functional core and the target storage space is not in the locked state, and transmitting first target data corresponding to the first private address in the target storage space.

Optionally, the first read request, the first target data, the first write-back request, and the data to be written back are transmitted through an on-chip network or an on-chip bus, and any two functional cores in the many-core system are connected through the on-chip network or the on-chip bus.

Optionally, the storage data access apparatus 600 further includes:

a third receiving module, configured to receive a second read request sent by a first data path, where the first data path is located in the first functional core, and the second read request carries a second private address;

and the second transmission module is used for transmitting second target data corresponding to the second private address in the target storage space to the first data path when the target storage space is determined not to be in the locked state.

Optionally, the setting module 603 includes:

the locking unit is used for setting the target storage space to be in a locking state and receiving the data to be written back;

the updating unit is used for updating the data in the target storage space according to the data to be written back;

and the unlocking unit is used for releasing the locking state of the target storage space after the updating is finished.

Further, the first write-back request also carries a storage length of the data to be written back, and the update unit includes:

the writing subunit is configured to, in a process of writing the data to be written back into the target storage space, obtain a data length in the target storage space, where updating is completed;

and the determining subunit is used for determining that the updating is completed when the length of the updated data in the target storage space is matched with the storage length of the data to be written back.

Optionally, the first determining module 602 includes:

the first determining unit is used for determining a third private address corresponding to the first target global address according to the mapping relation between the global address and the private address;

a second determining unit, configured to determine a target storage space corresponding to the third private address in the first functional core.

Optionally, the first write-back request is an access request initiated by a second functional core in the many-core system, and the apparatus 600 for accessing stored data further includes:

and a sending module, configured to send a notification signaling to the second functional core, where the notification signaling is used to notify the second functional core that the data to be written back is written back successfully.

Optionally, the storage data access apparatus 600 further includes:

an execution module, configured to, when the target storage space is in a locked state, perform at least one of the following operations:

rejecting the first writeback request;

Optionally, the first write-back request includes at least one of:

a writeback request sent by a first data path of the first functional core;

a writeback request sent by the second functional core;

Optionally, the mapping relationship between the global address and the private address is determined by the following method:

alternatively, the first and second electrodes may be,

Optionally, the working modes of the target storage space include a first working mode and a second working mode;

storage data access apparatus 600 further comprises at least one of:

the second determining module is used for determining the working mode of the target storage space according to the control instruction;

a third determining module, configured to determine, in response to the first read request, that the operating mode is the first operating mode;

a fourth determining module, configured to determine, in response to the second read request, that the operating mode is the second operating mode.

Optionally, in a case that a difference between receiving times of the first read request and the second read request is smaller than a preset time, responding to at least one of the first read request and the second read request is determined by arbitration or preset priority.

The storage data access device 600 provided in this embodiment of the application can execute each process executed by the first functional core in the method embodiment shown in fig. 1, and can improve the operating efficiency of the many-core system and save storage resources, which has the same beneficial effects as the method embodiment shown in fig. 1, and is not described here again to avoid repetition.

The storage data access device in the embodiment of the present application may be a device, and may also be a component, an integrated circuit, or a chip in a terminal. The device can be mobile electronic equipment or non-mobile electronic equipment. For example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a Personal Computer (PC), a teller machine, a self-service machine, and the like, and the embodiment of the present application is not particularly limited.

The storage data access device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present application are not limited specifically.

The stored data access device provided in the embodiment of the present application can implement each process implemented by the method embodiment shown in fig. 1, and is not described here again to avoid repetition.

Optionally, as shown in fig. 7, an electronic device 700 is further provided in this embodiment of the present application, and includes a processor 701, a memory 702, and a program or an instruction stored in the memory 702 and executable on the processor 701, where the program or the instruction is executed by the processor 701 to implement each process of the above-mentioned stored data access method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and the non-mobile electronic devices described above.

The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the program or the instruction implements each process of the foregoing storage data access method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and so on.

The embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to execute a program or an instruction to implement each process of the foregoing stored data access method embodiment, and can achieve the same technical effect, and in order to avoid repetition, the description is omitted here.

It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as system-on-chip, system-on-chip or system-on-chip, etc.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element identified by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A storage data access method is applied to a first functional core in a many-core system, and is characterized by comprising the following steps:

wherein the target storage space is located within the first functional core, and in the locked state, access requests other than the first writeback request to the target storage space are denied.

2. The method of stored data access according to claim 1, wherein prior to said receiving a first writeback request, said method further comprises:

when it is determined that the target storage space indicated by the second target global address is located in the first functional core and the target storage space is not in a locked state, a first private address corresponding to the second target global address is determined according to a mapping relation between the global address and the private address, and first target data corresponding to the first private address in the target storage space is transmitted.

3. The method of accessing stored data according to claim 2, wherein the method further comprises:

receiving a second read request sent by a first data path, wherein the first data path is located in the first functional core, and the second read request carries a second private address;

4. The method of claim 1, wherein setting the target storage space to a locked state until the data to be written back is successfully written back comprises:

5. The method of claim 4, wherein the first write-back request carries a storage length of the data to be written back, and the updating the data in the target storage space according to the data to be written back comprises:

6. The storage data access method according to claim 2 or 5, wherein the mapping relationship between the global address and the private address is determined by:

alternatively, the first and second electrodes may be,

7. The storage data access method of claim 3, wherein the operating modes of the target storage space include a first operating mode and a second operating mode;

in the first working mode, rejecting a second read request to the target storage space until the first read request completes a response; in the second working mode, rejecting the first read request to the target storage space until the second read request completes the response;

the method further comprises at least one of:

in response to the first read request, determining that the operating mode is the first operating mode;

8. A storage data access apparatus for use in a first functional core of a many-core system, the apparatus comprising:

the system comprises a first receiving module, a first write-back module and a second receiving module, wherein the first write-back module is used for receiving a first write-back request, and the first write-back request carries a first target global address of data to be written back;

9. An electronic device comprising a processor, a memory, and a program or instructions stored on the memory and executable on the processor, the program or instructions when executed by the processor implementing the steps of the stored data access method of any of claims 1-7.

10. A readable storage medium, on which a program or instructions are stored, which program or instructions, when executed by a processor, carry out the steps of the storage data access method according to any one of claims 1-7.