CN110597335B

CN110597335B - Current trap circuit with controllable output voltage

Info

Publication number: CN110597335B
Application number: CN201910747716.0A
Authority: CN
Inventors: 不公告发明人
Original assignee: Zhuhai Eeasy Electronic Tech Co ltd
Current assignee: Zhuhai Eeasy Electronic Tech Co ltd
Priority date: 2019-08-14
Filing date: 2019-08-14
Publication date: 2020-11-03
Anticipated expiration: 2039-08-14
Also published as: CN110597335A

Abstract

The application provides a controllable current sink circuit of output voltage includes: the bias module comprises at least two first output ends and at least one first input end; the feedback module comprises at least two second output ends and second input ends with the number equal to that of the first output ends; and the source electrode of the N-channel MOS tube is grounded. Wherein the first output of the bias module is coupled to the corresponding second input of the feedback module. The first input terminal of the bias module serves as the input terminal of the novel current sink circuit. One of the second output ends of the feedback module is interconnected with the drain electrode of the first N-channel MOS tube and serves as the output end of the novel current trap circuit. And the other one of the second output ends of the feedback module is interconnected with the grid electrode of the first N-channel MOS tube so as to ensure that the voltage of the input end of the novel current trap circuit is equal to the voltage of the output end.

Description

Current trap circuit with controllable output voltage

Technical Field

The invention relates to the technical field of signal processing and transmission in microelectronic technology, in particular to a novel current trap circuit with controllable output, which has flexible and wide application in various high-speed interfaces, especially application occasions needing the characteristic.

Background

With the continuous development of integrated circuit technology and process level, the smaller the sizes of transistors and devices on a chip are, the higher the integration level of the chip is, and the higher the high-speed interface speed is. This makes circuit design of integrated circuits very difficult. Especially, the redundancy of the area of the chip is continuously increased due to the massive multiplexing of the analog circuits, so that some simple structures are required to realize the multiplexing of the modules as much as possible so as to reduce the area of the chip.

The current sink circuit plays a crucial role in generating low-speed logic signals, and can generate a voltage meeting the swing requirement by using a structure similar to an LDO. If a large number of channels require more current sinks, the overall structure needs to be multiplexed, resulting in a larger circuit area. If a circuit with high-speed response is needed, a large-bandwidth operational amplifier is often needed, so that a large amount of power consumption is wasted on the operational amplifier, and the chip area and the power consumption are increased. Therefore, designing a current sink circuit with more flexibility and wider application is significant for saving power consumption and area in certain specific application occasions, especially in the occasion of multi-channel communication.

Disclosure of Invention

The utility model aims at solving the not enough of prior art, provide a controllable novel current trap circuit structure of output voltage, this circuit structure adopts simple feedback loop can realize the high bandwidth, thereby can reach the multiplexing area that reduces of biasing module simultaneously, and this technique makes this circuit have more nimble more extensive application under advanced nanometer technology.

In order to achieve the above object, the present application adopts the following technical solutions.

First, the present application provides a novel current sink circuit with controllable output voltage, including: the bias module comprises at least two first output ends and at least one first input end; the feedback module comprises at least two second output ends and second input ends with the number equal to that of the first output ends; and the source electrode of the first N-channel MOS tube is grounded. Wherein the first output of the bias module is coupled to the corresponding second input of the feedback module. The first input terminal of the bias module serves as the input terminal of the novel current sink circuit. One of the second output ends of the feedback module is interconnected with the drain electrode of the first N-channel MOS tube and serves as the output end of the novel current trap circuit. And the other of the second output ends of the feedback modules is interconnected with the grid electrode of the first N-channel MOS tube so as to ensure that the voltage of the input end of the current sink circuit is equal to the voltage of the output end of the current sink circuit.

Further, in the foregoing aspect of the present application, the bias module includes an operational amplifier, a ninth N-channel MOS transistor, an eighth P-channel MOS transistor, and a second resistor. The positive input end of the operational amplifier is used as the first input end of the bias module. And the negative input end of the operational amplifier and one end of the second resistor are interconnected with the source electrode of the ninth N-channel MOS tube. And the output end of the operational amplifier is interconnected with the grid electrode of the ninth N-channel MOS tube and is used as the first output end of the bias module. And the drain electrode of the ninth N-channel MOS tube is interconnected with the grid electrode and the drain electrode of the eighth P-channel MOS tube. One end of the second resistor is grounded. And the source electrode of the eighth P-channel MOS tube is connected with a power supply.

Further, in one or more of the above aspects of the present application, the feedback module includes a second N-channel MOS transistor, a fifth N-channel MOS transistor, a sixth N-channel MOS transistor, a third P-channel MOS transistor, a fourth P-channel MOS transistor, and a seventh P-channel MOS transistor. And the source electrode of the second N-channel MOS tube is used as the output end of the feedback module. And the grid electrode of the second N-channel MOS tube is used as the input end of the feedback module. And the drain electrode of the second N-channel MOS tube, the drain electrode of the third P-channel MOS tube, the grid electrode of the third P-channel MOS tube and the grid electrode of the fourth P-channel MOS tube are interconnected. And the drain electrode of the fourth P-channel MOS tube, the drain electrode of the fifth N-channel MOS tube, and the grid electrode of the fifth N-channel MOS tube are interconnected with the grid electrode of the sixth N-channel MOS tube. And the drain electrode of the sixth N-channel MOS tube is interconnected with the drain electrode of the seventh P-channel MOS tube and serves as a second output end of the feedback module. And the grid electrode of the seventh P-channel MOS tube is used as the second input end of the feedback module. And the source electrode of the fifth N-channel MOS tube and the source electrode of the sixth N-channel MOS tube are grounded. The source electrode of the third P-channel MOS tube, the source electrode of the fourth P-channel MOS tube and the source electrode of the seventh P-channel MOS tube are connected with a power supply.

Still further, in one or more aspects of the present application, the feedback module further includes a second capacitor. Wherein. And the source electrode of the second N-channel MOS tube is coupled with one end of the second capacitor, and the drain electrode of the sixth N-channel MOS tube and the drain electrode of the seventh P-channel MOS tube are interconnected with the other end of the second capacitor and used as a second output end of the feedback module to ensure that the working state of the feedback module is stabilized.

Alternatively, in one or more aspects of the present application, the novel current sink circuit further includes a first resistor. One end of the first resistor is coupled to the second output end of the feedback module and the drain electrode of the first N-channel MOS tube, and the other end of the first resistor is interconnected with a power supply to ensure that the static bias current keeps feedback stability.

Alternatively, in one or more aspects of the present application, the novel current sink circuit further includes a first capacitor. One end of the first capacitor is coupled to the second output end of the feedback module and the drain electrode of the first N-channel MOS tube, and the other end of the first capacitor is grounded so as to stabilize the capacitor under the condition that the output current of the current sink changes.

Still further, in one or more aspects of the present application, the bias module couples the first output terminal to the respective second input terminals of the plurality of feedback modules to multiplex the bias module itself.

Secondly, this application still provides a controllable current trap circuit of output voltage, includes: the bias module comprises at least two first output ends and at least one first input end; the feedback module comprises at least two second output ends and second input ends with the number equal to that of the first output ends; the source electrode of the first N-channel MOS tube is grounded; and a first resistor and a first capacitor. Wherein the first output of the bias module is coupled to the corresponding second input of the feedback module. The first input terminal of the bias module serves as the input terminal of the novel current sink circuit. One of one end of the first resistor, one end of the first capacitor and the second output end of the feedback module is interconnected with the drain electrode of the first N-channel MOS tube and serves as the output end of the novel current trap circuit. The other end of the first capacitor is grounded. And the other of the second output ends of the feedback modules is interconnected with the grid electrode of the first N-channel MOS tube so as to ensure that the voltage of the input end of the current sink circuit is equal to the voltage of the output end of the current sink circuit.

According to the technical scheme of the application, the method has the following beneficial effects: compared with the traditional current sink circuit, the circuit of the application adopts a simpler feedback module to greatly improve the bandwidth of the circuit, and meanwhile, the circuit can multiplex a bias module under a plurality of current sinks, so that the area and the power consumption of the circuit are greatly reduced, and the circuit is more flexible and wide.

Drawings

Advantages and mode of realisation of the invention will become more apparent and clearer from the following detailed description of the invention, given by way of example only, with reference to the accompanying drawings, which are given for illustrating the invention and not in any way limiting, and in which:

FIG. 1 is a schematic diagram of a conventional current sink circuit;

FIG. 2 is a schematic diagram of one embodiment of a current sink circuit of the present application;

FIG. 3 is a detailed schematic diagram of an embodiment of the current sink circuit shown in FIG. 2;

fig. 4 is a schematic diagram of another embodiment of the current sink circuit of the present application, wherein the bias modules are multiplexed.

These drawings will be described in detail below.

Detailed Description

The following detailed description is merely exemplary in nature and is not intended to limit the disclosure or the application and uses thereof. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background or the following detailed description.

Embodiments of the present disclosure are described herein. However, it is to be understood that the disclosed embodiments are merely exemplary, and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As will be appreciated by one of skill in the art, various features illustrated and described with reference to any one of the figures can be combined with features illustrated in one or more of the figures to produce embodiments that are not explicitly illustrated or described. The combination of features illustrated provides a representative embodiment of a typical application. However, various combinations and modifications of these features consistent with the teachings of the present disclosure may be desired for particular applications or implementations.

Certain terminology may be used in the following description for reference purposes only and is therefore not intended to be limiting. For example, terms such as "above" and "below" refer to directions referenced in the drawings. Terms such as "front," "back," "left," "right," "back," and "side" describe the orientation and/or position of various parts of a component or element within a consistent but arbitrary frame of reference that becomes apparent with reference to the text and associated drawings describing the component or element in question. Also, terms such as "first," "second," "third," and the like may be used to describe individual components. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Fig. 1 shows a conventional current sink circuit. As shown, the current sink circuit utilizes a similar structure to that of LDO to generate a voltage that meets the swing requirements of practical applications. However, as noted above, if a large number of channels require more current sinks, the structure shown in fig. 1 needs to be multiplexed in its entirety, resulting in a larger circuit area. In addition, if a circuit with high-speed response is required, a large-bandwidth operational amplifier is often required, so that a large amount of power consumption is wasted on the operational amplifier, and the chip area and the power consumption are increased.

Referring to fig. 2, in one or more embodiments of the present application, the current sink circuit includes: the bias module U1, the feedback module U2, the first N-channel MOS transistor M1, the first capacitor C1, and the first resistor R1. The connection relationship is as follows: the output vbn of the bias module U1 is connected to the input vbn of the feedback module U2. The output vbp of the bias block U1 is connected to the input vbp of the feedback block U2. At this time, the input terminal vref of the bias block U1 is used as the input vref of the entire current sink circuit. The output vfb of the feedback block U2, one end of the first resistor R1, one end of the first capacitor C1, and the drain of the first N-channel MOS transistor M1 are interconnected to form the output vout of the entire current sink circuit. The output terminal vgn of the feedback module U2 is interconnected with the gate of the first N-channel MOS transistor M1. The source of the first N-channel MOS transistor M1 and one end of the first capacitor C1 are connected to ground gnd. One end of the first resistor R1 is interconnected with the power supply vdd.

Further, referring to fig. 3 as an implementation circuit diagram, in one or more embodiments of the present application, the bias module U1 includes a ninth N-channel MOS transistor M9, an eighth P-channel MOS transistor M8, a second resistor R2, and an operational amplifier OP 1. The connection relationship is as follows: the positive input of the operational amplifier OP1 serves as the input vref of the bias block U1. The negative input terminal of the operational amplifier OP1, one terminal of the second resistor R2 and the source of the ninth N-channel MOS transistor M9 are interconnected. The output terminal of the operational amplifier OP1 is interconnected with the gate of the ninth N-channel MOS transistor M9 as the output terminal vbn of the bias module U1. The drain of the ninth N-channel MOS transistor M9, the gate of the eighth P-channel MOS transistor M8, and the drain of the eighth P-channel MOS transistor M8 are interconnected. The other terminal of the second resistor R2 is connected to ground gnd. The source of the eighth P-channel MOS transistor M8 is connected to the power vdd.

Correspondingly, the feedback module U2 includes a second N-channel MOS transistor M2, a fifth N-channel MOS transistor M5, a sixth N-channel MOS transistor M6, a third P-channel MOS transistor M3, a fourth P-channel MOS transistor M4, a seventh P-channel MOS transistor M7, and a second capacitor C2. The connection relationship is as follows: the source of the second N-channel MOS transistor M2 is connected to one end of the second capacitor C2 as the output terminal vfb of the feedback module U2. The gate of the second N-channel MOS transistor M2 serves as the input vbn of the feedback module U2. The drain electrode of the second N-channel MOS tube M2, the drain electrode of the third P-channel MOS tube M3, the gate electrode of the third P-channel MOS tube M3 and the gate electrode of the fourth P-channel MOS tube M4 are interconnected; the drain of the fourth P-channel MOS transistor M4, the drain of the fifth N-channel MOS transistor M5, the gate of the fifth N-channel MOS transistor M5, and the gate of the sixth N-channel MOS transistor M6 are connected. The drain of the sixth N-channel MOS transistor M6, the drain of the seventh P-channel MOS transistor M7, and the other end of the second capacitor C2 are connected to serve as the output end vgn of the feedback module U2. The gate of the seventh P-channel MOS transistor M7 serves as the input vbp of the feedback module U2. The source of the fifth N-channel MOS transistor M5 and the source of the sixth N-channel MOS transistor M6 are grounded gnd. The source of the third P-channel MOS transistor M3, the source of the fourth P-channel MOS transistor M4 and the source of the seventh P-channel MOS transistor M7 are connected to the power vdd.

When the circuit works normally, the output voltage of the current sink can be controlled by changing the input voltage of the bias module. Under the clamping action of the operational amplifier OP1, the voltage at the negative input terminal of the operational amplifier OP1 is equal to the reference voltage. A current associated with the input resistance is thus generated across the second resistor R2. The voltage at the gate of the ninth N-channel MOS transistor M9 changes according to the magnitude of the current, i.e., the input voltage increases and the gate voltage increases, and vice versa decreases. The eighth P-channel MOS transistor M8 and the seventh P-channel MOS transistor M7 form a current mirror, so that the current flowing through the seventh P-channel MOS transistor M7 is proportional to the current flowing through the eighth P-channel MOS transistor M8. The third P-channel MOS transistor M3 and the fourth P-channel MOS transistor M4, and the fifth N-channel MOS transistor M5 and the sixth N-channel MOS transistor M6 also form a current mirror, so that the current flowing through the sixth N-channel MOS transistor M6 is also proportional to the current flowing through the second N-channel MOS transistor M2. Under the action of the feedback module U1, since the currents flowing through the seventh P-channel MOS transistor M7 and the sixth N-channel MOS transistor M6 are equal, the voltage at the gate source of the ninth N-channel MOS transistor M9 must be equal to the voltage at the gate source of the second N-channel MOS transistor M2, and thus the voltage value at the output end must be equal to the voltage at the input end. In addition, the second capacitor C2 ensures stable operation of the feedback module. The output current of the current sink circuit can change according to the change of the load, the first capacitor C1 mainly acts as a voltage stabilizing capacitor, and the first resistor R1 is mainly used for generating a static bias current to keep feedback stable.

Fig. 4 illustrates a method of multiplexing a bias module with multiple current sinks. At this time, the bias module U1 may couple the first output terminal to the corresponding second input terminals of the plurality of feedback modules U2 (for example, as shown, to the corresponding second input terminals of two feedback modules U2A and U2B, respectively, and the feedback modules U2A and U2B are coupled to the corresponding first N-channel MOS transistors M1A and M1B, the first capacitors C1A and C1B, and the first resistors R1A and R1B, respectively; the coupling manner of the related electronic components is the same as that of the previously described embodiment of the single feedback module U2), thereby multiplexing the bias module U1 itself into the plurality of feedback modules. Therefore, high-speed operational amplification is not needed in each feedback module U2A and U2B, feedback can be achieved only by using a simple structure, and therefore the area and power consumption of a chip are greatly reduced.

It should be emphasized that many variations and modifications may be made to the embodiments described herein, the requirements of which are to be understood as acceptable examples. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims. Moreover, any of the steps described herein may be performed concurrently or in a different order than the order of the steps described herein. Moreover, as should be apparent, the features and attributes of the specific embodiments disclosed herein may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure.

Conditional language (such as, inter alia, "can," "e.g.," etc.) as used herein is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states unless specifically stated otherwise or otherwise understood in the context in which they are used. Thus, such conditional language is not generally intended to imply that features, elements, and/or states are in any way essential to one or more embodiments or that one or more embodiments necessarily include logic for deciding (with or without author input or prompting) whether these features, elements, and/or states are included in any particular embodiment or whether these features, elements, and/or states are to be performed in any particular embodiment.

Also, the following terms may be used herein. The singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to an item includes a reference to one or more items. The term "some" means one, two or more, and generally applies to some or all of a selected number. The term "plurality" refers to two or more items. The terms "about" or "approximately" mean that the quantity, dimensions, size, layout, parameters, shape, and other characteristics are not necessarily exact, but may be approximate and/or larger or smaller, as desired, reflecting acceptable tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art. The term "substantially" means that the recited feature, parameter, or value does not have to be achieved exactly, but may be offset or varied by amounts that do not preclude the effect that the characteristic is intended to provide, including: such as tolerances, measurement errors, measurement accuracy limitations, and other factors known to those skilled in the art.

Numerical data may be represented or presented herein in a range format. It is to be understood that such range format is used merely for convenience and brevity and, thus, such range format should be interpreted flexibly to include not only the numerical values recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. By way of illustration, a numerical range of "about 1 to 5" should be interpreted to include not only the values explicitly recited in about 1 to about 5, but also to include individual values and sub-ranges within the indicated range. Accordingly, included within this numerical range are individual values such as 2, 3, and 4, and sub-ranges such as "about 1 to about 3", "about 2 to about 4", and "about 3 to about 5", "1 to 3", "2 to 4", "3 to 5", and the like. This principle applies equally to ranges reciting only one numerical value (e.g., "about greater than 1"), and should apply regardless of the breadth of the range or the characteristics being described. For convenience, multiple items may be presented in a common list. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. Furthermore, when the terms "and" or "are used in conjunction with a list of items, the terms" and "or" should be interpreted broadly, as any one or more of the listed items may be used alone or in conjunction with other listed items. The term "alternatively" refers to the selection of one of two or more alternatives, but is not intended to limit the selection to only those listed alternatives or to only one of the listed alternatives at a time, unless the context clearly indicates otherwise.

While exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms encompassed by the claims. The words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention. As previously described, features of various embodiments may be combined to form exemplary aspects of the disclosure that may not be explicitly described or illustrated. While various embodiments may be described as providing advantages over or being preferred over other embodiments or prior art implementations with respect to one or more desired characteristics, those skilled in the art will recognize that one or more features or characteristics may be compromised to achieve overall system attributes desired for a particular application and implementation. These attributes may include, but are not limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, serviceability, weight, manufacturability, ease of assembly, and the like. Accordingly, embodiments that do not describe as desirable one or more features as other embodiments or prior art embodiments are not outside the scope of the present invention and may be desirable for particular applications.

Claims

1. A current sink circuit with controllable output voltage, comprising:

the bias module (U1) comprises at least two first output ends, at least one first input end, an operational amplifier (OP1), a ninth N-channel MOS (M9), an eighth P-channel MOS (M8) and a second resistor (R2);

the feedback module (U2) comprises at least two second output ends, second input ends, a second N-channel MOS tube (M2), a fifth N-channel MOS tube (M5), a sixth N-channel MOS tube (M6), a third P-channel MOS tube (M3), a fourth P-channel MOS tube (M4) and a seventh P-channel MOS tube (M7), wherein the number of the second input ends is equal to that of the at least two first output ends; and

a first N-channel MOS transistor (M1), wherein the source electrode of the first N-channel MOS transistor (M1) is grounded;

wherein at least two first outputs of the bias module (U1) are coupled to respective second inputs of the feedback module (U2), a first input of the bias module (U1) serves as an input of the current sink circuit, one of at least two second outputs of the feedback module (U2) is interconnected to the drain of the first N-channel MOS transistor (M1) and serves as an output of the current sink circuit, and another one of at least two second outputs of the feedback module (U2) is interconnected to the gate of the first N-channel MOS transistor (M1) to ensure that the voltage at the input of the current sink circuit is equal to the voltage at the output of the current sink circuit;

wherein a positive input of the operational amplifier (OP1) is used as a first input of the bias module (U1); the negative input end of the operational amplifier (OP1) and one end of the second resistor (R2) are interconnected with the source electrode of the ninth N-channel MOS transistor (M9); the output end of the operational amplifier (OP1) is interconnected with the gate of the ninth N-channel MOS tube (M9) as one of at least two first output ends of the bias module (U1); the drain electrode of the ninth N-channel MOS tube (M9) is interconnected with the gate electrode and the drain electrode of the eighth P-channel MOS tube (M8) to serve as the other one of the at least two first output ends of the biasing module (U1); the other end of the second resistor (R2) is grounded; the source electrode of the eighth P-channel MOS tube (M8) is connected with a power supply;

wherein the source of the second N-channel MOS transistor (M2) is one of at least two second outputs of the feedback module (U2), the gate of the second N-channel MOS transistor (M2) is one of the second inputs of the feedback module (U2), and the drain of the second N-channel MOS transistor (M2), the drain of the third P-channel MOS transistor (M3), the gate of the third P-channel MOS transistor (M3) and the gate of the fourth P-channel MOS transistor (M4) are interconnected; the drain electrode of the fourth P-channel MOS transistor (M4), the drain electrode of the fifth N-channel MOS transistor (M5), the gate electrode of the fifth N-channel MOS transistor (M5) and the gate electrode of the sixth N-channel MOS transistor (M6) are interconnected; the drain electrode of the sixth N-channel MOS transistor (M6) and the drain electrode of the seventh P-channel MOS transistor (M7) are interconnected to serve as the other one of the at least two second output ends of the feedback module (U2); the gate of the seventh P-channel MOS transistor (M7) is used as the other of the second input ends of the feedback module (U2); the source electrode of the fifth N-channel MOS tube (M5) and the source electrode of the sixth N-channel MOS tube (M6) are grounded; the source electrode of the third P-channel MOS tube (M3), the source electrode of the fourth P-channel MOS tube (M4) and the source electrode of the seventh P-channel MOS tube (M7) are connected with a power supply.

2. The current sink circuit according to claim 1, wherein the feedback module (U2) further comprises a second capacitor (C2), wherein the source of the second N-channel MOS transistor (M2) is coupled to one end of the second capacitor (C2), and the drain of the sixth N-channel MOS transistor (M6) and the drain of the seventh P-channel MOS transistor (M7) are interconnected to the other end of the second capacitor (C2) as another one of the at least two second output terminals of the feedback module (U2) to ensure that the operating state of the feedback module (U2) is stabilized.

3. The current sink circuit according to claim 1, further comprising a first resistor (R1), wherein one end of the first resistor (R1) is coupled to one of the at least two second output terminals of the feedback module (U2) and the drain of the first N-channel MOS transistor (M1), and the other end of the first resistor (R1) is interconnected with a power supply to ensure that a static bias current keeps feedback stable.

4. The current sink circuit according to claim 1, further comprising a first capacitor (C1), wherein one end of the first capacitor (C1) is coupled to one of the at least two second output terminals of the feedback module (U2) and the drain of the first N-channel MOS transistor (M1), and the other end of the first capacitor (C1) is grounded to stabilize the capacitor in case of a change in the output current of the current sink.

5. The current sink circuit according to any of claims 1 to 3, wherein the bias module (U1) couples the at least two first outputs to respective second inputs of a plurality of feedback modules (U2) for multiplexing the bias module (U1) itself.

6. A current sink circuit with controllable output voltage, comprising:

the feedback module (U2) comprises at least two second output ends, second input ends, a second N-channel MOS tube (M2), a fifth N-channel MOS tube (M5), a sixth N-channel MOS tube (M6), a third P-channel MOS tube (M3), a fourth P-channel MOS tube (M4) and a seventh P-channel MOS tube (M7), wherein the number of the second input ends is equal to that of the at least two first output ends;

a first N-channel MOS transistor (M1), wherein the source electrode of the first N-channel MOS transistor (M1) is grounded; and

a first resistor (R1) and a first capacitor (C1);

wherein at least two first outputs of the bias module (U1) are coupled to respective second inputs of the feedback module (U2), a first input of the bias module (U1) serves as an input of the current sink circuit, one end of the first resistor (R1), one end of the first capacitor (C1) and one of at least two second output ends of the feedback module (U2) are interconnected with the drain electrode of the first N-channel MOS tube (M1) to serve as the output end of the current sink circuit, the other end of the first resistor (R1) is connected with a power supply, the other end of the first capacitor (C1) is grounded, the other of the at least two second output ends of the feedback module (U2) is interconnected with the gate of the first N-channel MOS transistor (M1), to ensure that the voltage at the input of the current sink circuit is equal to the voltage at the output of the current sink circuit;

wherein a positive input of the operational amplifier (OP1) is used as a first input of the bias module (U1); the negative input end of the operational amplifier (OP1) and one end of the second resistor (R2) are interconnected with the source electrode of the ninth N-channel MOS transistor (M9); the output end of the operational amplifier (OP1) is interconnected with the gate of the ninth N-channel MOS tube (M9) as one of at least two first output ends of the bias module (U1); the drain electrode of the ninth N-channel MOS tube (M9) is interconnected with the gate electrode and the drain electrode of the eighth P-channel MOS tube (M8) to serve as the other one of the at least two first output ends of the bias module (U1); the other end of the second resistor (R2) is grounded; the source electrode of the eighth P-channel MOS tube (M8) is connected with a power supply;

wherein the source of the second N-channel MOS transistor (M2) is used as one of at least two second output ends of the feedback module (U2); the gate of the second N-channel MOS transistor (M2) is used as one of the second input ends of the feedback module (U2); the drain electrode of the second N-channel MOS tube (M2), the drain electrode of the third P-channel MOS tube (M3), the gate electrode of the third P-channel MOS tube (M3) and the gate electrode of the fourth P-channel MOS tube (M4) are interconnected; the drain electrode of the fourth P-channel MOS transistor (M4), the drain electrode of the fifth N-channel MOS transistor (M5), the gate electrode of the fifth N-channel MOS transistor (M5) and the gate electrode of the sixth N-channel MOS transistor (M6) are interconnected; the drain electrode of the sixth N-channel MOS transistor (M6) and the drain electrode of the seventh P-channel MOS transistor (M7) are interconnected to serve as the other one of the at least two second output ends of the feedback module (U2); the gate of the seventh P-channel MOS transistor (M7) is used as the other of the second input ends of the feedback module (U2); the source electrode of the fifth N-channel MOS tube (M5) and the source electrode of the sixth N-channel MOS tube (M6) are grounded; the source electrode of the third P-channel MOS tube (M3), the source electrode of the fourth P-channel MOS tube (M4) and the source electrode of the seventh P-channel MOS tube (M7) are connected with a power supply.