CN110581180A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN110581180A CN110581180A CN201910865839.4A CN201910865839A CN110581180A CN 110581180 A CN110581180 A CN 110581180A CN 201910865839 A CN201910865839 A CN 201910865839A CN 110581180 A CN110581180 A CN 110581180A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 27
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims description 103
- 239000002184 metal Substances 0.000 claims description 103
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 63
- 239000010408 film Substances 0.000 claims description 33
- 239000000377 silicon dioxide Substances 0.000 claims description 31
- 235000012239 silicon dioxide Nutrition 0.000 claims description 30
- 230000003647 oxidation Effects 0.000 claims description 17
- 238000007254 oxidation reaction Methods 0.000 claims description 17
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 11
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000007935 neutral effect Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Computer Hardware Design (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
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- Electrodes Of Semiconductors (AREA)
Abstract
the embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device provided by the embodiment of the invention comprises a first electrode layer; the substrate layer is positioned on the first electrode layer; an epitaxial layer on the substrate layer and having a first surface remote from the substrate layer; the epitaxial layer is arranged on the first surface of the epitaxial layer, the first surface of the epitaxial layer is provided with a first well region, the first surface of the epitaxial layer is provided with a second well region, the second surface of the epitaxial layer is provided with a plurality of doping units, the first surface of the epitaxial layer is provided with a first surface, the second surface of the epitaxial layer is provided with a second surface, the second surface of the epitaxial layer is provided with; and the second electrode layer covers the epitaxial layer and the well region. The semiconductor device provided by the embodiment of the invention has excellent forward rated conduction capability and stronger surge current conduction capability.
Description
Technical Field
the invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
the Schottky diode is used as a semiconductor device structure with long development time and mature technology, belongs to an ultra-high-speed semiconductor device, is widely applied to the field of energy conversion, and is mainly used as a high-frequency application environment.
the existing Schottky diode usually adopts a junction barrier Schottky diode, and under the condition of large current (surge current comes temporarily), a PN junction is conducted, and minority carriers are injected into a drift region of a device, so that the surge current capability of the device is improved, and therefore, the larger the area of a P-type trap region is, the stronger the surge current capability of the device is. However, the larger the area of the P-type well region, the smaller the schottky area between the P-type well regions of the device under the same area condition, resulting in a significant increase in the on-resistance of the device in the forward conduction mode.
Accordingly, a need exists for a new and improved semiconductor device.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, which can have an excellent forward rated conduction capability and a stronger surge current conduction capability.
in a first aspect, an embodiment of the present invention provides a semiconductor device, including:
a first electrode layer;
The substrate layer is positioned on the first electrode layer;
An epitaxial layer on the substrate layer and having a first surface remote from the substrate layer;
The epitaxial layer is arranged on the first surface of the epitaxial layer, the first surface of the epitaxial layer is provided with a first well region, the first surface of the epitaxial layer is provided with a second well region, the second surface of the epitaxial layer is provided with a plurality of doping units, the first surface of the epitaxial layer is provided with a first surface, the second surface of the epitaxial layer is provided with a second surface, the second surface of the epitaxial layer is provided with;
And the second electrode layer covers the epitaxial layer and the well region.
According to an aspect of the embodiments of the present invention, an orthogonal projection of the first well region on the first surface is a stripe shape, and an orthogonal projection of the doping unit on the first surface is a circle or a polygon.
according to an aspect of the embodiments of the invention, the plurality of doping units in the second well region are regularly arranged, and one or more rows of doping units are distributed in a second direction perpendicular to the first direction.
According to an aspect of the embodiment of the present invention, the second electrode layer includes a first metal layer and a second metal layer electrically connected to each other, the first metal layer is located on a side of the well region opposite to the substrate layer, and the second metal layer covers the epitaxial layer and the first metal layer;
Ohmic contact is formed between the first metal layer and the well region, and Schottky contact is formed between the second metal layer and the epitaxial layer.
According to an aspect of the embodiments of the present invention, the first metal layer includes a plurality of metal blocks disposed in a one-to-one correspondence with the well region, and an orthographic projection of the metal blocks on the well region is within a boundary of the well region.
According to an aspect of the embodiments of the present invention, in the first direction, a maximum width of the first well region is 3 μm to 20 μm, and a maximum width of the doping unit is 0.5 μm to 3 μm.
according to one aspect of the embodiments of the present invention, the substrate layer is of the first conductivity type having a first doping concentration, the epitaxial layer is of the first conductivity type having a second doping concentration, and the well region is of the second conductivity type;
the first doping concentration is higher than the second doping concentration, the first conduction type is opposite to the second conduction type, and the first conduction type is N type.
in a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate layer;
Forming an epitaxial layer on the substrate layer;
Forming a well region on a first surface, far away from the substrate layer, of the epitaxial layer, wherein the well region is arranged from the first surface to the interior of the epitaxial layer, the well region comprises a first well region and a second well region which are alternately distributed in a first direction, the second well region comprises a plurality of doping units which are distributed at intervals, and the maximum width of the first well region in the first direction is larger than or equal to the maximum width of the doping units;
forming a first electrode layer on one side of the substrate layer, which is back to the epitaxial layer;
And forming a second electrode layer on one side of the epitaxial layer and the well region, which is back to the substrate layer, wherein the second electrode layer covers the epitaxial layer and the well region.
According to an aspect of the embodiments of the present invention, forming a second electrode layer on a side of the epitaxial layer and the well region facing away from the substrate layer includes:
Forming a first metal layer on one side of the well region, which is opposite to the substrate layer, wherein the first metal layer comprises a plurality of metal blocks which are arranged in one-to-one correspondence with the well region, and orthographic projections of the metal blocks on the well region are in the boundary range of the well region;
And forming a second metal layer covering the epitaxial layer and the first metal layer, wherein the second metal layer is electrically connected with the first metal layer to obtain a second electrode layer.
according to an aspect of the embodiments of the invention, the step of forming the well region and the first metal layer includes:
padding a silicon dioxide film on the first surface of the epitaxial layer far away from the substrate layer, and carrying out graphical processing on the silicon dioxide film;
injecting second conductive type ions above the silicon dioxide film after the graphical treatment to obtain a well region;
forming a carbon film covering the silicon dioxide film and the well region after the patterning treatment;
carrying out high-temperature annealing treatment and removing the carbon film;
Carrying out high-temperature oxidation treatment to obtain a silicon dioxide film after high-temperature oxidation, wherein the thickness and the width of the silicon dioxide film after high-temperature oxidation are larger than those of the silicon dioxide film before high-temperature oxidation;
And performing metal coating on one side of the well region, which is back to the substrate layer, and performing alloy annealing to obtain a first metal layer, wherein the first metal layer comprises a plurality of metal blocks which are arranged in one-to-one correspondence with the well region, and orthographic projections of the metal blocks on the well region are in the boundary range of the well region.
According to the semiconductor device provided by the embodiment of the invention, the first well region and the second well region are alternately distributed in the first direction, the second well region comprises a plurality of doping units which are distributed at intervals, and the maximum width of the first well region in the first direction is larger than the maximum width of the doping units. On one hand, the wider first well region can enable a PN junction of the well region to be started in advance when surge current is conducted, minority carrier holes are injected into a high-resistance drift region, the minority carrier concentration injected and accumulated in the drift region is large, and in order to maintain a neutral condition of a semiconductor, the majority carrier concentration is correspondingly and greatly increased, so that the resistivity of the semiconductor is obviously reduced, namely the conductivity is greatly increased, a conductivity modulation effect is formed, and the surge current conducting capacity of a semiconductor device is improved; on the other hand, the second well region comprises a plurality of doping units which are distributed at intervals, and the area of the non-well region (namely the Schottky region) can be increased relative to the first well region, so that the reverse leakage current blocking capability of the semiconductor device is prevented from being influenced, and the forward rated current conducting capability of the semiconductor device is ensured.
drawings
other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
fig. 1 shows a schematic top view of a semiconductor device according to an embodiment of the present invention;
fig. 2 shows a schematic top view of a semiconductor device according to another embodiment of the present invention;
Fig. 3 shows a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present invention;
FIG. 4 shows a schematic flow diagram of a method of fabricating a semiconductor device according to one embodiment of the present invention;
fig. 5A to 5O are schematic cross-sectional structure diagrams illustrating steps of forming respective components included in a semiconductor device manufacturing method according to an embodiment of the present invention.
Description of reference numerals:
1-a first electrode layer;
2-a substrate layer; 20-a terminal structure; 21-a silicon dioxide film; 211-a silica thin film after high temperature oxidation; 22-ions of a second conductivity type; 23-a carbon film; 24-a first electrode metal; 25-a second electrode metal; 26-a passivation layer;
3-an epitaxial layer; 30-a first surface;
4-well region; 41-a first well region; 42-a second well region; 420-doping unit;
5-a second electrode layer; 51-a first metal layer; 52-second metal layer; 510-a metal block;
d1-first direction; d2-second direction.
Detailed Description
features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
it is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
silicon carbide junction barrier schottky diode, on the basis of simple schottky diode structure promptly, added PN junction structure, when bearing reverse voltage, the depletion region of PN structure can expand and protect the schottky metal between the PN junction, and the electric field that the schottky metal bore reduces greatly to can show and reduce reverse leakage current.
the starting voltage of the silicon carbide PN structure is about 2.6V generally, the potential difference above and below the PN junction is guaranteed to be larger than 2.6V when the PN structure is started, the potential difference below the PN junction mainly comes from the transverse flow of current, and the applicant finds that the potential difference above and below the most central position of the PN structure can reach 2.6V at the earliest, and the larger the width of the PN structure is, the earlier the PN junction is started. However, the wider the PN structure, the smaller the area of the schottky portion between the PN junctions, which results in a significant increase in the on-resistance of the semiconductor device in the forward rated on mode.
In order to solve the problems in the prior art, the semiconductor device provided by the invention comprises a certain number of wider PN junctions, so that minority carrier injection is ensured to be started earlier, and simultaneously comprises a large number of narrower PN junctions, so that the area of a Schottky part is ensured. The structure of the semiconductor device provided by the present invention is described in detail below.
fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention. Fig. 2 is a schematic top view of a semiconductor device according to another embodiment of the present invention. Fig. 3 is a schematic cross-sectional structure diagram of a semiconductor device according to an embodiment of the present invention. Referring to fig. 1 to 3, the semiconductor device according to the embodiment of the present invention includes a first electrode layer 1, a substrate layer 2, an epitaxial layer 3, a well region 4, and a second electrode layer 5. It should be understood that fig. 1 and 2 only show schematic top views of a partial region of a semiconductor device, and the layout structure of the well region 4 shown in fig. 1 or 2 can be formed by designing and drawing a photolithography mask with corresponding shape features. Fig. 3 shows a schematic cross-sectional structure of only a partial region of the semiconductor device.
the semiconductor device according to the embodiment of the present invention may be a semiconductor device of silicon carbide, silicon, gallium nitride, gallium oxide, diamond, or the like. Preferably, the semiconductor device according to the embodiment of the present invention is a silicon carbide semiconductor device. The shape of the semiconductor device may be square, rectangular, circular, irregular, etc., which is not limited by the present invention.
the first electrode layer 1 serves as a cathode of the semiconductor device. The first electrode layer 1 may be a metal layer, which may be gold, silver, copper, etc. or a combination thereof.
the substrate layer 2 is located on the first electrode layer 1, and in one embodiment, an ohmic contact is formed between the first electrode layer 1 and the substrate layer 2. The substrate layer 2 is of a first conductivity type having a first doping concentration.
an epitaxial layer 3 on the substrate layer 2 and having a first surface 30 remote from the substrate layer 2, the epitaxial layer 3 being of the first conductivity type having a second doping concentration. In some alternative embodiments, the first conductivity type is N-type, and the substrate layer 2 and the epitaxial layer 3 are both N-type semiconductors. The N-type semiconductor has a large number of electrons, and the electrons have higher mobility, so that the N-type semiconductor has stronger current conduction capability. In some alternative embodiments, the first doping concentration is higher than the second doping concentration, for example, the substrate layer 2 is a heavily doped N-type semiconductor and the epitaxial layer 3 is a lightly doped N-type semiconductor.
the well region 4 is arranged to extend from the first surface 30 of the epitaxial layer 3 into the epitaxial layer 3. In one embodiment, well region 4 is formed within epitaxial layer 3 and at least a partial region overlaps first surface 30 of epitaxial layer 3. The epitaxial layer 3 may have a plurality of well regions 4, the well regions 4 being of the second conductivity type. In some alternative embodiments, the first conductivity type is opposite to the second conductivity type, i.e. the well region 4 is P-type.
the well region 4 includes first well regions 41 and second well regions 42 alternately distributed in the first direction D1, the second well regions 42 include a plurality of doping units 420 distributed at intervals, and a maximum width of the first well regions 41 in the first direction is greater than or equal to a maximum width of the doping units 420 in the first direction. Illustratively, the maximum width of the first well region 41 is 3 μm to 20 μm, and the maximum width of the doping unit 420 is 0.5 μm to 3 μm, and the widths of the first well region 41 and the doping unit 420 may be set according to actual requirements. For example, the first direction D1 may be understood as a width direction of the first well region 41, and the second direction D2 may be understood as a length direction of the first well region 41.
the second electrode layer 5 covers the epitaxial layer 3 and the well region 4. The second electrode layer 5 serves as the anode of the semiconductor device. The first metal layer 51 may be a metal layer of gold, silver, copper, or the like, or a combination thereof. The second electrode layer 5 forms an ohmic contact with the well region 4, and the second electrode layer 5 forms a schottky contact with the epitaxial layer 3 around the well region 4.
according to the semiconductor device provided by the embodiment of the invention, the first well regions 41 and the second well regions 42 are alternately distributed in the first direction D1, the second well regions 42 include a plurality of doping units 420 distributed at intervals, and the maximum width of the first well regions 41 in the first direction D1 is greater than the maximum width of the doping units 420. On one hand, the wider first well region 41 can enable a PN junction of the well region to be opened in advance when surge current is conducted, minority carrier holes are injected into a drift region with high resistance, the minority carrier concentration injected and accumulated in the drift region is large, and in order to maintain a neutral condition of a semiconductor, the majority carrier concentration is correspondingly and greatly increased, so that the resistivity of the semiconductor is obviously reduced, namely the conductivity of the semiconductor is greatly increased, a conductivity modulation effect is formed, and the surge current conducting capability of a semiconductor device is improved; on the other hand, the second well region 42 includes a plurality of doping units 420 distributed at intervals, and the area of the non-well region (i.e., schottky region) can be increased relative to the first well region 41, so as to avoid affecting the reverse leakage current blocking capability of the semiconductor device, and ensure the forward rated current conducting capability of the semiconductor device.
In some alternative embodiments, an orthographic projection of the first well region 41 on the first surface 30 is a stripe shape, and an orthographic projection of the doping unit 420 on the first surface 30 is a circle or a polygon. Referring to fig. 1, the orthographic projection of the first well region 41 is a continuous strip shape, and the orthographic projection of the doping unit 420 is a circle, or referring to fig. 2, the orthographic projection of the first well region 41 is a continuous strip shape, and the orthographic projection of the doping unit 420 is a regular hexagon, and the orthographic projection of the exemplary doping unit 420 on the first surface 30 may also be a regular octagon, a regular decagon, an irregular polygon, or the like. The strip-shaped first well region 41 can ensure that the wider first well region 41 enters a minority carrier injection mode at the same time, and the circular or polygonal doping units 420 are distributed at intervals to form the second well region 42, so that the area ratio of the non-well region (i.e. schottky region) can be increased, the reverse blocking leakage current capability of the semiconductor device is prevented from being influenced, and the forward rated current conducting capability and the reverse blocking capability of the semiconductor device are ensured.
in some alternative embodiments, the doped cells 420 in the second well 42 are regularly arranged, and one or more columns of doped cells 420 are distributed in a second direction D2 perpendicular to the first direction D1. Referring to fig. 1 or fig. 2, three rows of doping units 420 are distributed in the second direction D2. It is understood that, in the second direction D2, the more the columns of the doping units 420 are distributed, or the larger the spacing distance of the doping units 420 is, the larger the area ratio of the schottky region is, and the number of the columns of the doping units 420 and the spacing distance of the doping units 420 may be set according to practical requirements, which is not limited in the present invention.
In some optional embodiments, with reference to fig. 3, the second electrode layer 5 includes a first metal layer 51 and a second metal layer 52 electrically connected to each other, the first metal layer 51 is located on a side of the well region 4 facing away from the substrate layer 2, and the second metal layer 52 covers the epitaxial layer 3 and the first metal layer 51; an ohmic contact is formed between the first metal layer 51 and the well region 4, and a schottky contact is formed between the second metal layer 52 and the epitaxial layer 3. For example, the first metal layer 51 and the second metal layer 52 may be metal layers of gold, silver, copper, or the like, or a combination thereof.
in some alternative embodiments, the first metal layer 51 includes a plurality of metal blocks 510 disposed in a one-to-one correspondence with the well regions 4, and orthographic projections of the metal blocks 510 on the well regions 4 are within boundaries of the well regions 4. The boundaries of the metal blocks 510 are smaller than the boundaries of the well regions 4, ensuring that the metal blocks 510 forming ohmic contacts with the well regions 4 are completely within the well regions 4, avoiding the risk of short circuits.
It is understood that according to the semiconductor device of the embodiment of the present invention, the termination structure 20 and the passivation layer 26 may be further disposed at the edge of the semiconductor device, for example, referring to fig. 3, the termination structure 20 is located at a side of the epitaxial layer 3 facing away from the substrate layer 2, and the passivation layer 26 is located at a side of the termination structure 20 facing away from the epitaxial layer 3.
Fig. 4 shows a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the invention. As shown in fig. 4, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:
S110, providing a substrate layer 2;
s120, forming an epitaxial layer 3 on the substrate layer 2;
s130, forming a well region 4 on the first surface 30 of the epitaxial layer 3 away from the substrate layer 2, where the well region 4 is extended from the first surface 30 into the epitaxial layer 3, the well region 4 includes first well regions 41 and second well regions 42 alternately distributed in a first direction, the second well region 42 includes a plurality of doping units 420 distributed at intervals, and a maximum width of the first well region 41 in the first direction is greater than or equal to a maximum width of the doping units 420;
S140, forming a first electrode layer 1 on one side of the substrate layer 2 back to the epitaxial layer 3;
S150, a second electrode layer 5 is formed on the side of the epitaxial layer 3 and the well region 4 opposite to the substrate layer 2, and the second electrode layer 5 covers the epitaxial layer 3 and the well region 4.
According to the semiconductor device provided by the embodiment of the invention, the first well regions 41 and the second well regions 42 are alternately distributed in the first direction, the second well regions 42 include a plurality of doping units 420 distributed at intervals, and the maximum width of the first well regions 41 in the first direction is greater than the maximum width of the doping units 420. On one hand, the wider first well region 41 can enable a PN junction of the well region to be opened in advance when surge current is conducted, minority carrier holes are injected into a drift region with high resistance, the minority carrier concentration injected and accumulated in the drift region is large, and in order to maintain a neutral condition of a semiconductor, the majority carrier concentration is correspondingly and greatly increased, so that the resistivity of the semiconductor is obviously reduced, namely the conductivity of the semiconductor is greatly increased, a conductivity modulation effect is formed, and the surge current conducting capability of a semiconductor device is improved; on the other hand, the second well region 42 includes a plurality of doping units 420 distributed at intervals, and the area of the non-well region (i.e., schottky region) can be increased relative to the first well region 41, so as to avoid affecting the reverse leakage current blocking capability of the semiconductor device, and ensure the forward rated current conducting capability of the semiconductor device.
In some alternative embodiments, the first electrode layer 1 and the second electrode layer 5 may be formed simultaneously.
in some alternative embodiments, the step of forming the second electrode layer 5 comprises:
Forming a first metal layer 51 on one side of the well region 4 opposite to the substrate layer 2, wherein the first metal layer 51 comprises a plurality of metal blocks 510 arranged in one-to-one correspondence with the well region 4, and orthographic projections of the metal blocks 510 on the well region 4 are within the boundary range of the well region 4;
a second metal layer 52 is formed to cover the epitaxial layer 3 and the first metal layer 51, and the second metal layer 52 is electrically connected to the first metal layer 51 to obtain a second electrode layer 5.
the orthographic projection of the metal block 510 on the well region 4 is within the boundary of the well region 4, so that short circuit is avoided.
in some alternative embodiments, the step of forming the well region 4 and the first metal layer 51 includes:
Padding a silicon dioxide film 21 on a first surface 30 of the epitaxial layer 3 far away from the substrate layer 2, and carrying out graphical processing on the silicon dioxide film 21;
implanting ions 22 of the second conductivity type above the patterned silicon dioxide film 21 to obtain a well region 4;
Forming a carbon film 23 covering the patterned silicon dioxide film 21 and the well region 4;
Performing high-temperature annealing treatment, and removing the carbon film 23;
performing high-temperature oxidation treatment to obtain a silicon dioxide film 211 after high-temperature oxidation, wherein the thickness and the width of the silicon dioxide film 211 after high-temperature oxidation are larger than those of the silicon dioxide film 21 before high-temperature oxidation;
And performing metal coating on one side of the well region 4, which is opposite to the substrate layer 2, and performing alloy annealing to obtain a first metal layer 51, wherein the first metal layer 51 comprises a plurality of metal blocks 510 which are arranged in one-to-one correspondence with the well region 4, and orthographic projections of the metal blocks 510 on the well region 4 are within the boundary range of the well region 4.
The silicon dioxide film 21 used as the ion implantation mask is oxidized at high temperature, and then used to continuously define the boundary of the ohmic contact electrode (i.e. the metal block 510), since the silicon dioxide becomes wider and thicker after oxidation, and the defined ohmic contact boundary is smaller than the previously defined well region 4 boundary, so as to ensure that the metal block 510 forming ohmic contact with the well region 4 is completely within the well region 4, and avoid the risk of subsequent short circuit. The step can save an additional photoetching process required in the traditional process, save the production cost, and meanwhile, the new process flow can break through the process limit of a photoetching machine, and ohmic contact electrodes (namely metal blocks 510) can be formed on the doping units 420 with the width of about 1 micron.
in a specific embodiment, a semiconductor device manufacturing method of an embodiment of the present invention includes the steps of:
Providing an initial silicon carbide semiconductor material as shown in fig. 5A, the initial silicon carbide semiconductor material having a substrate layer 2 of heavily doped N-type and an epitaxial layer 3 of lightly doped N-type;
Forming a termination structure 20 of the silicon carbide device as shown in fig. 5B by patterning the mask and implanting a low dose of ions of the second conductivity type;
Forming a silicon oxide film 21 as shown in fig. 5C by a chemical vapor deposition method;
patterning the silicon dioxide film 21 by using a photolithography technique and an etching process to obtain a patterned silicon dioxide film 21 as shown in fig. 5D;
As shown in fig. 5E, a certain dose of second conductivity type ions 22 is implanted to obtain the well region 4 shown in fig. 5F;
as shown in fig. 5G, a carbon film 23 is stacked to a certain thickness;
Performing a high temperature anneal to activate the implanted second conductivity type ions 22, illustratively, at a temperature of 1500-1600 ℃;
as shown in fig. 5H, the carbon film 23 for high-temperature annealing protection is removed by plasma ashing;
Performing a high-temperature oxidation process, wherein the previous silicon dioxide thin film (21) becomes wider and thicker after oxidation to obtain a high-temperature oxidized silicon dioxide thin film 211 shown in FIG. 5I;
removing the thin silicon dioxide film formed on the exposed silicon carbide surface by utilizing dry etching or wet etching in a short time;
as shown in fig. 5J, a second electrode metal 25 capable of forming an ohmic contact is deposited on the first surface 30 of the epitaxial layer 3, and a first electrode metal 24 capable of forming an ohmic contact is also deposited on the surface of the substrate layer 2 opposite to the epitaxial layer 3, so as to obtain a first electrode layer 1 as a cathode;
Annealing the alloy at a certain temperature, removing the residual non-alloyed ohmic metal, and forming a plurality of metal blocks 510 in ohmic contact with the well region 4 as shown in fig. 5K, wherein the plurality of metal blocks 510 form the first metal layer 51;
As shown in fig. 5L, the silicon dioxide film 211 after the high temperature oxidation is removed;
as shown in fig. 5M, passivation layer 26 is deposited;
As shown in fig. 5N, the passivation layer 26 is patterned using photolithography and etching techniques; and depositing a metal forming a Schottky contact with the non-well region;
As shown in fig. 5O, the schottky metal is patterned by using a photolithography technique and an etching process, and the alloy is annealed to form the second metal layer 52 of the schottky contact, so that the resulting first metal layer 51 and second metal layer 52 constitute the second electrode layer 5 serving as an anode;
further, conventional front and back metal thickening processes may be performed.
it should be noted that, in this document, the sequence of the process steps is only an example of this embodiment, and it is also obvious to those skilled in the art that the sequence may be properly adjusted according to the cost control and the different manufacturing process capabilities, without affecting the implementation effect of the embodiment of the present invention.
it should be understood that the description herein of specific embodiments of the invention is exemplary and should not be construed as unduly limiting the scope of the invention. The scope of the invention is defined by the claims appended hereto, and encompasses all embodiments and obvious equivalents thereof that fall within their scope.
Claims (10)
1. A semiconductor device, comprising:
a first electrode layer (1);
a substrate layer (2) located on the first electrode layer (1);
an epitaxial layer (3) located on the substrate layer (2) and having a first surface (30) remote from the substrate layer (2);
The well region (4), the well region (4) is extended from the first surface (30) to the epitaxial layer (3), the well region (4) includes a first well region (41) and a second well region (42) alternately distributed in a first direction, the second well region (42) includes a plurality of doping units (420) distributed at intervals, and the maximum width of the first well region (41) in the first direction is greater than or equal to the maximum width of the doping units (420);
And the second electrode layer (5) covers the epitaxial layer (3) and the well region (4).
2. The semiconductor device according to claim 1, wherein an orthographic projection of the first well region (41) on the first surface (30) is a stripe shape, and an orthographic projection of the doping unit (420) on the first surface (30) is a circle or a polygon shape.
3. the semiconductor device according to claim 1, wherein the doped cells (420) are regularly arranged in the second well region (42), and one or more columns of the doped cells (420) are distributed in a second direction perpendicular to the first direction.
4. the semiconductor device according to claim 1, wherein the second electrode layer (5) comprises a first metal layer (51) and a second metal layer (52) which are electrically connected, the first metal layer (51) is located on a side of the well region (4) facing away from the substrate layer (2), and the second metal layer (52) is disposed to cover the epitaxial layer (3) and the first metal layer (51);
An ohmic contact is formed between the first metal layer (51) and the well region (4), and a Schottky contact is formed between the second metal layer (52) and the epitaxial layer (3).
5. The semiconductor device according to claim 4, wherein the first metal layer (51) comprises a plurality of metal blocks (510) arranged in a one-to-one correspondence with the well regions (4), and an orthographic projection of the metal blocks (510) on the well regions (4) is within boundaries of the well regions (4).
6. A semiconductor device according to any of claims 1 to 5, characterized in that in the first direction the maximum width of the first well region (41) is between 3 μm and 20 μm and the maximum width of the doping unit (420) is between 0.5 μm and 3 μm.
7. semiconductor device according to any of claims 1 to 5, characterized in that the substrate layer (2) is of a first conductivity type having a first doping concentration, the epitaxial layer (3) is of the first conductivity type having a second doping concentration, and the well region (4) is of the second conductivity type;
the first doping concentration is higher than the second doping concentration, the first conduction type is opposite to the second conduction type, and the first conduction type is N type.
8. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate layer (2);
forming an epitaxial layer (3) on the substrate layer (2);
forming a well region (4) on a first surface (30) of the epitaxial layer (3) far away from the substrate layer (2), wherein the well region (4) is arranged from the first surface (30) to extend into the epitaxial layer (3), the well region (4) comprises a first well region (41) and a second well region (42) which are alternately distributed in a first direction, the second well region (42) comprises a plurality of doping units (420) which are distributed at intervals, and the maximum width of the first well region (41) in the first direction is greater than or equal to the maximum width of the doping units (420);
forming a first electrode layer (1) on one side of the substrate layer (2) opposite to the epitaxial layer (3);
And forming a second electrode layer (5) on one side of the epitaxial layer (3) and the well region (4) back to the substrate layer (2), wherein the second electrode layer (5) covers the epitaxial layer (3) and the well region (4).
9. Method for manufacturing a semiconductor device according to claim 8, wherein forming a second electrode layer (5) on a side of the epitaxial layer (3) and the well region (4) facing away from the substrate layer (2) comprises:
forming a first metal layer (51) on one side of the well region (4) opposite to the substrate layer (2), wherein the first metal layer (51) comprises a plurality of metal blocks (510) which are arranged in one-to-one correspondence with the well region (4), and orthographic projections of the metal blocks (510) on the well region (4) are within the boundary range of the well region (4);
And forming a second metal layer (52) covering the epitaxial layer (3) and the first metal layer (51), wherein the second metal layer (52) is electrically connected with the first metal layer (51) to obtain the second electrode layer (5).
10. A method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the well region (4) and the first metal layer (51) comprises:
laying a silicon dioxide film (21) on a first surface (30) of the epitaxial layer (3) far away from the substrate layer (2), and carrying out graphical processing on the silicon dioxide film (21);
injecting second conductive type ions (22) above the silicon dioxide thin film (21) after the patterning treatment to obtain the well region (4);
forming a carbon film (23) covering the silicon dioxide film (21) and the well region (4) after the patterning treatment;
performing high-temperature annealing treatment, and removing the carbon film (23);
performing high-temperature oxidation treatment to obtain a silicon dioxide thin film (211) after high-temperature oxidation, wherein the thickness and the width of the silicon dioxide thin film (211) after high-temperature oxidation are larger than those of the silicon dioxide thin film (21) before high-temperature oxidation;
And carrying out metal coating on one side of the well region (4) opposite to the substrate layer (2), and carrying out alloy annealing to obtain the first metal layer (51), wherein the first metal layer (51) comprises a plurality of metal blocks (510) which are arranged in one-to-one correspondence with the well region (4), and the orthographic projection of the metal blocks (510) on the well region (4) is in the boundary range of the well region (4).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113964183A (en) * | 2021-09-13 | 2022-01-21 | 西安电子科技大学 | Fluorine plasma injection terminal gallium oxide power diode and preparation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040173801A1 (en) * | 2002-12-18 | 2004-09-09 | Infineon Technologies Ag | Schottky diode having overcurrent protection and low reverse current |
| JP2012231019A (en) * | 2011-04-26 | 2012-11-22 | Hitachi Ltd | Silicon carbide diode |
| US20130032809A1 (en) * | 2010-03-08 | 2013-02-07 | Scott Thomas Allen | Semiconductor Devices with Non-Implanted Barrier Regions and Methods of Fabricating Same |
| CN105206681A (en) * | 2014-06-20 | 2015-12-30 | 意法半导体股份有限公司 | Wide Bandgap High-Density Semiconductor Switching Device And Manufacturing Process Thereof |
| CN106847922A (en) * | 2017-01-24 | 2017-06-13 | 深圳基本半导体有限公司 | A kind of wide band gap semiconductor device |
| US20180061951A1 (en) * | 2016-08-25 | 2018-03-01 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device |
| CN210272376U (en) * | 2019-09-12 | 2020-04-07 | 瑞能半导体科技股份有限公司 | Semiconductor device with a plurality of transistors |
-
2019
- 2019-09-12 CN CN201910865839.4A patent/CN110581180A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040173801A1 (en) * | 2002-12-18 | 2004-09-09 | Infineon Technologies Ag | Schottky diode having overcurrent protection and low reverse current |
| US20130032809A1 (en) * | 2010-03-08 | 2013-02-07 | Scott Thomas Allen | Semiconductor Devices with Non-Implanted Barrier Regions and Methods of Fabricating Same |
| JP2012231019A (en) * | 2011-04-26 | 2012-11-22 | Hitachi Ltd | Silicon carbide diode |
| CN105206681A (en) * | 2014-06-20 | 2015-12-30 | 意法半导体股份有限公司 | Wide Bandgap High-Density Semiconductor Switching Device And Manufacturing Process Thereof |
| US20180061951A1 (en) * | 2016-08-25 | 2018-03-01 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device |
| CN106847922A (en) * | 2017-01-24 | 2017-06-13 | 深圳基本半导体有限公司 | A kind of wide band gap semiconductor device |
| CN210272376U (en) * | 2019-09-12 | 2020-04-07 | 瑞能半导体科技股份有限公司 | Semiconductor device with a plurality of transistors |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113964183A (en) * | 2021-09-13 | 2022-01-21 | 西安电子科技大学 | Fluorine plasma injection terminal gallium oxide power diode and preparation method thereof |
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