CN110571332A - Transistor and method of manufacturing the same - Google Patents
Transistor and method of manufacturing the same Download PDFInfo
- Publication number
- CN110571332A CN110571332A CN201910711187.9A CN201910711187A CN110571332A CN 110571332 A CN110571332 A CN 110571332A CN 201910711187 A CN201910711187 A CN 201910711187A CN 110571332 A CN110571332 A CN 110571332A
- Authority
- CN
- China
- Prior art keywords
- forming
- layer
- gate
- manufacturing
- gate dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
Abstract
The application discloses a transistor and a manufacturing method thereof, wherein the manufacturing method of the transistor comprises the following steps: forming carbon nanotubes on a substrate; forming a gate stack structure on the carbon nanotube; and forming an electrical contact on the carbon nanotube, wherein the step of forming the electrical contact comprises: and growing a conductive material on the surface of the carbon nano tube by adopting an electroplating process, wherein the gate stack structure is used as a mask in the electroplating process. The manufacturing method takes the gate laminated structure as a mask, and adopts an electroplating process to selectively grow a conductive material on the source and drain regions on the surface of the carbon nano tube from bottom to top to form electric contact, thereby solving the problems of holes generated when depositing source and drain metals by using deposition means such as sputtering, evaporation and the like and the problem of side wall deposition of the source and drain metals in the prior art.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit device fabrication, and more particularly, to a transistor and a method of fabricating the same.
Background
Carbon Nanotubes (CNTs) have advantages in terms of high speed, low power consumption, and the like, and are considered to be one of the best channel materials for constructing field effect transistors in the future.
In the prior art, when a carbon nanotube transistor is manufactured, for example, a sputtering and evaporation method is used to deposit source and drain metals on the surface of the carbon nanotube from top to bottom. In the deposition process, due to the secondary sputtering effect, the contact electrode area cannot be filled perfectly, so that holes affecting the performance of the device appear.
When a self-aligned process is used to deposit the source and drain metals, the deposition process inevitably occurs simultaneously on the source and drain regions, the gate, and the sidewalls. For a silicon-based device, source and drain metals can form a silicide material with a silicon substrate through annealing, and the source and drain metals deposited on the surface of the side wall are removed through a subsequent wet cleaning process. For the carbon nanotube device, when depositing source and drain metals by deposition means like sputtering, evaporation and the like, the metals deposited on the gate and the side wall cannot be completely removed, so that the side wall is polluted, and parasitic capacitance is increased.
When the non-self-aligned process is adopted to deposit the source and drain metal, although the problem of side wall pollution can be avoided, the problem of holes caused by the secondary sputtering effect cannot be avoided, and in addition, the non-self-aligned process is adopted to deposit the source and drain metal, so that the occupied space (footprint) of the whole package of the device is overlarge.
Therefore, there is a need to further improve the manufacturing process of the source-drain contact of the carbon nanotube device, and solve the problems of the hole, the sidewall deposition of the source-drain metal, and the large occupied space of the device.
Disclosure of Invention
In view of the above, the present invention provides a transistor and a method for manufacturing the same, in which a gate stack structure is used as a mask, and a conductive material is selectively grown from bottom to top in a source/drain region on a surface of a carbon nanotube by an electroplating process to form an electrical contact, thereby solving the problems of a hole, a sidewall deposition of source/drain metal, and an excessively large occupied space of a device.
According to an aspect of the present invention, there is provided a method of manufacturing a transistor, including: forming carbon nanotubes on a substrate; forming a gate stack structure on the carbon nanotube; and forming an electrical contact on the carbon nanotube, wherein the step of forming the electrical contact comprises: and growing a conductive material on the surface of the carbon nano tube by adopting an electroplating process, wherein the gate stack structure is used as a mask in the electroplating process.
Preferably, before forming the electrical contact, forming a protective structure covering the gate stack structure, wherein the protective structure comprises an insulating material.
preferably, the step of forming the gate stack structure comprises: forming a gate dielectric covering the carbon nanotubes; forming a gate conductor on the gate dielectric; patterning the gate conductor; and removing a portion of the gate dielectric to expose a portion of the carbon nanotubes, wherein the gate dielectric comprises an oxide of a group IIIB element, the gate dielectric acting as a stop layer when patterning the gate conductor.
preferably, the material of the gate dielectric comprises yttria.
Preferably, the patterning comprises removing a portion of the gate conductor using an etching process, the etchant comprising a fluorine-based gas.
Preferably, the step of forming the protective structure comprises: forming a mask layer on the gate conductor; forming an oxide layer overlying the mask layer, the gate conductor, and the gate dielectric; forming a protective layer covering the oxide layer; and etching the mask layer, the oxide layer and the protective layer, wherein the etching is stopped when the protective layer forms a side wall morphology, and the mask layer, the oxide layer and the protective layer are remained to form the protective structure.
Preferably, the mask layer, the oxide layer and the protective layer are etched using fluorine-based and chlorine-based gases.
preferably, the step of removing a portion of the gate dielectric comprises: converting the oxide to chloride with a chlorine-based gas; and dissolving the chloride in a solvent.
Preferably, after the electrical contact is formed, the method further comprises: forming an interlayer dielectric layer covering the electric contact and the protection structure; removing part of the interlayer dielectric layer and part of the protective layer to expose the gate conductor; and penetrating the interlayer dielectric layer to form an electric connection structure contacted with the electric contact.
Preferably, the conductive material comprises one or a combination of palladium, scandium, yttrium, aluminum, titanium, gold, molybdenum, platinum, potassium, and calcium.
According to another aspect of the present invention, there is provided a transistor formed by the manufacturing method as described above.
According to the transistor and the manufacturing method thereof provided by the invention, the conductive material is grown on the surface of the carbon nano tube from bottom to top by adopting an electroplating method, so that the problem of holes in the deposition process is solved. In the electroplating process, the grid laminated structure is used as a mask, and the self-alignment process is adopted to form electric contact in the source drain contact area of the carbon nano tube, so that the problem of overlarge occupied space of a device is solved.
Furthermore, by forming the insulating protection structure covering the gate stack structure, in the electroplating process, the source and drain regions of the carbon nanotube are exposed in the electroplating solution, the gate region is covered by the gate stack structure and the protection structure, and only the carbon nanotube exposed in the electroplating solution conducts electricity, so that the protection structure and the gate stack structure can be avoided, and the conductive material can be selectively formed in the source and drain regions of the carbon nanotube.
Compared with the prior art, the bottom-up selective growth mode provided by the application can avoid the deposition effect of the gate and the gate side wall, and greatly reduces the process complexity and the cost.
drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.
Fig. 1 shows a schematic structural diagram of a transistor according to an embodiment of the present invention.
fig. 2a to 2i show cross-sectional views of a method of manufacturing a transistor at various stages according to an embodiment of the invention.
Detailed Description
the invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, a semiconductor device obtained after several steps can be described in one drawing.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
the present invention may be embodied in various forms, some examples of which are described below.
Fig. 1 shows a schematic structural diagram of a carbon nanotube transistor according to an embodiment of the present invention.
As shown in fig. 1, the transistor of the embodiment of the present invention includes: the carbon nanotube-based solar cell comprises a substrate 101, a carbon nanotube 110, a gate stack structure 120, an electrical contact including a source contact structure 130 and a drain contact structure 140, an oxide layer 103, a sidewall spacer 104, an interlayer dielectric layer 106, and a plurality of electrical connection structures 160.
The carbon nanotubes 110 are located on the substrate 101. The gate stack structure 120 covers a portion of the carbon nanotube 110, wherein the gate stack structure 120 includes a gate dielectric 121 and a gate conductor, and the gate dielectric 121 is located on the surface of the carbon nanotube 110. The gate conductor includes a functional layer 122 and an extraction layer 123, which are sequentially stacked on the gate dielectric 121, thereby covering a portion of the gate dielectric 121. The surface of the gate dielectric 121 not covered by the gate conductor is covered by the oxide layer 103, and the oxide layer 103 also covers the sidewalls of the gate conductor. The spacers 104 are located on both sides of the gate conductor and contact the oxide layer 103. The source contact structure 130 and the drain contact structure 140 cover at least a portion of the carbon nanotube 110 and are respectively located at two sides of the gate stack structure 120 and outside the sidewall 104. The interlayer dielectric layer 106 covers the carbon nanotubes 110, the sidewall spacers 104, the source contact structures 130, and the drain contact structures 140. A plurality of electrical connection structures 160 penetrate through the interlayer dielectric layer 106 and are in contact with the source contact structure 130 and the drain contact structure 140, respectively.
In some embodiments, the substrate 101 includes an insulating layer on a supporting substrate. The supporting substrate mainly plays a supporting role, and the material can be silicon, sapphire substrate, quartz, glass, alumina and other hard insulating materials, and any substrate capable of bearing carbon nanotube materials, as long as the substrate is very flat and has good uniformity. In the present embodiment, a silicon material is used as a substrate, and is not particularly limited. The material of the insulating layer comprises silicon oxide, silicon nitride, and high-temperature resistant flexible insulating materials such as PET, PEN, polyimide and the like.
in this embodiment, the material of the gate dielectric 121 includes an oxide of a group IIIB element, preferably yttria. In other embodiments, the material of the gate dielectric 121 includes one or a combination of silicon oxide, silicon oxynitride, high-k (high-k) dielectric material. The gate conductor is a metal conductor, wherein the material of the functional layer 122 includes but is not limited to titanium nitride, and the material of the extraction layer 123 includes metal materials such as tungsten, cobalt, copper, aluminum, and the like. The material of the oxide layer 103 includes, but is not limited to, silicon oxide. The material of the sidewall spacers 104 includes, but is not limited to, silicon nitride. The material of the interlayer dielectric layer 106 includes silicon oxide, low-k (low-k) dielectric material or other insulating material, and the material of the electrical connection structure 160 includes metal material such as tungsten, cobalt, copper, aluminum, etc.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the materials of the gate stack structure 120, the oxide layer 103, the sidewall spacers 104, and the interlayer dielectric layer 106 as required.
In the present embodiment, when the carbon nanotube transistor is an N-type MOSFET, the material of the source contact structure 130 and the drain contact structure 140 includes scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy material thereof or a composite material thereof, and when the carbon nanotube transistor is a P-type MOSFET, the material of the source contact structure 130 and the drain contact structure 140 includes palladium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy material thereof or a composite material thereof.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements on the materials of the source contact structure 130 and the drain contact structure 140 as needed.
Fig. 2a to 2i show cross-sectional views of a method of manufacturing a transistor at various stages according to an embodiment of the invention.
The method of the embodiment of the invention starts with a substrate 101, first forms a carbon nanotube 110 on the substrate 101, then sequentially stacks a gate dielectric 121, a functional layer 122 for forming a gate conductor, a lead-out layer 123 and a mask layer 102 on the carbon nanotube 110, and finally coats a photoresist 10 on the mask layer 102, as shown in fig. 2 a.
In some embodiments, the substrate 101 includes an insulating layer on a supporting substrate. The material of the supporting substrate mainly plays a supporting role, and can be silicon, sapphire substrate, quartz, glass, alumina and other hard insulating materials, and any substrate capable of bearing carbon nanotube materials, as long as the substrate is very flat and has good uniformity. In the present embodiment, a silicon material is used as a substrate, and is not particularly limited. The material of the insulating layer comprises silicon oxide, silicon nitride, and high-temperature resistant flexible insulating materials such as PET, PEN, polyimide and the like. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements of the materials of the supporting substrate and the insulating layer as required.
In this embodiment, the material of the gate dielectric 121 includes an oxide of a group IIIB element, preferably yttria. In other embodiments the material of the gate dielectric 121 comprises silicon oxide, silicon oxynitride, high-k (high-k) dielectric material. The gate conductor is a metal conductor, wherein the material of the functional layer 122 includes but is not limited to titanium nitride, and the material of the extraction layer 123 includes metal materials such as tungsten, cobalt, copper, aluminum, and the like. The material of the mask layer 102 includes, but is not limited to, silicon oxide. The photoresist 10 is preferably Hydrogen Silsesquioxane (HSQ) with a thickness of preferably 100 nm.
In this step, after the photoresist is coated, the photoresist is patterned using an electron beam lithography process to define a gate region.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the material of the gate stack structure 120 as needed, for example, when a front gate process is adopted, the dummy gate electrode may be made of amorphous silicon, polysilicon, or the like.
further, the gate conductor is patterned to define the gate conductor in the defined gate region, as shown in fig. 2 b.
in this step, for example, an Inductively Coupled Plasma Etch (ICPE) process is used to remove a portion of the gate conductor, and the etchant includes a fluorine-based Inductively Coupled Plasma (F-based ICP), since the material of the gate dielectric 121 of this embodiment includes yttria, which has a higher etching selectivity with respect to the gate conductor, the gate dielectric 121 may serve as a stop layer when etching the gate conductor, so as to protect the carbon nanotubes 110 from being damaged by the etchant.
Further, an oxide layer 103 is formed covering the mask layer 102, the gate conductor and the gate dielectric 121, as shown in fig. 2 c.
In this step, the oxide layer 103 conformally coats the surface of the gate dielectric 121, the surface of the mask layer 102, and the sidewalls of the functional layer 122, the extraction layer 123, and the mask layer 102. In the present embodiment, the material of the oxide layer 103 includes silicon oxide, and the thickness is preferably 3 nm.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings on the material and thickness of the oxide layer 103 as required.
Further, a protection layer 104 is formed covering the oxide layer 103, as shown in fig. 2 c.
In this step, the protective layer 104 is formed, for example, by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or a Low Pressure Chemical Vapor Deposition (LPCVD) process. In the present embodiment, the material of the protection layer 104 comprises silicon nitride, and the thickness is preferably 50 nm.
Further, the protection layer 104, the oxide layer 103 and the mask layer 102 are etched, so that the protection layer forms a sidewall profile, as shown in fig. 2 d.
In this step, a portion of the protection layer 104, the oxide layer 103, the mask layer 102 and the gate dielectric 121 are removed, for example, by an Inductively Coupled Plasma (ICPE) etching process, and the etchant includes fluorine-based and chlorine-based inductively coupled plasmas (F-based & Cl-based ICPs). The technological parameters of the etching are adjusted, which comprises the following steps: and controlling the etching to stop when the protective layer forms the side wall morphology, wherein the etching process comprises one or more of reaction pressure, reaction time, reaction temperature, reaction speed, radio frequency power, gas or liquid flow and the like. In this embodiment, the remaining mask layer 102, the oxide layer 103 and the protection layer 104 (sidewall) form a protection structure covering the surface of the gate stack structure, and after the F-based & Cl-based ICP contacts the exposed gate dielectric 121, the yttrium oxide material undergoes a chlorination reaction to form yttrium chloride, which is dissolved by water or other organic solution to expose a portion of the carbon nanotubes 110. By using the property of yttrium chloride being very soluble in water or ethanol, the exposed gate dielectric 121 can be removed without damaging or contaminating the carbon nanotubes 110.
Further, electrical contacts are formed on the surface of the carbon nanotube 110, including a source contact structure and a drain contact structure. In this step, an electroplating process is used to grow a conductive material on the surface of the carbon nanotube 110 to form an electrical contact between the source and drain regions, and then a suitable process is used to completely remove the contact metal in some regions between the devices to achieve insulation between the devices, otherwise, the devices are shorted.
Specifically, the device is first immersed in a salt solution containing a pre-plated metal, the salt solution containing a large number of pre-plated metal ions 1051, as shown in fig. 2 e. Then, the carbon nanotube 110 is used as an electrode, and the preplated metal ions 1051 in the plating solution are transformed into the conductive material 1052 by electrolysis and deposited on the surface of the carbon nanotube 110, as shown in FIG. 2 f. In the electroplating process, the gate stack structure is used as a mask, the gate stack structure is covered by the protective layer 150, and the material forming the protective layer 150 is an insulating material, so that in the electroplating process, only the surface of the conductive carbon nanotube 110 can grow the conductive material 105 from bottom to top, and the protective layer 150 is insulating and cannot be covered by the conductive material 105, so that the purpose of selective growth is achieved, the deposition effect of a gate and a gate side wall is avoided, and the process complexity and the cost are greatly reduced. The conductive material on the carbon nanotubes 110 is then removed, for example, by photolithography and etching processes, to form the source contact structure 130 and the drain contact structure 140 as shown in fig. 2 g.
In the present embodiment, when the carbon nanotube transistor is an N-type MOSFET, the material of the source contact structure 130 and the drain contact structure 140 includes scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy material thereof or a composite material thereof, and when the carbon nanotube transistor is a P-type MOSFET, the material of the source contact structure 130 and the drain contact structure 140 includes palladium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy material thereof or a composite material thereof.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements on the materials of the source contact structure 130 and the drain contact structure 140 as needed.
Further, an interlayer dielectric layer 106 is formed covering the carbon nanotube 110, the source contact structure 130, the drain contact structure 140 and the protection structure 150, as shown in fig. 2 h.
In this step, for example, a PECVD process or a Spin-on (Spin-on) process is used to form the interlayer dielectric layer 106, wherein two sides of the interlayer dielectric layer 106 corresponding to the gate structure correspond to portions of the source-drain contact structure. In the present embodiment, the material of the interlayer dielectric layer 106 includes silicon oxide, low-k (low-k) dielectric material or other insulating material.
however, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements for the material of the interlayer dielectric layer 106 as needed.
Further, the mask layer and a portion of the interlayer dielectric layer 106 are removed to expose the gate conductor, as shown in fig. 2 i.
In this step, for example, an ICPE process is used to etch the interlayer dielectric layer 106, the etchant includes fluorine-based inductively coupled plasma (F-based ICP), and the adjusting of the etching process parameters includes: one or more of reaction pressure, reaction time, reaction temperature, reaction speed, radio frequency power, gas or liquid flow rate, etc., and the etching is controlled to stop when the extraction layer 123 is completely exposed after the mask layer is removed.
In this embodiment, although the oxide layer 103 and the sidewall spacers 104 are also partially etched, after the etching is finished, the oxide layer 103 and the sidewall spacers 104 still cover the sidewalls of the gate conductor to protect the gate conductor, and the lead-out layer 123 is higher than the portion of the interlayer dielectric layer 106 corresponding to the source-drain contact structure.
Further, a plurality of electrical connection structures 160 contacting the source contact structure 130 and the drain contact structure 140 are formed through the interlayer dielectric layer 106, as shown in fig. 1.
After the plurality of electrical connection structures 160 are formed, the plurality of electrical connection structures 160 are etched by an ICPE process, such that the surfaces of the plurality of electrical connection structures 160 are recessed. Wherein the etchant comprises (F-based ICP).
Because the extraction layer 123 in the gate is higher than the electrical connection structure 160, and the sidewalls of the gate conductor are protected by the oxide layer 102, the sidewall 103, and the interlayer dielectric layer 106, the problem of breakdown between the electrical connection structure 160 and the gate conductor is prevented.
according to the transistor and the manufacturing method thereof provided by the invention, the conductive material is grown on the surface of the carbon nano tube from bottom to top by adopting an electroplating method, so that the problem of holes in the deposition process is solved. In the electroplating process, the grid laminated structure is used as a mask, and the self-alignment process is adopted to form electric contact in the source drain contact area of the carbon nano tube, so that the problem of overlarge occupied space of a device is solved.
Furthermore, by forming the insulating protection structure covering the gate stack structure, in the electroplating process, the source and drain regions of the carbon nanotube are exposed in the electroplating solution, the gate region is covered by the gate stack structure and the protection structure, and only the carbon nanotube exposed in the electroplating solution conducts electricity, so that the protection structure and the gate stack structure can be avoided, and the conductive material can be selectively formed in the source and drain regions of the carbon nanotube.
Compared with the prior art, the bottom-up selective growth mode provided by the application can avoid the deposition effect of the gate and the gate side wall, and greatly reduces the process complexity and the cost.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (11)
1. A method of manufacturing a transistor, comprising:
Forming carbon nanotubes on a substrate;
Forming a gate stack structure on the carbon nanotube; and
Forming an electrical contact on the carbon nanotube,
Wherein the step of forming the electrical contact comprises: and growing a conductive material on the surface of the carbon nano tube by adopting an electroplating process, wherein the gate stack structure is used as a mask in the electroplating process.
2. The method of manufacturing of claim 1, further comprising, prior to forming the electrical contact, forming a protective structure overlying the gate stack structure, the protective structure comprising an insulating material.
3. the manufacturing method of claim 2, wherein the step of forming the gate stack structure comprises:
Forming a gate dielectric covering the carbon nanotubes;
Forming a gate conductor on the gate dielectric;
Patterning the gate conductor; and
Removing portions of the gate dielectric to expose portions of the carbon nanotubes,
Wherein the gate dielectric comprises an oxide of a group IIIB element, the gate dielectric acting as a stop layer when patterning the gate conductor.
4. A method of manufacture according to claim 3, wherein the material of the gate dielectric comprises yttria.
5. the method of manufacturing of claim 3, wherein the patterning comprises removing a portion of the gate conductor using an etching process, the etchant comprising a fluorine-based gas.
6. The manufacturing method of claim 3, wherein the step of forming the protective structure comprises:
Forming a mask layer on the gate conductor;
Forming an oxide layer overlying the mask layer, the gate conductor, and the gate dielectric;
Forming a protective layer covering the oxide layer; and
Etching the mask layer, the oxide layer and the protection layer,
And stopping etching when the protective layer forms a side wall morphology, and forming the protective structure by the residual mask layer, the oxide layer and the protective layer.
7. The manufacturing method according to claim 6, wherein the mask layer, the oxide layer, and the protective layer are etched using fluorine-based and chlorine-based gases.
8. The method of manufacturing of claim 7, wherein removing a portion of the gate dielectric comprises:
Converting the oxide to chloride with a chlorine-based gas; and
Dissolving the chloride in a solvent.
9. The method of manufacturing of claim 6, further comprising, after forming the electrical contact:
Forming an interlayer dielectric layer covering the electric contact and the protection structure;
removing part of the interlayer dielectric layer and part of the protective layer to expose the gate conductor; and
an electrical connection structure is formed through the interlayer dielectric layer in contact with the electrical contacts.
10. the manufacturing method according to any one of claims 1 to 9, wherein the conductive material includes one or a combination of palladium, scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, and calcium.
11. a transistor formed by the manufacturing method according to any one of claims 1 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910711187.9A CN110571332B (en) | 2019-08-02 | 2019-08-02 | Transistor and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910711187.9A CN110571332B (en) | 2019-08-02 | 2019-08-02 | Transistor and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110571332A true CN110571332A (en) | 2019-12-13 |
| CN110571332B CN110571332B (en) | 2023-06-23 |
Family
ID=68774328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910711187.9A Active CN110571332B (en) | 2019-08-02 | 2019-08-02 | Transistor and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110571332B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101099248A (en) * | 2005-01-07 | 2008-01-02 | 国际商业机器公司 | Self-aligned process for nanotube/nanowire fets |
| CN101593699A (en) * | 2008-05-30 | 2009-12-02 | 清华大学 | The preparation method of thin-film transistor |
| CN103107199A (en) * | 2011-10-11 | 2013-05-15 | 国际商业机器公司 | Patterning contacts in carbon nanotube devices |
| CN103531476A (en) * | 2012-07-03 | 2014-01-22 | 中国科学院微电子研究所 | Manufacturing method for semiconductor device |
| CN103855023A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device and semiconductor device |
| CN104979402A (en) * | 2015-05-14 | 2015-10-14 | 北京大学 | Carbon nano-tube three-dimensional fin-like field effect transistor and preparation method therefor |
| US20160380217A1 (en) * | 2015-06-29 | 2016-12-29 | International Business Machines Corporation | Self-aligned carbon nanotube transistor including source/drain extensions and top gate |
-
2019
- 2019-08-02 CN CN201910711187.9A patent/CN110571332B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101099248A (en) * | 2005-01-07 | 2008-01-02 | 国际商业机器公司 | Self-aligned process for nanotube/nanowire fets |
| CN101593699A (en) * | 2008-05-30 | 2009-12-02 | 清华大学 | The preparation method of thin-film transistor |
| CN103107199A (en) * | 2011-10-11 | 2013-05-15 | 国际商业机器公司 | Patterning contacts in carbon nanotube devices |
| CN103531476A (en) * | 2012-07-03 | 2014-01-22 | 中国科学院微电子研究所 | Manufacturing method for semiconductor device |
| CN103855023A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device and semiconductor device |
| CN104979402A (en) * | 2015-05-14 | 2015-10-14 | 北京大学 | Carbon nano-tube three-dimensional fin-like field effect transistor and preparation method therefor |
| US20160380217A1 (en) * | 2015-06-29 | 2016-12-29 | International Business Machines Corporation | Self-aligned carbon nanotube transistor including source/drain extensions and top gate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110571332B (en) | 2023-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8680512B2 (en) | Graphene transistor with a self-aligned gate | |
| TWI527096B (en) | Growth epi as interconnection layer on mos structure | |
| CN103295912A (en) | Graphene transistor production method based on self-aligning technology | |
| CN104067384A (en) | Method and system for a gallium nitride vertical JFET with self-aligned source and gate | |
| US10263004B2 (en) | Semiconductor device and method of manufacturing | |
| TW202008433A (en) | Method of manufacturing semiconductor device | |
| TW201611269A (en) | Series-connected transistor structure and method of manufacturing the same | |
| CN103000498A (en) | Graphene nano-ribbon manufacturing method, MOSFET (metal-oxide -semiconductor field effect transistor) and manufacturing method thereof | |
| TW202129765A (en) | Method for manufacturing semiconductor device | |
| CN111180583A (en) | Transistor and method of manufacturing the same | |
| TW202125581A (en) | Method of manufacturing semiconductor device | |
| CN110571332B (en) | Transistor and method for manufacturing the same | |
| US7449748B2 (en) | Semiconductor device | |
| US20120211825A1 (en) | Trench MOSFET and Method for Fabricating Same | |
| CN110783461B (en) | Transistor and method for manufacturing the same | |
| US20230361175A1 (en) | Transistor and method for fabricating the same | |
| US11791399B2 (en) | Method for fabricating semiconductor device with graphene-based element | |
| US11824099B2 (en) | Source/drains in semiconductor devices and methods of forming thereof | |
| CN110364438B (en) | Transistor and method for manufacturing the same | |
| CN113644109B (en) | Transistor and preparation method thereof | |
| CN113745111B (en) | Semiconductor device and method of forming the same | |
| US10672623B2 (en) | Transistor and method of manufacturing the same | |
| CN110400841B (en) | Semiconductor device and method for manufacturing the same | |
| CN103021859B (en) | Fabricating method of transistor | |
| CN113659077A (en) | Semiconductor transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |