CN113659077A - Semiconductor transistor and preparation method thereof - Google Patents

Abstract

The invention provides a transistor and a preparation method thereof, wherein the transistor is provided with a semiconductor channel layer on a substrate, a high-k gate dielectric layer is arranged on the channel layer, a gate structure is formed on the channel layer, the gate structure comprises two side walls and a gate dielectric layer positioned in the two side walls, the width of the high-k gate dielectric layer is larger than that of the gate structure, and a source electrode and a drain electrode are respectively formed on a semiconductor at two sides of the gate structure and the part of the high-k gate dielectric layer exceeding the gate structure. The transistor realizes the optimization of a semiconductor transistor, particularly a device structure with energy band distribution of a narrow-bandgap semiconductor transistor, can inhibit off-state current and static energy consumption by regulating and controlling the energy band of a source end and a drain end, is compatible with an industrialized semiconductor process, and can realize large-scale integrated preparation.

Description

Semiconductor transistor and preparation method thereof

Technical Field

The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a transistor with a non-silicon novel semiconductor material channel layer and a manufacturing method thereof.

Background

As semiconductor integrated circuit technology continues to scale down to sub-3 nm technology nodes, silicon-based integrated circuits are likely to reach the limits of silicon materials and physical quantum mechanics. With the continued development of the electronic industry, there is a strong need to find new materials with more potential and advantages to extend silicon materials, and break through the limits of moore's law. Carbon Nanotubes (CNTs) have high carrier mobility and long mean free path, nano-scale tube diameter, and can be used to build faster, lower power consumption, smaller-sized nano-field effect transistors, and thus Carbon Nanotube (CNTs) electrons are considered as one of the future information technologies that have the potential to extend silicon-based CMOS devices and continue to support moore's law.

For low-dimensional materials such as carbon nanotubes, graphene, black phosphorus or two-dimensional materials, the forbidden bandwidth is generally smaller than that of silicon, wherein the typical band gap of the carbon nanotubes is about 0.8eV, the band gap of the corresponding silicon is about 1.12eV, and the band gap is narrower, so that the width of the tunneling barrier between the drain ends in an off state is greatly compressed, a larger tunneling current is generated, and the static energy consumption is influenced (as shown in fig. 1). The off-state tunneling effect of the corresponding transistor is more remarkable than that of a silicon-based transistor, and in the existing undoped MOS structure, the Schottky barrier existing near a channel bias drain terminal is too thin due to the over-concentrated and over-strong electric field of the drain terminal, so that the Schottky tunneling is serious. And no ion implantation and doping are carried out in the preparation process of the transistor, so that the light doped source drain (LDD) of the silicon-based transistor can not be realized to finely regulate the distribution of the doping concentration of a drain end on the space, and the negative effects such as short channel effect, junction leakage current, parasitic current and the like are reduced. In addition, the narrow-bandgap nanomaterial has good interface property, few surface states, no Fermi pinning effect when in contact with metal, and the energy band structure is difficult to adjust by adjusting the work function of the contact metal.

The feedback gate structure is connected to the vicinity of a channel bias drain end, and the feedback gate is electrically connected with a drain end metal electrode, so that a rectangular potential barrier which is not changed along with a drain bias voltage is clamped at the drain end, schottky tunneling is greatly inhibited, off-state leakage current is inhibited, and the on-off ratio is improved. The existing semi-self-aligned feedback gate process still has many defects, the process is still limited in a laboratory process, is incompatible with the current industrial process of integrated circuits, cannot be prepared in a large scale, cannot be realized on a technical node with the size less than 90nm, and has the difficulty in the aspect of size reduction (scaling-down).

Therefore, there is a need to design a device structure capable of optimizing the band distribution of a semiconductor transistor, suppressing off-state current and static power consumption, and compatible with an industrialized semiconductor process, and capable of realizing large-scale integrated manufacturing.

Disclosure of Invention

The invention provides a semiconductor transistor and a preparation method thereof aiming at the problems in the prior art, and the technical scheme of the invention is as follows:

a semiconductor transistor comprising a substrate having a semiconductor channel layer thereon, a high-k gate dielectric layer having a first width W1 on the semiconductor channel layer, and a gate structure having a second width W2 thereon, the gate structure including two sidewalls and a gate electrode therein, wherein:

the first width W1 is greater than the second width W2 and covers the semiconductor channel layer and the widened portion of the high-k gate dielectric layer on both sides of the gate structure with a source and a drain, respectively.

The semiconductor channel layer is made of a narrow-band-gap semiconductor material and is selected from carbon nano tubes, graphene and two-dimensional materials such as molybdenum disulfide, tungsten disulfide and black phosphorus.

Preferably, tungsten plugs are provided on the source and drain electrodes for metal interconnection.

Preferably, the substrate is selected from hard insulating materials such as silicon oxide, quartz, glass and aluminum oxide, and high-temperature resistant flexible insulating materials such as PET, PEN and polyimide.

The source and drain electrodes may be selected from metals such as titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), or different types of stacked combinations thereof.

The high-k gate dielectric layer can be selected from hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, lanthanum oxide, titanium oxide, or different types of laminated structures or ternary compound structures of the oxides.

The invention provides a preparation method of a semiconductor transistor adopting a front gate process, which comprises the following steps:

s1, providing a substrate, forming a semiconductor channel layer on the substrate, and further depositing a high-k gate dielectric layer on the substrate;

s2, forming a grid electrode on the high-k grid dielectric layer, and depositing a low-k dielectric layer on the obtained structure, wherein the low-k dielectric layer covers the high-k grid dielectric layer, the side wall and the top of the grid electrode;

s3, carrying out back etching on the low-k dielectric layer by adopting first etching gas to form a side wall, and further carrying out etching removal on the high-k gate dielectric layer below the side wall by taking the pattern of the side wall as a mask to form a gate structure with a first width W1 (as shown in figure 7);

s4, further etching the low-k side wall by using second etching gas, and simultaneously keeping the high-k gate dielectric layer at the lower layer not etched to form a gate structure with a second width W2 (as shown in figure 8);

and S5, depositing a source-drain metal layer on the structure obtained in the step S4 to form a final transistor structure.

And further forming a tungsten plug and an interlayer dielectric layer on the source drain metal layer.

Further, depositing a source-drain metal layer, patterning the source-drain metal layer, depositing an interlayer dielectric layer, forming a through hole corresponding to the source-drain metal layer, and forming a tungsten plug in the through hole.

Further, an interlayer dielectric layer is formed firstly, then a through hole is formed, and then a source drain metal layer and a tungsten plug are deposited in the through hole simultaneously.

The first etching gas can adopt chlorine-based, bromine-based or fluorine-based etching gas, and the second etching gas can adopt fluorine-based etching gas.

The semiconductor channel layer is made of a narrow-band-gap semiconductor material and is selected from carbon nano tubes, graphene and two-dimensional materials such as molybdenum disulfide, tungsten disulfide and black phosphorus.

The low-k dielectric layer is selected from silicon oxide (SiO)₂) Silicon oxyfluoride (SiOF), silicon oxyfluoride containing carbon (SiOCH), hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), organic polymer, inorganic polymer or TEOS and a laminated structure thereof, wherein the high-k gate dielectric layer is selected from hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, lanthanum oxide, titanium oxide, or different laminated structures or ternary compound structures of the above oxides.

Preferably, the source and drain are selected from metals such as titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), or different types of stacked combinations thereof.

Another aspect of the present invention provides a method for manufacturing a semiconductor transistor using a gate last process, including the steps of:

s1, providing a substrate, forming a semiconductor channel layer on the substrate, and further depositing a first high-k gate dielectric layer on the substrate;

s2, forming a dummy gate on the first high-k gate dielectric layer and depositing a low-k dielectric layer on the obtained structure, wherein the low-k dielectric layer covers the first high-k gate dielectric layer and the side wall and the top of the dummy gate electrode;

s3, carrying out back etching on the low-k dielectric layer by using first etching gas to form a side wall, and further carrying out etching removal on the first high-k gate dielectric layer by using the side wall as a mask to form a false gate structure with a first width W1;

s4, further etching the side wall by using second etching gas, and simultaneously keeping the first high-k gate dielectric layer not etched to form a false gate structure with a second width W2;

s5, depositing a source-drain metal layer on the structure obtained in the step S4, and forming a tungsten plug and an interlayer dielectric layer on the source-drain metal layer;

and S6, defining a dummy gate electrode pattern by adopting a mask process, removing the dummy gate, and forming a metal gate in the dummy gate.

Preferably, the semiconductor channel layer is a narrow bandgap semiconductor material selected from carbon nanotubes, graphene, and two-dimensional materials such as molybdenum disulfide, tungsten disulfide, and black phosphorus.

Preferably, in step S6, the first high-k gate dielectric layer under the dummy gate is etched at the same time, a second high-k gate dielectric layer is deposited on the bottom and the sidewall of the formed via, and then a gate electrode is formed therein.

The first high-k gate dielectric layer and the second high-k gate dielectric layer can be selected from hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, lanthanum oxide, titanium oxide, or different types of laminated structures or ternary compound structures of the above oxides, wherein the first high-k gate dielectric layer and the second high-k gate dielectric layer are the same or different.

The source and drain electrodes may be selected from metals such as titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), or different types of stacked combinations thereof.

According to the invention, the width of the high-k gate dielectric between the gate electrode of the transistor and the semiconductor channel is extended by adjusting the thickness of the low-k side wall between the gate electrode of the transistor and the source-drain electrode, so that the channel region partially regulated and controlled by the drain electrode is increased, the width of the potential barrier between drain electrode bands is further increased, and the problem of static power consumption caused by off-state tunneling current can be solved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing the technical solution thereof with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a prior art carbon nanotube transistor structure;

FIG. 2 is a schematic diagram of a transistor structure according to the present invention;

FIG. 3 is a flow chart of a process for fabricating a transistor using a front gate process;

FIG. 4 is a schematic diagram of forming a channel layer and a high-k gate dielectric layer on a substrate;

FIG. 5 is a schematic diagram of gate formation;

FIG. 6 is a schematic diagram of forming a low-k dielectric layer;

FIG. 7 is a schematic diagram of a gate structure formed with a first width W1 by etching back with a first etching gas;

FIG. 8 is a schematic diagram of a gate structure etched back to a second width W2 using a second etching gas;

FIG. 9 is a schematic diagram of a structure for forming a source/drain;

FIG. 10 is a flow chart of a process for fabricating a transistor using a back gate process;

FIG. 11 is a schematic diagram of forming a channel layer, a first high-k gate dielectric layer, a dummy gate, and a low-k dielectric layer on a substrate;

FIG. 12 is a schematic view of a dummy gate structure formed with a first width W1 by etching back with a first etching gas;

FIG. 13 is a schematic view of a dummy gate structure etched back with a second etching gas to form a second width W2;

FIG. 14 is a schematic view of forming a source/drain, an interlayer dielectric layer, and a tungsten plug and performing CMP;

FIG. 15 is a schematic view of the dummy gate and first high-k gate dielectric layer removed;

FIG. 16 is a schematic view of depositing a second high-k gate dielectric layer and a gate electrode;

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Like elements in the drawings are represented by like reference numerals, and parts of the drawings are not drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.

As shown in fig. 2, the semiconductor transistor of the present invention includes a substrate 100, where the substrate 100 is selected from a group consisting of hard insulating materials such as silicon oxide, quartz, glass, and aluminum oxide, and high temperature resistant flexible insulating materials such as PET, PEN, and polyimide, and in this embodiment, the substrate 10 is a quartz substrate. A semiconductor channel layer 101 is provided on the substrate 100, wherein the semiconductor channel layer 101 is a narrow bandgap semiconductor material selected from the group consisting of carbon nanotubes, graphene, two-dimensional materials such as molybdenum disulfide, black phosphorus, and in the present embodiment, a carbon nanotube channel layer. The material of the high-k gate dielectric layer 102 with the first width W1 on the semiconductor channel layer 101 may be selected from hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, lanthanum oxide, titanium oxide, or different types of stacked structures or ternary compound structures of the above oxides. The high-k gate dielectric layer 102 has a gate structure with a second width W2, and the first width W1 is equal to or greater than the second width W2, so that the high-k gate dielectric layer exceeds the gate structure layer in the width direction and an extension is formed in both layers of the gate structure. The gate structure includes two sidewalls 105 and a gate 103 therein, the sidewalls 105 being of a low-k material selected from silicon oxide (SiO)₂) Silicon oxyfluoride (SiOF), silicon oxyfluoride containing carbon (SiOCH), hydrogen silsesquioxane (HSSQ), methyl silsesquioxaneSilicon oxide (MSSQ), organic polymer, inorganic polymer, or TEOS, and stacked structures thereof, in this embodiment, silicon oxide is used as the low-k material, and polysilicon is used as the gate 103.

Further, the channel layer and the widened portion of the high-k gate dielectric layer on both sides of the gate structure are covered with a source 106 and a drain 107, respectively, wherein the source 106 and the drain 107 may be selected from titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), and the like, or a combination of different types of stacked layers of the above metals. An interlevel dielectric layer 109 is formed between the transistors and further has tungsten plugs 108 on the source 106 and drain 107 to make electrical contact with the metal interconnect layer.

According to the semiconductor transistor structure, the width of a high-k gate dielectric between a gate electrode of the transistor and a semiconductor channel is extended by adjusting the thickness of the low-k side wall between the gate electrode of the transistor and a source-drain electrode, a channel region partially regulated and controlled by a drain electrode is increased, and the width of a potential barrier between drain electrode bands is further increased, so that the problem of static power consumption caused by off-state tunneling current can be solved.

A method of fabricating the above-described semiconductor transistor using a front gate process is described with reference to fig. 3-9.

Fig. 3 is a flow chart of the fabrication of the transistor using the gate-last process, first providing a quartz substrate 100, forming a carbon nanotube channel layer 101 thereon, and further depositing a gate dielectric oxide layer 102 with a thickness less than 5 nm or more thereon, as shown in fig. 4, according to step S1. In further embodiments, the substrate 101 may be selected from a hard insulating material such as silicon oxide, glass, aluminum oxide, and the like, and a high temperature resistant flexible insulating material such as PET, PEN, polyimide, and the like, and the channel layer 101 may also be selected from other narrow bandgap channel materials including graphene, two-dimensional materials such as molybdenum disulfide, black phosphorus, and the like.

Further according to step S2, a polysilicon gate 103 is formed on the oxide layer 102, and the polysilicon gate 103 may be prepared by conventional photolithography masking and deposition processes, as shown in fig. 5. A silicon oxide layer 104 is then deposited on the resulting structure by a PECVD process, the silicon oxide layer 104 covering the oxide layer 102 and the sidewalls and top of the polysilicon gate 103, as shown in fig. 6. In further embodiments, the gate 103 may also be selected from amorphous silicon or metal.

Further according to step S3, the silicon oxide layer 104 is etched back by using a first etching gas to form a sidewall 105, and then the gate dielectric layer 102 is further etched and removed by using the pattern of the sidewall 105 as a mask to form a gate structure with a first width W1, as shown in fig. 7. Chlorine-based, bromine-based or fluorine-based etching gases are used in the first etching gas. Further according to step S4, the etching conditions are changed, and a second etching gas containing fluorine radicals is used to further etch back the sidewall spacers 105, so as to maintain the selectivity of the gate dielectric layer 102 and prevent the gate dielectric layer from being etched, thereby forming a gate structure with a second width W2, as shown in fig. 8. Since the first width W1 is greater than the second width W2, the gate dielectric layer 102 extends beyond the gate structure in the width direction. In another embodiment, the gate structure with the first width W1 may be formed in one step without further etching back in step S4, and the second width W2 is equal to the first width W1, so that the energy band of the device is optimized through the sidewall 105.

Further according to step S5, a source metal layer 106 and a drain metal layer 107 are deposited on the structure obtained in step S4, then a silicon nitride interlayer dielectric layer 109 is deposited between the transistors to isolate the transistors, then an interconnection via corresponding to the source and drain electrodes is formed by conventional masking and etching processes, and then a tungsten plug 108 is deposited in the interconnection via to be electrically connected with the upper metal interconnection layer. In another embodiment, after step S4, an interlayer dielectric layer 109 may be deposited, and then a via hole may be formed, in which the source metal layer 106, the drain metal layer 107 and the tungsten plug are sequentially deposited, so as to be electrically connected to the upper metal interconnection layer.

In another embodiment, a semiconductor transistor of the present invention can be fabricated using a gate-last process, which is illustrated in fig. 10 and described in detail below with reference to fig. 11-16.

First, according to step S1, a quartz substrate 200 is provided, a carbon nanotube channel layer 201 is formed thereon, and a first high-k gate dielectric layer 202 with an optimized thickness of less than 5 nm or less is further deposited thereon, and then, according to step S2, a polysilicon dummy gate 203 is formed on the first high-k gate dielectric layer 202, the polysilicon dummy gate 203 can be prepared by a conventional photolithography mask and deposition process, and then a silicon oxide layer 204 is deposited on the obtained structure by a PECVD process, the silicon oxide layer 204 covering the oxide layer 202 and the sidewalls and top of the polysilicon dummy gate 203, as shown in fig. 11. In further embodiments, the substrate 201 may be selected from a hard insulating material such as silicon oxide, glass, aluminum oxide, and the like, and a high temperature resistant flexible insulating material such as PET, PEN, polyimide, and the like, and the channel layer 201 may also be selected from other narrow bandgap channel materials including graphene, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, black phosphorus, and the like.

Further according to step S3, the silicon oxide layer 204 is etched back by using a first etching gas to form a sidewall 205, and then the first high-k gate dielectric layer 202 is further etched and removed by using the sidewall 205 pattern as a mask to form a dummy gate structure with a first width W1, as shown in fig. 12. Chlorine-based, bromine-based or fluorine-based etching gases are used in the first etching gas. Further according to step S4, the etching conditions are changed, and a second etching gas containing fluorine radicals is used to further etch back the sidewall spacers 205, where the second etching gas has selectivity to the first high-k gate dielectric layer 202, so that the first high-k gate dielectric layer is not etched, thereby forming a dummy gate structure with a second width W2, as shown in fig. 13. Because the first width W1 is greater than the second width W2, the first high-k gate dielectric layer 202 extends beyond the dummy gate structure in the width direction. In another embodiment, the gate structure with the first width W1 may be formed in one step without further etching back in step S4, and the second width W2 is equal to the first width W1, so that the energy band of the device is optimized through the sidewall 105.

Further according to step S5, a source metal layer 206 and a drain metal layer 207 are deposited on the structure obtained in step S4, then a silicon nitride interlayer dielectric layer 209 is deposited between the transistors to isolate the transistors, then an interconnection via corresponding to the source and drain electrodes is formed by conventional masking and etching processes, then a tungsten plug 208 is deposited in the interconnection via, and then the above structure is planarized by Chemical Mechanical Polishing (CMP) to expose the dummy gate 203. Then, a dummy gate pattern is defined, the dummy gate 203 is removed, and the first high-k gate dielectric layer 202 under the dummy gate 203 is etched and removed, so as to form a through hole between the sidewalls 205, as shown in fig. 15.

Further according to step S6, a second high-k gate dielectric layer 210 is deposited in the through hole formed in the above step to cover the bottom carbon nanotube channel layer and the sidewall, and a metal gate 211 is further deposited therein. The second high-k gate dielectric layer 210 may also be made of a different material than the first high-k gate dielectric layer. In another embodiment, the metal gate 211 may be deposited directly after removing the dummy gate 203 without removing the first high-k gate dielectric layer 202 thereunder.

According to the invention, the width of a high-k gate dielectric between the gate electrode of the transistor and a semiconductor channel is extended by adjusting the thickness of the low-k side wall between the gate electrode of the transistor and the source-drain electrode, so that a part of channel region regulated and controlled by the drain electrode is increased, and the width of a barrier between drain end bands is further increased. The semiconductor transistor provided by the invention can solve the problem of static power consumption caused by off-state tunneling current, is compatible with the conventional silicon integrated circuit process, and can be prepared in a large-scale integrated manner.

Although the invention has been described in detail hereinabove with respect to specific embodiments thereof, it will be apparent to those skilled in the art that modifications and improvements can be made thereto without departing from the scope of the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims (10)

1. A semiconductor transistor comprising a substrate (100) having a semiconductor channel layer (101) on the substrate (100), a high-k gate dielectric layer (102) having a first width W1 on the semiconductor channel layer (101), and a gate structure having a second width W2 thereon, the gate structure comprising two sidewalls and a gate electrode (103) located therein, wherein:

the first width W1 is equal to or greater than the second width W2, with a source (106) and a drain (107) on either side of the gate structure.

2. The semiconductor transistor of claim 1, wherein said semiconducting channel layer (101) is a narrow bandgap semiconducting material, which may be selected from carbon nanotubes, graphene, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, black phosphorus, or various combinations of these materials on the same plane or different stacks.

3. The semiconductor transistor of claim 1, having tungsten plugs (108) on the source (106) and drain (107) for metal interconnects.

4. The semiconductor transistor according to claim 1, wherein the substrate (100) is selected from the group consisting of hard insulating materials such as silicon oxide, quartz, glass, aluminum oxide, and high temperature resistant flexible insulating materials such as PET, PEN, polyimide.

5. The semiconductor transistor of claim 1, wherein the source (106) and drain (107) are selected from titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), and the like, or a combination of different types of stacked layers of the above metals.

6. The semiconductor transistor of claim 1, wherein said high-k gate dielectric layer (102) is selected from hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, lanthanum oxide, titanium oxide, or different types of stacked structures or ternary compound structures of the above oxides.

7. A method of manufacturing a semiconductor transistor according to claims 1-6, comprising the steps of:

s1, providing a substrate (100), forming a semiconductor channel layer (101) thereon, and further depositing a high-k gate dielectric layer (102) thereon;

s2, forming a gate (103) on the high-k gate dielectric layer (102), and depositing a low-k dielectric layer (104) on the obtained structure, wherein the low-k dielectric layer (104) covers the high-k gate dielectric layer (102) and the side wall and the top of the gate electrode (103);

s3, carrying out back etching on the low-k dielectric layer (104) by adopting first etching gas to form a side wall (105), and further carrying out etching removal on the high-k gate dielectric layer (102) by taking the side wall (105) as a mask to form a gate structure with a first width W1;

s4, further etching the side wall (105) by using second etching gas, and simultaneously keeping the high-k gate dielectric layer (102) from being etched to form a gate structure with a second width W2;

and S5, depositing source and drain metal layers (106 and 107) on the structure obtained in the step S4 to form a final transistor structure.

8. The method of manufacturing a semiconductor transistor according to claim 7, further comprising forming a tungsten plug (108) and an interlayer dielectric layer (109) on the source and drain metal layers (106, 107), wherein the tungsten plug (108) is formed by first depositing the source and drain metal layers, then patterning the source and drain metal layers, then depositing the interlayer dielectric layer, and forming a via hole corresponding to the source and drain metal layers, and forming the tungsten plug in the via hole, or by first forming an interlayer dielectric layer, then forming the via hole, and then simultaneously depositing the source and drain metal layers and the tungsten plug in the via hole.

9. The method for manufacturing a semiconductor transistor according to claim 7, wherein a chlorine-based, bromine-based, or fluorine-based etching gas is used as the first etching gas, and a fluorine-based etching gas is used as the second etching gas.

10. The method of claim 7, wherein said semiconductor channel layer is a narrow bandgap semiconductor material selected from the group consisting of carbon nanotubes, graphene, two dimensional materials such as molybdenum disulfide, and black phosphorus.

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