CN107808899B - Lateral power device with mixed conduction mode and preparation method thereof - Google Patents

Lateral power device with mixed conduction mode and preparation method thereof Download PDF

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CN107808899B
CN107808899B CN201711026475.8A CN201711026475A CN107808899B CN 107808899 B CN107808899 B CN 107808899B CN 201711026475 A CN201711026475 A CN 201711026475A CN 107808899 B CN107808899 B CN 107808899B
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region
strips
drift region
layer
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CN107808899A (en
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张金平
崔晓楠
刘竞秀
李泽宏
任敏
张波
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University of Electronic Science and Technology of China
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    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract

The invention provides a transverse power device with a mixed conduction mode and a preparation method thereof, and the transverse power device comprises a P-type substrate, a buried oxide layer, an N-type drift region, a P-type base region, an N-type buffer region, an N-type source region, a P-type contact region, a P-type collector region, an emitter, a collector, a gate dielectric layer and a gate electrode, wherein N-type strips and P-type strips are arranged on the surface of the N-type drift region at intervals in a direction perpendicular to the length direction of a channel on the surface of the drift region of the device, and a P-type RESURF layer is arranged in the drift region below the N-type strips and the P-type strips; a medium groove structure is arranged among the N-type strip, the P-type strip and the P-type RESURF layer and the N-type buffer area; the concentration of the N-type strips and the concentration of the P-type strips are greater than that of the N-type drift region; the depth of the dielectric groove structure is not less than the depth of the N-type strip, the P-type strip and the P-type collector region; the invention realizes the mixed conduction of the surface SJ-LDMOS and the LIGBT, can obtain lower conduction voltage drop, higher voltage resistance, higher switching speed and lower turn-off loss, eliminates snapback effect and greatly improves the performance of the device.

Description

Lateral power device with mixed conduction mode and preparation method thereof
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a transverse power semiconductor device with a mixed conduction mode and a preparation method thereof.
Background
A Lateral Insulated Gate Bipolar Transistor (LIGBT) is a Lateral power device that combines the advantages of a Lateral power MOSFET and a Bipolar Transistor, has the characteristics of high input impedance and low on-state voltage drop, and is widely used in various power integrated circuits. Compared with the traditional device based on the bulk silicon technology, the device manufactured by adopting the SOI technology has the advantages of high speed, low power consumption, high integration density, strong latch-up resistance, low cost, good irradiation resistance and the like. Therefore, the LIGBT device based on the SOI material also has the advantages of good insulating property, low substrate leakage current, small parasitic capacitance, high integration level and the like, and the manufacturing process of the LIGBT device is compatible with the SOI-CMOS process and is easy to realize, so the LIGBT device becomes one of the core components of the power integrated circuit. When the LIGBT device is switched on, low on-state voltage drop can be obtained due to the conductance modulation effect in the drift region, but when the LIGBT device is switched off, the switching-off time is long and the switching-off loss is large due to the existence of a large number of non-equilibrium carriers stored in the drift region. Meanwhile, due to the existence of the PN junction in the collector region of the device, when the device is conducted in the forward direction, the conducted voltage drop of the LIGBT is larger than that of the LDMOS device in the low collector voltage region under the same current density, and the loss characteristic of the device is not reduced favorably.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a lateral power semiconductor device with mixed conduction modes and a method for manufacturing the same.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a transverse power device with a mixed conduction mode comprises a P-type substrate 1, a buried oxide layer 2 and an N-type drift region 3 which are sequentially arranged from bottom to top; one end inside the N-type drift region 3 is provided with a P-type base region 4, and the other end is provided with an N-type buffer region 8; an N-type source region 5 and a P-type contact region 6 are arranged above the inside of the P-type base region 4, and a P-type collector region 9 is arranged above the inside of the N-type buffer region 8; an emitter 10 is arranged above the P-type contact region 6 and part of the N-type source region 5; the upper surface of part of the P type collector region 9 is provided with a collector 12; a gate dielectric layer 7 is further arranged above the P-type base region 4, a gate electrode 11 is arranged above the gate dielectric layer 7, the length of a gate structure formed by the gate dielectric layer 7 and the gate electrode 11 is larger than the length of the surface of the P-type base region 4, and two ends of the gate structure are respectively contacted with the upper surface of the N-type source region 5 and the upper surface of the N-type drift region 3; the surface of the N-type drift region 3 is provided with N-type strips 13 and P-type strips 14, the N-type strips 13 and the P-type strips 14 are alternately arranged on the surface of the drift region of the device in a direction vertical to the length direction of a channel, and a P-type RESURF layer 16 is arranged in the drift region below the N-type strips 13 and the P-type strips 14; a dielectric groove structure 17 is arranged between the N-type strip 13, the P-type strip 14 and the P-type RESURF layer 16 and the N-type buffer region 8; the upper surface of the N-shaped strip 13 on the side close to the dielectric groove structure 17 is provided with an electrode 15, and the electrode 15 is connected with the collector 12; the concentration of the N-type strips 13 and the P-type strips 14 is greater than that of the N-type drift region 3; the depth of the dielectric trench structure 17 is not less than the depth of the N-type stripes 13, the P-type stripes 14 and the P-type collector region 9.
Compared with the traditional LIGBT structure shown in figure 1, the invention introduces the high-concentration N/P strips 3-dimensional structure which are arranged alternately on the surface of the drift region of the device and is vertical to the length direction (Z direction) of the channel, and introduces the P-type RESURF layer below the drift region, when the device is conducted in the forward direction, the mixed conduction of the surface SJ-LDMOS and the LIGBT is realized, and simultaneously, the 3-dimensional RESURF action of the surface N/P strips and the P-type RESURF layer is utilized to improve the breakdown voltage of the device, the three-dimensional expansion of the depletion layer is utilized to improve the turn-off speed of the device, and the turn-off loss of the device is reduced. In the structure, along with the increase of the voltage of a collector in the forward conduction process, the snapback effect of the conventional RC-IGBT can not occur due to the isolation effect of the dielectric trench structure and the P-type RESURF layer in the process of transition from the SJ-LDMOS conduction mechanism to the SJ-LDMOS and LIGBT mixed conduction mechanism. In addition, the manufacturing process of the invention is compatible with the traditional LIGBT process, and the manufacturing difficulty is not increased.
Preferably, none of the P-type RESURF layer 16, the N-type stripe 13 and the P-type stripe 14 is in contact with the P-type base region 4, and the concentration of the N-type stripe 13 and the concentration of the P-type stripe 14 are not less than the concentration of the P-type RESURF layer 16.
Preferably, an N-type layer 18 is further provided between the P-type RESURF layer 16 and both the N- type strips 13 and 14, and the concentration of the N-type layer 18 is greater than that of the N-type drift region 3.
Preferably, the P-type RESURF layer 16 is composed of a first sub-region 161, a second sub-region 162, and a third sub-region 163, which are sequentially decreased in concentration from left to right.
Preferably, the N-type drift region 3 is composed of a first doped region 31 and a second doped region 32, the concentration of which increases from left to right.
Preferably, the width of the N-type strips 13 gradually increases from left to right, and the width of the P-type strips 14 gradually decreases from left to right; or the concentration of the N-type stripes 13 gradually increases from left to right and the concentration of the P-type stripes 14 gradually decreases from left to right.
Preferably, the MOS structure of the device is a trench type structure.
Preferably, the MOS structure of the device is a double-gate composite structure formed by a planar structure and a groove-type structure.
Preferably, the dielectric trench structure 17 is in direct contact with the P type collector region 9, the N type buffer region 8 is only under the P type collector region 9, and the depth of the dielectric trench structure 17 is greater than the depth of the P type RESURF layer 16 and the N type buffer region 8.
In order to achieve the above object, the present invention further provides a method for manufacturing the lateral power device with mixed conduction mode, including the following steps:
the first step is as follows: selecting a silicon-on-insulator material, wherein the thickness of the substrate is 300-500 microns, and the doping concentration is 1014～1015Per cm3The thickness of the buried oxide layer on the substrate is 0.5-3 microns, and the thickness of the SOI layer is 5-20 microns;
the second step is that: photoetching, implanting N-type impurities into the right area of the surface of the silicon wafer through ions, and annealing to manufacture an N-type buffer region 8, wherein the thickness of the formed N-type buffer region 8 is 2-4 microns;
the third step: thermally oxidizing the surface of the silicon wafer, depositing a gate electrode material, photoetching, and etching part of the gate electrode material and the gate oxide layer to form a gate electrode;
the fourth step: photoetching, injecting a P-type impurity into the left side of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture a P-type base region, wherein the thickness of the formed P-type base region is 2-3 microns;
the fifth step: photoetching, injecting P-type impurities into the middle of a drift region on the surface of the silicon wafer through high-energy ions to form a P-type RESURF layer;
and a sixth step: photoetching, implanting N-type impurities into the middle of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture N regions, wherein the width of the formed N regions is 0.5-1 micron;
the seventh step: photoetching, implanting P-type impurities in the middle of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture a P-strip region, wherein the width of the formed P-strip region is 0.5-1 micron;
eighth step: photoetching, etching and filling a medium to form a medium groove, wherein the depth of the formed medium groove is not less than that of the P-type collector region;
the ninth step: photoetching, respectively implanting N-type impurities and P-type impurities into the left side area of the surface of the silicon wafer through ions, and annealing to manufacture an N-type source area and a P-type contact area, wherein the thickness of the formed N-type source area and the P-type contact area is about 0.2-0.3 micrometer;
the tenth step: photoetching, implanting P-type impurities into the right side area of the surface of the silicon wafer through ions, and annealing to manufacture a P-type collector region, wherein the thickness of the formed P-type collector region is 0.3-0.5 microns;
the eleventh step: depositing, photoetching and etching the dielectric layer to form a dielectric layer;
the twelfth step: depositing, photoetching and etching metal to form a metal emitter and a metal collector on the surface of the device; namely, the transverse power device with the mixed conduction mode is prepared.
The invention has the beneficial effects that: the invention introduces alternately arranged high-concentration N/P strip 3-dimensional structures on the surface of a drift region of a device in a direction vertical to the length direction of a channel, introduces a P-type RESURF layer below the high-concentration N/P strip 3-dimensional structures, and separates the N-P strip 3-dimensional structures from an N-buffer region and a P-type collector region through a dielectric trench structure. When the device is in a blocking state, the breakdown voltage of the device is improved by utilizing the 3-dimensional RESURF action of the surface N/P strip and the P-type RESURF layer, and meanwhile, the doping concentrations of the surface N/P strip, the P-type RESURF layer and the N-type drift region are improved; when the device is conducted in the forward direction, when the voltage of a collector is lower, a super-junction MOS structure formed by a high-concentration N/P3-dimensional structure on the surface is conducted, due to the high N-strip concentration, the conducting resistance of the device is small, when the voltage of the collector reaches and exceeds 0.7V, the LIGBT and the super-junction MOS structure are conducted simultaneously, large conducting current is achieved under certain voltage of the collector, due to the shielding effect of a dielectric groove structure and a P-type RESURF layer, the conducting characteristic of the LIGBT cannot be influenced due to the existence of the super-junction MOS structure, and the snapback effect of a conventional RC-IGBT cannot occur; when the device is turned off, due to the three-dimensional expansion of the depletion layer of the surface N/P strip and the P-type RESURF layer, the turn-off speed of the device is improved, and the turn-off loss of the device is reduced; meanwhile, the super junction MOS structure is integrated, so that the super junction MOS structure has a reverse conducting function. Therefore, compared with the traditional SOI-LIGBT, the surface SJ-LDMOS and LIGBT hybrid conduction device realizes hybrid conduction of the surface SJ-LDMOS and the surface LIGBT, can obtain lower conduction voltage drop, higher voltage resistance, higher switching speed and lower turn-off loss, eliminates the snapback effect, and greatly improves the performance of the device.
Drawings
FIG. 1 is a schematic diagram of a conventional SOI-LIGBT cell structure.
Fig. 2 is a schematic diagram of a lateral power device cell structure with a mixed conduction mode in embodiment 1 of the present invention.
Fig. 3 is an interface view of the lateral power device cell structure with mixed conduction mode along the AA' line in embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of a lateral power device cell structure with a mixed conduction mode in embodiment 2 of the present invention.
Fig. 5 is an interface view of the lateral power device cell structure with mixed conduction mode along the AA' line in embodiment 2 of the present invention.
Fig. 6 is a schematic diagram of a lateral power device cell structure with a mixed conduction mode according to embodiment 3 of the present invention.
Fig. 7 is a schematic diagram of a lateral power device cell structure with a mixed conduction mode in embodiment 4 of the present invention.
Fig. 8 is a schematic diagram of a lateral power device cell structure having a mixed conduction mode according to embodiment 5 of the present invention.
Fig. 9 is a schematic diagram of a lateral power device cell structure having a mixed conduction mode according to embodiment 6 of the present invention.
The semiconductor device comprises a substrate 1, a buried oxide layer 2, an N-type drift region 3, a P-type base region 4, an N + source region 5, a P + contact region 6, a gate dielectric layer 7, an N-type buffer region 8, a P-type collector region 9, a gate electrode 10, a gate electrode 11, a collector electrode 12, an N-type strip 13, a P-type strip 14, an electrode 15, a P-type RESURF layer 16, a dielectric groove structure 17, an N-type layer 18, a P-type RESURF layer first sub-region 161, a P-type RESURF layer second sub-region 162, a P-type RESURF layer third sub-region 163, an N-type drift region first doping region 31 and an N-type drift region first doping region 32.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
A lateral power device with a mixed conduction mode is disclosed, a cellular structure and a cross-sectional view along an AA' line are respectively shown in fig. 2 and fig. 3, and the lateral power device comprises a P-type substrate 1, a buried oxide layer 2 and an N-type drift region 3 which are sequentially arranged from bottom to top; one end inside the N-type drift region 3 is provided with a P-type base region 4, and the other end is provided with an N-type buffer region 8; an N-type source region 5 and a P-type contact region 6 are arranged above the inside of the P-type base region 4, and a P-type collector region 9 is arranged above the inside of the N-type buffer region 8; an emitter 10 is arranged above the P-type contact region 6 and part of the N-type source region 5; the upper surface of part of the P type collector region 9 is provided with a collector 12; a gate dielectric layer 7 is further arranged above the P-type base region 4, a gate electrode 11 is arranged above the gate dielectric layer 7, the length of a gate structure formed by the gate dielectric layer 7 and the gate electrode 11 is larger than the length of the surface of the P-type base region 4, and two ends of the gate structure are respectively contacted with the upper surface of the N-type source region 5 and the upper surface of the N-type drift region 3; the surface of the N-type drift region 3 is provided with N-type strips 13 and P-type strips 14, the N-type strips 13 and the P-type strips 14 are alternately arranged on the surface of the drift region of the device in a direction vertical to the length direction of a channel, and a P-type RESURF layer 16 is arranged in the drift region below the N-type strips 13 and the P-type strips 14; a dielectric groove structure 17 is arranged between the N-type strip 13, the P-type strip 14 and the P-type RESURF layer 16 and the N-type buffer region 8; the upper surface of the N-shaped strip 13 on the side close to the dielectric groove structure 17 is provided with an electrode 15, and the electrode 15 is connected with the collector 12; the concentration of the N-type strips 13 and the P-type strips 14 is greater than that of the N-type drift region 3; the depth of the dielectric trench structure 17 is not less than the depth of the N-type stripes 13, the P-type stripes 14 and the P-type collector region 9. The thickness of the N-type drift region 3 is 5-20 microns; the depth of the P-type RESURF layer from the surface is 1-4 microns, and the thickness is 0.5-2 microns; the width of the N-shaped strips 13 and the width of the P-shaped strips 14 are 0.5-1 micron; the distance between the P-type RESURF layer 16, the N-type strips 13 and the P-type strips 14 and the P-type base region 4 is 0.5-5 microns.
The working principle of the embodiment is as follows:
in the blocking state: when the collector is positively biased and the emitter and the gate are at zero potential, the device is in a blocking mode of operation. The surface N/P strips, the P-type RESURF layer and the N-type drift region are fully depleted before the device breaks down by utilizing the 3-dimensional RESURF action of the surface N/P strips and the P-type RESURF layer, so that the electric field of the drift region is optimized, higher voltage resistance of the device is obtained under a certain drift region length, and the doping concentrations of the surface N/P strips, the P-type RESURF layer and the N-type drift region are improved. Meanwhile, due to the MOS structure introduced into the surface, the gain of a P-type collector region/N-type drift region/P-type base region parasitic PNP transistor is reduced, and the breakdown voltage of the device is further improved.
In a forward conduction state: the emitter is connected with zero potential, when the voltage applied to the grid is greater than the threshold voltage of the device, the semiconductor on the surface of the P-type base region below the grid is inverted, the channel of the device is conducted, the collector is positively biased, and at the moment, the transverse super-junction MOSFET formed by the high-concentration N/P3-dimensional structures on the left surface of the dielectric trench 17 is conducted. When the voltage applied to the collector is greater than the turn-on voltage of the PN junction, the P-type collector region 9 injects holes into the N-type drift region 3, and at the moment, the LIGBT structure starts to be conducted, and a conductivity modulation effect is formed in the N-type drift region 3. At the moment, the LIGBT and the super-junction MOS structure are conducted simultaneously, large conducting current is achieved under a certain collector voltage, the conducting characteristic of the LIGBT cannot be influenced due to the shielding effect of the medium groove structure and the P-type RESURF layer, and the snapback effect of the conventional RC-IGBT cannot occur.
In the off state: the device begins to turn off when the gate voltage begins to decrease from the voltage at which it turned on in the forward direction. Because the SJ-MOSFET structure and the LIGBT structure can be simultaneously conducted when the device is conducted in the forward direction, holes stored in the drift region are reduced in the conducting state, the turn-off is quicker, and the turn-off loss is smaller; and due to the three-dimensional expansion of the depletion layer of the surface N/P strip and the P-type RESURF layer, the depletion of the drift region is accelerated, so that the extraction speed of current carriers is higher, the turn-off performance of the device is more excellent, the turn-off speed of the device is further improved, and the turn-off loss of the device is reduced.
Reverse conduction state: due to the formation of the surface SJ-MOSFET structure, when an emitter is connected with a high potential and a collector is connected with a low potential, a body diode of the surface SJ-MOSFET structure starts to be conducted, reverse conduction can be realized, and a reverse conduction function is realized.
Therefore, compared with the traditional SOI-LIGBT, the surface SJ-LDMOS and LIGBT hybrid conduction device realizes hybrid conduction of the surface SJ-LDMOS and the surface LIGBT, can obtain lower conduction voltage drop, higher voltage resistance, higher switching speed and lower turn-off loss, eliminates the snapback effect, and greatly improves the performance of the device.
The P-type RESURF layer 16, the N-type strips 13 and the P-type strips 14 are not in contact with the P-type base region 4, and the concentration of the N-type strips 13 and the concentration of the P-type strips 14 are not less than that of the P-type RESURF layer 16.
Example 2
As shown in fig. 4 and 5, this example differs from embodiment 1 in that an N-type layer 18 is further provided between both the N-type strips 13 and the P-type strips 14 and the P-type RESURF layer 16, and the concentration of the N-type layer 18 is greater than that of the N-type drift region 3. This embodiment can further improve the current conducting capability of the lateral MOSFET compared to embodiment 1.
Example 3
As shown in fig. 6, this example is different from embodiment 1 in that the P-type RESURF layer 16 is composed of a first sub-region 161, a second sub-region 162, and a third sub-region 163 whose concentrations decrease in this order from left to right. This embodiment can further improve the breakdown voltage of the device as compared with embodiment 1.
Example 4
As shown in fig. 7, this example is different from embodiment 3 in that the N-type drift region 3 is composed of a first doped region 31 and a second doped region 32 whose concentration increases from left to right in sequence. Compared with embodiment 3, the present embodiment can further improve the breakdown voltage of the device, and improve the turn-off speed of the device, reducing the turn-off loss.
Example 5
As shown in fig. 8, this example is different from embodiment 4 in that the MOS structure of the device is a trench type structure. This embodiment can further reduce the on-voltage drop of the device as compared with embodiment 4. In this embodiment, a dual-gate composite structure composed of a planar MOS structure and a trench MOS structure may also be used.
Example 6
As shown in fig. 9, this example is different from embodiment 5 in that the dielectric trench structure 17 is in direct contact with the P type collector region 9, the N type buffer region 8 is only under the P type collector region 9, and the depth of the dielectric trench structure 17 is larger than the depth of the P type RESURF layer 16 and the N type buffer region 8. This embodiment can further reduce the area of the device as compared with embodiment 5.
Example 7
The method for manufacturing the lateral power device with the mixed conduction mode in the 6 embodiments includes the following steps:
the first step is as follows: selecting a silicon-on-insulator material, wherein the thickness of the substrate is 300-500 microns, and the doping concentration is 1014～1015Per cm3The thickness of the buried oxide layer on the substrate is 0.5-3 microns, and the thickness of the SOI layer is 5-20 microns;
the second step is that: photoetching, implanting N-type impurities into the right area of the surface of the silicon wafer through ions, and annealing to manufacture an N-type buffer region 8, wherein the thickness of the formed N-type buffer region 8 is 2-4 microns;
the third step: thermally oxidizing the surface of the silicon wafer, depositing a gate electrode material, photoetching, and etching part of the gate electrode material and the gate oxide layer to form a gate electrode;
the fourth step: photoetching, injecting a P-type impurity into the left side of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture a P-type base region, wherein the thickness of the formed P-type base region is 2-3 microns;
the fifth step: photoetching, injecting P-type impurities into the middle of a drift region on the surface of the silicon wafer through high-energy ions to form a P-type RESURF layer;
and a sixth step: photoetching, implanting N-type impurities into the middle of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture N regions, wherein the width of the formed N regions is 0.5-1 micron;
the seventh step: photoetching, implanting P-type impurities in the middle of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture a P-strip region, wherein the width of the formed P-strip region is 0.5-1 micron;
eighth step: photoetching, etching and filling a medium to form a medium groove 17, wherein the depth of the formed medium groove is not less than that of the P-type collector region;
the ninth step: photoetching, respectively implanting N-type impurities and P-type impurities into the left side area of the surface of the silicon wafer through ions, and annealing to manufacture an N-type source area and a P-type contact area, wherein the thickness of the formed N-type source area and the P-type contact area is about 0.2-0.3 micrometer;
the tenth step: photoetching, implanting P-type impurities into the right side area of the surface of the silicon wafer through ions, and annealing to manufacture a P-type collector region, wherein the thickness of the formed P-type collector region is 0.3-0.5 microns;
the eleventh step: depositing, photoetching and etching the dielectric layer to form a dielectric layer;
the twelfth step: depositing, photoetching and etching metal to form a metal emitter and a metal collector at proper positions on the surface of the device; namely, the transverse power device with the mixed conduction mode is prepared.
Furthermore, as a preferable mode, the width of the N-type strips 13 gradually increases from left to right, and the width of the corresponding P-type strips 14 gradually decreases from left to right; or the concentration of the N-type stripes 13 gradually increases from left to right and the concentration of the P-type stripes 14 gradually decreases from left to right.
Need to claimThe method is as follows: the technical scheme of the invention is only explained by taking an N-channel device as an example, only the doping types of all the regions are required to be interchanged, and the invention is also suitable for a P-channel device. The dielectric material of the present invention is not limited to silicon dioxide, and also includes: silicon nitride (Si)3N4) Hafnium oxide (HfO)2) Aluminum oxide (Al)2O3) And the like. The semiconductor material can be silicon, and can also be wide bandgap materials such as silicon carbide, gallium nitride, diamond and the like. Meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. A transverse power device with a mixed conduction mode comprises a P-type substrate (1), a buried oxide layer (2) and an N-type drift region (3) which are arranged from bottom to top in sequence; one end inside the N-type drift region (3) is provided with a P-type base region (4), and the other end is provided with an N-type buffer region (8); an N-type source region (5) and a P-type contact region (6) are arranged above the inner part of the P-type base region (4), and a P-type collector region (9) is arranged above the inner part of the N-type buffer region (8); an emitter (10) is arranged above the P-type contact region (6) and part of the N-type source region (5); the upper surface of part of the P-type collector region (9) is provided with a collector (12); a gate dielectric layer (7) is further arranged above the P-type base region (4), a gate electrode (11) is arranged above the gate dielectric layer (7), the length of a gate structure formed by the gate dielectric layer (7) and the gate electrode (11) is larger than the length of the surface of the P-type base region (4), and two ends of the gate structure are respectively contacted with the upper surface of the N-type source region (5) and the upper surface of the N-type drift region (3); the method is characterized in that: the surface of the N-type drift region (3) is provided with N-type strips (13) and P-type strips (14), the N-type strips (13) and the P-type strips (14) are arranged at intervals on the surface of the drift region of the device perpendicular to the length direction of a channel, and a P-type RESURF layer (16) is arranged in the drift region below the N-type strips (13) and the P-type strips (14); a medium groove structure (17) is arranged among the N-type strip (13), the P-type strip (14) and the P-type RESURF layer (16) and the N-type buffer area (8); the upper surface of the N-shaped strip (13) close to one side of the dielectric groove structure (17) is provided with an electrode (15), and the electrode (15) is connected with the collector electrode (12); the concentration of the N-type strips (13) and the P-type strips (14) is greater than that of the N-type drift region (3); the depth of the dielectric groove structure (17) is not less than the depth of the N-type strip (13), the depth of the P-type strip (14) and the depth of the P-type collector region (9); an N-type layer (18) is arranged between the N-type strip (13) and the P-type strip (14) and the P-type RESURF layer (16), and the concentration of the N-type layer (18) is greater than that of the N-type drift region (3).
2. The lateral power device with mixed conduction modes as claimed in claim 1, wherein: the P-type RESURF layer (16), the N-type strips (13) and the P-type strips (14) are not in contact with the P-type base region (4), and the concentration of the N-type strips (13) and the concentration of the P-type strips (14) are not less than that of the P-type RESURF layer (16).
3. The lateral power device with mixed conduction modes as claimed in claim 1, wherein: the P-type RESURF layer (16) is composed of a first sub-region (161), a second sub-region (162) and a third sub-region (163) which are sequentially reduced in concentration from left to right.
4. The lateral power device with mixed conduction modes as claimed in claim 1, wherein: the N-type drift region (3) is composed of a first doped region (31) and a second doped region (32) of which the concentration is increased sequentially from left to right.
5. The lateral power device with mixed conduction modes as claimed in claim 1, wherein: the width of the N-shaped strips (13) is gradually increased from left to right, and the width of the P-shaped strips (14) is gradually decreased from left to right; or the concentration of the N-type strips (13) is gradually increased from left to right, and the concentration of the P-type strips (14) is gradually decreased from left to right.
6. The lateral power device with mixed conduction modes as claimed in claim 1, wherein: the MOS structure of the device is a trench type structure.
7. The lateral power device with mixed conduction modes as claimed in claim 1, wherein: the MOS structure of the device is a double-gate composite structure formed by a plane structure and a groove structure.
8. The lateral power device with mixed conduction modes as claimed in claim 1, wherein: the dielectric groove structure (17) is directly contacted with the P type collector region (9), the N type buffer region (8) is only arranged below the P type collector region (9), and the depth of the dielectric groove structure (17) is larger than the depth of the P type RESURF layer (16) and the N type buffer region (8).
9. A method of manufacturing a lateral power device with mixed conduction modes according to any of claims 1 to 8, characterized by the steps of:
the first step is as follows: selecting a silicon-on-insulator material, wherein the thickness of the substrate is 300-500 microns, and the doping concentration is 1014～1015Per cm3The thickness of the buried oxide layer on the substrate is 0.5-3 microns, and the thickness of the SOI layer is 5-20 microns;
the second step is that: photoetching, implanting N-type impurities into the right area of the surface of the silicon wafer through ions, and annealing to manufacture an N-type buffer area, wherein the thickness of the formed N-type buffer area is 2-4 microns;
the third step: thermally oxidizing the surface of the silicon wafer, depositing a gate electrode material, photoetching, and etching part of the gate electrode material and the gate oxide layer to form a gate electrode;
the fourth step: photoetching, injecting a P-type impurity into the left side of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture a P-type base region, wherein the thickness of the formed P-type base region is 2-3 microns;
the fifth step: photoetching, injecting P-type impurities into the middle of a drift region on the surface of the silicon wafer through high-energy ions to form a P-type RESURF layer;
and a sixth step: photoetching, implanting N-type impurities into the middle of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture N regions, wherein the width of the formed N regions is 0.5-1 micron;
the seventh step: photoetching, implanting P-type impurities in the middle of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture a P-strip region, wherein the width of the formed P-strip region is 0.5-1 micron;
eighth step: photoetching, etching and filling a medium to form a medium groove, wherein the depth of the formed medium groove is not less than that of the P-type collector region;
the ninth step: photoetching, respectively implanting N-type impurities and P-type impurities into the left side area of the surface of the silicon wafer through ions, and annealing to manufacture an N-type source area and a P-type contact area, wherein the thickness of the formed N-type source area and the P-type contact area is 0.2-0.3 micrometer;
the tenth step: photoetching, implanting P-type impurities into the right side area of the surface of the silicon wafer through ions, and annealing to manufacture a P-type collector region, wherein the thickness of the formed P-type collector region is 0.3-0.5 microns;
the eleventh step: depositing, photoetching and etching the dielectric layer to form a dielectric layer;
the twelfth step: depositing, photoetching and etching metal to form a metal emitter and a metal collector on the surface of the device; namely, the transverse power device with the mixed conduction mode is prepared.
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