CN110503921A

CN110503921A - Gate driving circuit and its driving method, display device

Info

Publication number: CN110503921A
Application number: CN201910881857.1A
Authority: CN
Inventors: 方浩博
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2019-09-18
Filing date: 2019-09-18
Publication date: 2019-11-26
Anticipated expiration: 2039-09-18
Also published as: CN110503921B

Abstract

This application discloses a kind of gate driving circuit and its driving methods, display device.The gate driving circuit includes two row sub-pixels for driving each pixel group, and a line sub-pixel is connect with the first grid line and the second grid line, the display panel that another row sub-pixel is connect with the second grid line and third grid line.The gate driving circuit includes the first shift register cell and the second shift register cell, and first the first grid line for being connected to the first pixel group of shift register cell and third grid line output gate drive signal period, the second shift register cell can persistently export gate drive signal to the second grid line that the first pixel group connects.The first shift register cell that the first pixel group is connect with the grid line that adjacent pixel group shares can export gate drive signal twice.The area for enabling the display device of certain volume that display panel is arranged is larger, so that the pixel that can be arranged in display panel is more, promotes the resolution ratio of display device.

Description

Gate driving circuit and its driving method, display device

Technical field

The present invention relates to field of display technology, in particular to a kind of gate driving circuit and its driving method, display device.

Background technique

With the progress of display technology, the display device of small volume, the wearable device for such as capableing of body-worn has There is display function.Also, in order to realize that broken colour is shown, display panel that the display device of the type (i.e. small volume) includes In each pixel can be divided into two sub-pixels, and the driving circuit that display device includes can respectively drive this two Sub-pixel for emitting light.

In the related technology, in order under the premise of promoting the display device cruising ability power consumption of display device (reduce), Realize reliable driving to two sub-pixels, it generally can be by being provided with two driving chips of a large amount of electronic components (Integrated Circuit, IC) is used as driving circuit, respectively drives the two sub-pixels.

But due to the finite volume of display device, driving IC needs to occupy the biggish space of the display device, accordingly , the space for causing the display device that display panel can be arranged reduces, and then the display panel for causing the display device to include In the pixel that can be arranged it is less, the resolution ratio of display device is lower.

Summary of the invention

The embodiment of the invention provides a kind of gate driving circuit and its driving methods, display device, can solve correlation The lower problem of the resolution ratio of display device in technology, the technical solution is as follows:

On the one hand, a kind of gate driving circuit is provided, for driving display panel, the display panel includes multiple pictures Plain group, each pixel group includes two row sub-pixels, and wherein a line sub-pixel is connect with the first grid line and the second grid line, another row Pixel is connect with second grid line and third grid line, and the adjacent rows sub-pixel in two neighboring pixel group shares an institute It states the first grid line or shares a third grid line；

The gate driving circuit includes: at least two cascade first shift register cells and at least two grades Connection the second shift register cell, cascade two first shift register cells respectively with first grid line It is connected with a third grid line, each second shift register cell is connect with second grid line, and each The grid line of shift register cell connection is different, and first shift register cell is used for the first grid line connected to it Or third grid line exports gate drive signal, the second grid line output that second shift register cell is used to be connected to it Gate drive signal；

Wherein, the first grid line and third the grid line output connected to the first pixel group in first shift register cell The period of gate drive signal, the second grid line output that second shift register cell is connected to the first pixel group Gate drive signal, and the second grid line output grid that second shift register cell is connected to the first pixel group drives The duration of dynamic signal, the first grid line and third grid connected greater than first shift register cell to the first pixel group The total duration of the gate drive signal of line output, the first pixel group are any one pixel group in the multiple pixel group；

The first shift register cell connecting with target grid line stops output gate drive signal target in object time After duration, continue to the target grid line export gate drive signal, the target grid line be the first pixel group with it is adjacent The shared grid line of pixel group, the object time is what second shift register cell was connected to the first pixel group At the time of second grid line stops output gate drive signal, the target duration is exported less than second shift register cell The duration of gate drive signal.

Optionally, first shift register cell includes: the first input module, the first pull-up control module, first Output module, the first pull-down control module and the first pull-down module；

First input module is connect with the first input signal end, the first power end and the first pull-up node respectively, institute Input signal of first input module for providing in response to first input signal end is stated, the first pull-up node of Xiang Suoshu is defeated Out from the first power supply signal of first power end；

The first pull-up control module is connect with first pull-up node and the first clock signal terminal respectively, and described the One pull-up control module is used for first in response to the current potential of first pull-up node and first clock signal terminal offer Clock signal controls the current potential of first pull-up node；

First output module is believed with first pull-up node, first clock signal terminal, the first control respectively Number end is connected with the first output end, and first output module is used for the current potential in response to first pull-up node and described the The first control signal that one control signal end provides, the first output end of Xiang Suoshu export first clock signal；

First pull-down control module respectively with first pull-up node, second source end, third power end and The connection of one pull-down node, first pull-down control module are used in response to the current potential of first pull-up node and described second The second source signal that power end provides, third power supply letter of the first pull-down node of Xiang Suoshu output from the third power end Number or the output second source signal；

First pull-down module respectively with second control signal end, initial signal end, the third power end, described One pull-down node, first pull-up node are connected with first output end, and first pull-down module is used in response to institute State the first pull-down node current potential and the initial signal end provide initial signal, the first pull-up node of Xiang Suoshu output described in Third power supply signal, and the second control signal for providing in response to the second control signal end, Xiang Suoshu first are defeated Outlet exports the third power supply signal, and the current potential of the second control signal is complementary with the current potential of the first control signal.

Optionally, first output module includes: output sub-module and output control submodule；

The output sub-module connects with first pull-up node, first clock signal terminal and output node respectively It connects, the output sub-module is used for the current potential in response to first pull-up node, Xiang Suoshu output node output described first Clock signal；

The output control submodule is exported with the output node, the first control signal end and described first respectively End connection, the output control submodule are used in response to the first control signal, described in the first output end of Xiang Suoshu exports Output sub-module is exported to the first clock signal of the output node；

First pull-down module is also connect with the 4th power end and the output node respectively, first pull-down module It is also used to the 4th power supply signal provided in response to the current potential of first pull-down node and the 4th power end, to described defeated Egress exports the third power supply signal.

Optionally, the output control submodule includes: output control transistor；

The grid of the output control transistor is connect with the first control signal end, the output control transistor First pole is connect with the output node, and the second pole of the output control transistor is connect with first output end.

Optionally, second shift register cell includes: the second input module, the second pull-up control module, second Output module, the second pull-down control module and the second pull-down module；

Second input module connects with the second input signal end, first power end and the second pull-up node respectively It connects, second input module is used for the input signal provided in response to second input signal end, and Xiang Suoshu second is pulled up Node exports first power supply signal；

The second pull-up control module is connect with second pull-up node and second clock signal end respectively, and described the Two pull-up control modules are used for second in response to the current potential of second pull-up node and second clock signal end offer Clock signal controls the current potential of second pull-up node；

Second output module respectively with second pull-up node, the second clock signal end and second output terminal Connection, second output module are used for the current potential in response to second pull-up node, and Xiang Suoshu second output terminal exports institute State second clock signal；

Second pull-down control module is electric with second pull-up node, the second source end, the third respectively Source is connected with the second pull-down node, second pull-down control module be used in response to second pull-up node current potential and The second source signal, the second pull-down node of Xiang Suoshu export the third power supply signal, alternatively, to the second drop-down section Point exports the second source signal；

Second pull-down module respectively with the 4th power end, the initial signal end, the third power end, institute State the second pull-down node, second pull-up node is connected with the second output terminal, second pull-down module is for responding Current potential and the initial signal in second pull-down node, the second pull-up node of Xiang Suoshu export the third power supply letter Number, and for the current potential in response to the 4th power supply signal and second pull-down node, Xiang Suoshu second output terminal is defeated The third power supply signal out.

Optionally, the first pull-up control module and the second pull-up control module include: pull-up control submodule Block and pull-up submodule；

The pull-up control submodule connects with target pull-up node, target control node and target clock signal end respectively It connects, the pull-up control submodule is used for the current potential in response to the target pull-up node, the output of Xiang Suoshu target control node Target clock signal from the target clock signal end, the pull-up submodule respectively with the target control node, institute It states target clock signal end to connect with the target pull-up node, the pull-up submodule is used in response to the target control section The current potential of point, Xiang Suoshu target pull-up node export the target clock signal, target pull-down module and the target control section Point connection, the target pull-down module are used for the current potential in response to target pull-down node, and Xiang Suoshu target control node exports institute State third power supply signal；

Alternatively, the pull-up control submodule respectively with the target pull-up node, first object control node and second Target control node connection, the pull-up control submodule is used for the current potential in response to the target pull-up node, described in control The on off operating mode of first object control node and the second target control node, the pull-up submodule respectively with the first object Control node, second target control node, target clock signal end are connected with the target pull-up node, the upper rock Module is used for the Xiang Suoshu target pull-up node output when the first object control node and the second target control node are connected Target clock signal from the target clock signal end, target pull-down module are connect with second target control node, The target pull-down module is used for the current potential in response to target pull-down node, the second target control node of Xiang Suoshu output described the Three power supply signals；

Wherein, the corresponding target pull-up node of first shift register cell is first pull-up node, target Control node is the first control node, and target clock signal end is first clock signal terminal, and target pull-down module is described First pull-down module, target pull-down node are first pull-down node, and first object control node is first object node, the Two target control nodes are the second destination node；

The corresponding target pull-up node of second shift register cell is second pull-up node, target control section Point is the second control node, and target clock signal end is the second clock signal end, under target pull-down module is described second Drawing-die block, target pull-down node are second pull-down node, and first object control node is third destination node, the second target Control node is the 4th destination node.

Optionally, the pull-up control submodule respectively with target pull-up node, target control node and target clock Signal end connection, the pull-up submodule respectively with the target control node, the target clock signal end and the target When pull-up node connects, the pull-up control submodule includes: pull-up control transistor, and the pull-up submodule includes: first It pulls up transistor, the grid of the pull-up control transistor is connect with the target pull-up node, and the pull-up controls transistor The first pole connect with the target clock signal end, it is described pull-up control transistor the second pole and the target control node Connection, the described first grid to pull up transistor connect with the target control node, described first pull up transistor first Pole is connect with the target clock signal end, and the described first the second pole to pull up transistor is connect with the target pull-up node；

The pull-up control submodule respectively with the target pull-up node, first object control node and the second target Control node connection, the pull-up submodule respectively with the first object control node, second target control node, mesh When mark clock signal terminal is connected with the target pull-up node, the pull-up submodule further include: second pulls up transistor, and institute State pull-up control transistor grid connect with the target pull-up node, it is described pull up control transistor the first pole with it is described Second pole of the connection of first object control node, the pull-up control transistor is connect with second target control node, institute The grid that first pulls up transistor is stated to connect with the first object control node, the described first the first pole to pull up transistor with Described second the second pole connection to pull up transistor, the described first the second pole to pull up transistor and the target pull-up node connect Connect, the described second grid to pull up transistor is connect with second target control node, described second pull up transistor One pole is connect with the target clock signal end.

Optionally, first input module includes: the first input transistors, and second input module includes: second Input transistors；

The grid of first input transistors is connect with first input signal end, second input transistors Grid is connect with second input signal end, and the first of first input transistors and second input transistors is extremely It being connect with first power end, the second pole of first input transistors is connect with first pull-up node, and described Second pole of two input transistors is connect with second pull-up node；

First pull-down control module includes: that the first drop-down control transistor and the second drop-down control transistor, described Second pull-down control module includes: third drop-down control transistor and the 4th drop-down control transistor；

The grid of the grid of the first drop-down control transistor and the first pole and third drop-down control transistor It is extremely connect with the second source end with first, the grid of the second drop-down control transistor and first pull-up node The grid of connection, the 4th drop-down control transistor is connect with second pull-up node, the first drop-down control crystal Second pole of pipe and second drop-down control the second of transistor and extremely connect with first pull-down node, under the third The second pole of control transistor and the second of the 4th drop-down control transistor is drawn extremely to connect with second pull-down node, The first of first pole of the second drop-down control transistor and the 4th drop-down control transistor extremely with third electricity Source connection；

First pull-down module includes: the first pull-down transistor, the second pull-down transistor, third pull-down transistor, Four pull-down transistors, the 5th pull-down transistor and the 6th pull-down transistor, second pull-down module include: the 7th lower crystal pulling Pipe, the 8th pull-down transistor, the 9th pull-down transistor, the tenth pull-down transistor and the 11st pull-down transistor；

The grid of first pull-down transistor, second pull-down transistor and the third pull-down transistor is and institute State the connection of the first pull-down node, the grid and the initial signal of the 4th pull-down transistor and the tenth pull-down transistor End connection, the grid of the 5th pull-down transistor connect with the second control signal end, the 6th pull-down transistor with The grid of 11st pull-down transistor is connect with the 4th power end, under the 7th pull-down transistor, the described 8th The grid of pull transistor and the 9th pull-down transistor is connect with second pull-down node, first pull-down transistor To first extremely being connect with the third power end for the 11st pull-down transistor, first pull-down transistor and described Second pole of the 4th pull-down transistor is connect with first pull-up node, the second pole of second pull-down transistor with it is described The connection of first control node, the second pole and the output node of the third pull-down transistor and the 6th pull-down transistor Connection, the second pole of the 5th pull-down transistor connect with first output end, the 7th pull-down transistor and described Second pole of the tenth pull-down transistor is connect with second pull-up node, the second pole of the 8th pull-down transistor with it is described The connection of second control node, the second pole of the 9th pull-down transistor and the 11st pull-down transistor and described second defeated Outlet connection；

First output module includes: the first output transistor, first capacitor device and output control transistor, and described Two output modules include: the second output transistor and the second capacitor；

The grid of first output transistor is connect with first pull-up node, and the of first output transistor One pole is connect with first clock signal terminal, and the second pole of first output transistor is connect with the output node, institute The one end for stating first capacitor device is connect with first pull-up node, and the other end is connect with the output node, the output control The grid of transistor processed is connect with the first control signal end, and the first pole of the output control transistor and the output save Point connection, the second pole of the output control transistor are connect with first output end, the grid of second output transistor Pole is connect with second pull-up node, and the first pole of second output transistor is connect with the second clock signal end, Second pole of second output transistor is connect with the second output terminal, one end of second capacitor and described second Pull-up node connection, the other end are connect with the second output terminal.

On the other hand, a kind of driving method of gate driving circuit is provided, for driving the grid as described in terms of above-mentioned Pole driving circuit, which comprises

The first grid line or third grid line that at least two cascade first shift register cells are successively connected to it are defeated Gate drive signal out, the second grid line that at least two cascade second shift register cells are successively connected to it export grid Pole driving signal；

Wherein, the first grid line and third the grid line output connected to the first pixel group in first shift register cell The period of gate drive signal, the second grid line output that second shift register cell is connected to the first pixel group Gate drive signal, and the second grid line output grid that second shift register cell is connected to the first pixel group drives The duration of dynamic signal, the first grid line and third grid connected greater than first shift register cell to the first pixel group The total duration of the gate drive signal of line output, the first pixel group are any in multiple pixel groups that display panel includes A pixel group；

Another aspect provides a kind of display device, and the display device includes: display panel, and as in terms of above-mentioned The gate driving circuit；

The display panel includes multiple pixel groups, and each pixel group includes two row sub-pixels, wherein a line sub-pixel with First grid line and the connection of the second grid line, another row sub-pixel is connect with second grid line and third grid line, and two neighboring picture Adjacent rows sub-pixel in plain group shares first grid line or shares a third grid line, the gate driving Circuit is connect with first grid line, second grid line and the third grid line respectively, the gate driving circuit be used for First grid line, second grid line and the third grid line provide gate drive signal

In conclusion technical solution bring beneficial effect provided in an embodiment of the present invention at least may include:

The embodiment of the invention provides a kind of gate driving circuit and its driving methods, display device.Gate driving electricity Road includes multiple pixel groups for driving, and each pixel group includes two row sub-pixels, a line sub-pixel and the first grid line and the The connection of two grid lines, the display panel that another row sub-pixel is connect with the second grid line and third grid line.Due to the gate driving circuit Including at least two cascade first shift register cells and at least two cascade second shift register cells, and for The first pixel group in multiple pixel groups, the first grid line and third that the first shift register cell is connected to the first pixel group Grid line exports the period of gate drive signal, the second gate that the second shift register cell can be connected to the first pixel group Line exports gate drive signal, the first shift register list that the first pixel group is connect with the grid line that adjacent pixel group shares Member can stop output gate drive signal in the second grid line that the second shift register cell is connected to the first pixel group Moment stops output gate drive signal, and can export gate drive signal less than the second shift register cell in duration Duration target duration after continue to output gate drive signal.

Due to shift register cell be it is a kind of using array substrate row actuation techniques by each electronic component integration aobvious Show the structure on substrate, therefore under the premise of guaranteeing reliable driving, for the display device of certain volume, relative to related skill Art is driven using driving IC, which only needs to occupy the lesser space of the display device, correspondingly, can make this The space that display panel can be arranged in display device is larger, so that the pixel that can be arranged in the display panel is more, mentions Rise the resolution ratio of display device.

Detailed description of the invention

To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.

Fig. 1 is a kind of structural schematic diagram of pixel provided in an embodiment of the present invention；

Fig. 2 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；

Fig. 3 is a kind of structural schematic diagram of first shift register cell provided in an embodiment of the present invention；

Fig. 4 is the structural schematic diagram of another first shift register cell provided in an embodiment of the present invention；

Fig. 5 is a kind of structural schematic diagram of second shift register cell provided in an embodiment of the present invention；

Fig. 6 is the structural schematic diagram of another second shift register cell provided in an embodiment of the present invention；

Fig. 7 is the structural schematic diagram of another the first shift register cell provided in an embodiment of the present invention；

Fig. 8 is the structural schematic diagram of another the second shift register cell provided in an embodiment of the present invention；

Fig. 9 is the structural schematic diagram of another the first shift register cell provided in an embodiment of the present invention；

Figure 10 is the structural schematic diagram of another the second shift register cell provided in an embodiment of the present invention；

Figure 11 is the structural schematic diagram of another the second shift register cell provided in an embodiment of the present invention；

Figure 12 is a kind of method flow diagram of gate driving circuit provided in an embodiment of the present invention；

Figure 13 is the structural schematic diagram of another gate driving circuit provided in an embodiment of the present invention；

Figure 14 is a kind of timing diagram of each signal end of gate driving circuit provided in an embodiment of the present invention；

Figure 15 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.

Specific embodiment

To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention is implemented below in conjunction with attached drawing Mode is described in further detail.

The transistor used in all embodiments of the invention all can be thin film transistor (TFT) or field-effect tube or other characteristics Identical device is mainly switching transistor according to transistor used by effect the embodiment of the present invention in circuit.By It is symmetrical in the source electrode of the switching transistor used here, drain electrode, so its source electrode, drain electrode can be interchanged.In this hair In bright embodiment, wherein it will be known as the first pole by source electrode, drain electrode is known as the second pole；Alternatively, referred to as the first pole that will wherein drain, source electrode Referred to as the second pole.Provide that the intermediate ends of transistor are grid, signal input part is source electrode, output end is leakage by the form in attached drawing Pole.In addition, switching transistor used by the embodiment of the present invention may include in p-type switching transistor and N-type switching transistor It is any, wherein p-type switching transistor grid be low level when be connected, grid be high level when end, N-type switch Transistor is connected when grid is high level, ends when grid is low level.In addition, multiple in each embodiment of the present invention Signal is all corresponding with the first current potential and the second current potential, and the current potential that the first current potential and the second current potential only represent the signal has 2 differences Quantity of state, not representing the first current potential and the second current potential in full text has specific numerical value.

With the progress of display technology, a series of small volumes come into being convenient for the display device worn.For example, can wear Wear equipment.The embodiment of the present invention is also illustrated by taking wearable device as an example.Also, in order to reduce the entirety of wearable device Power consumption promotes the cruising ability of wearable device, and wearable device is generally based on total reflection display and semi-transparent half display at present. In addition to this, in order under the premise of ensuring low-power consumption, realize that broken colour is shown, in the display panel that wearable device includes, Each pixel can be divided into two sub-pixels (being referred to as piecemeal processing), and the two sub-pixels can be distinguished It is driven.

Fig. 1 is the structural schematic diagram for the pixel that a kind of wearable device provided in an embodiment of the present invention includes.Such as Fig. 1 institute Show, which may include the light-emitting component R1 for driving transistor and connecting with driving transistor, correspondingly, at piecemeal After reason, with reference to Fig. 1, which may include two sub-pixels 001 and 002, and each sub-pixel may each comprise a driving Transistor M1, a driving transistor M2 and a sub- light-emitting component R11.Driving transistor with reference to Fig. 1, in sub-pixel 001 The grid of M1 can be connect with the first grid line G1, and first extremely can drive the second pole of transistor M2 to connect with one, the second pole It can be connect with a sub- light-emitting component R11.The grid of driving transistor M1 in sub-pixel 002 can connect with third grid line G3 It connects, first can extremely connect with the second pole of another driving transistor M2, and second extremely can be with another sub- light-emitting component R11 Connection.And the grid of the driving transistor M2 in the two sub-pixels can be connect with the second grid line G2, first extremely can be equal It is connect with data line D1.

Wherein, when the second grid line G2 provides gate drive signal, two driving transistor M2 are opened, on data line D1 Data-signal can be exported by this two driving transistor M2 to the driving transistor M1 respectively connected.It is mentioned in the first grid line G1 When for gate drive signal, the driving transistor M1 connecting with first grid line G1 can be by the data-signal of its first pole storage The sub- light-emitting component R11 connected to it is exported, to drive the sub- light-emitting component R11 to shine.Similarly, it is provided in third grid line G3 When gate drive signal, the data-signal that the driving transistor M1 connecting with third grid line G3 can store its first pole is defeated Out to the sub- light-emitting component R11 that it is connected, to drive the sub- light-emitting component R11 to shine.

Since each pixel includes two sub-pixels, a sub-pixel is connect with the first grid line and the second grid line, another Sub-pixel is connect with the second grid line and third grid line, therefore when being driven, and can be driven using double grid.It that is to say, it can be with A gate driving circuit is arranged to connect with the first grid line and third grid line, which can be used for the first grid line Gate drive signal is provided with third grid line.Another gate driving circuit can be set to connect with the second grid line, which drives Dynamic circuit can be used for providing gate drive signal to the second grid line.And in order to realize that low frequency driving (is ensured low with this simultaneously Power consumption) and high-frequency drive (display effect is ensured with this), the gate driving circuit for providing gate drive signal to the second grid line need to Have the ability of long-time stable output, provides the gate driving circuit of gate drive signal to the first grid line and third grid line Need to have the ability opened twice in the short time.In addition to this, in order to avoid the gate driving circuit pair of realization low frequency driving It realizes that the transistor in the gate driving circuit of high-frequency drive causes low pressure bias effect, two grids can independently be driven to drive Dynamic circuit work.

Fig. 2 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention, which can For driving display panel.With reference to Fig. 2, which may include: multiple pixel groups 02, and each pixel group 02 can be with It include: two adjacent row sub-pixels 021 and 022, the structure of each pixel in each pixel group can refer to Fig. 1.

Also, with reference to Fig. 2 can be seen that a line sub-pixel in each pixel group can respectively with the first grid line G1 and the Two grid line G2 connections, another row sub-pixel can be connect with the second grid line G2 and third grid line G3 respectively, two neighboring pixel Adjacent rows sub-pixel in group can share a first grid line G1 or share a third grid line G3.For example, with reference to Fig. 2, The first row sub-pixel 021 in first pixel group 02 is connect with the first grid line G1 and the second grid line G2, first pixel group 02 In the second row sub-pixel 021 connect with the second grid line G2 and third grid line G3, the second sub-pixel 021 and the third line sub-pixel 021 shares a third grid line G3.

In embodiments of the present invention, with reference to Fig. 2, which may include: at least two cascade first Shift register cell 101 and at least two cascade second shift register cells 102.This at least two cascade One shift register cell 101 is referred to as the first sub- gate driving circuit, at least two cascade second shift LD Device unit 102 is referred to as the second sub- gate driving circuit.

Wherein, cascade two the first shift register cells 101 respectively with a first grid line G1 and a third grid Line G3 connection, each second shift register cell 102 can be connect with the second grid line G2, and each shift register cell The grid line of connection is different.The the first grid line G1 or third grid line G3 that first shift register cell 101 can be connected to it Gate drive signal is exported, the second grid line G2 that the second shift register cell 102 can be connected to it exports gate driving Signal.

Also, the first grid line G1 and third grid line G3 connected in the first shift register cell 101 to the first pixel group Export the period of gate drive signal, the second gate that the second shift register cell 102 can be connected to the first pixel group Line G2 exports gate drive signal.And second the second grid line G2 that is connected to the first pixel group of shift register cell 102 it is defeated The duration of gate drive signal out, the first grid line G1 connected greater than the first shift register cell 101 to the first pixel group With the total duration of the gate drive signal of third grid line G3 output.Wherein, which can include for display panel Any one pixel group in multiple pixel groups 02, for being connect with other pixel groups in display panel in addition to the first pixel group The first shift register cell and the second shift register cell, can also with reference to connect with the first pixel group first shifting The driving method of bit register unit and the second shift register cell, the embodiment of the present invention repeat no more this.

The first shift register cell 101 connecting with target grid line stops output gate drive signal mesh in object time After marking duration, it can continue to export gate drive signal to the target grid line.The target grid line can for the first pixel group with The shared grid line of adjacent pixel group, the object time can connect for the second shift register cell 102 to the first pixel group At the time of the second grid line G2 connect stops output gate drive signal, target duration can be less than the second shift register cell The duration of 102 output gate drive signals.It can be seen that in conjunction with Fig. 1 and Fig. 2 through above-mentioned driving method, it is ensured that first The reliable driving of shift register cell 101 and the second shift register cell 102 to each pixel group.

It is exemplary, it is assumed that the first pixel group is first pixel group 02 shown in Fig. 2, then the target grid line can be for one Third grid line G3.Two the first shift register cells 101 connecting with first pixel group 02 can be first to this The the first grid line G1 and third grid line G3 that pixel group 02 connects are sequentially output gate drive signal.And in the first shift register list Member 101 exports gate drive signal to the first grid line G1, and to the period of third grid line G3 output gate drive signal, with this Second shift register cell 102 of first pixel group 02 connection can be always to the second of first pixel group 02 connection Grid line G2 exports gate drive signal, so that successively opening in driving transistor M1, M2 is kept it turning on, and then ensure that The two reliable outputting data signals of row sub-pixel that data line D1 can include to first pixel group 02, that is, ensure that this The reliable driving of two row sub-pixels in one pixel group 02.

When second shift register cell 102 stops exporting gate drive signal to the second grid line G2, with third grid First shift register cell 101 of line G3 connection can stop exporting gate drive signal, so as to avoid grid are continued to output Pole driving signal, and the data-signal by mistake is caused to export to the first row sub-pixel 021 of second pixel group 02, cause letter The problem of number crosstalk.And in target of the duration less than the duration of the second shift register cell 102 output gate drive signal After length, the first shift register cell 101 connecting with third grid line G3 can continue to output gate drive signal, to drive A line sub-pixel work being connect in second pixel group 02 with third grid line G3, and then ensure that two neighboring pixel group In share a grid line two row sub-pixels reliable driving.

In conclusion the gate driving circuit is for driving packet the embodiment of the invention provides a kind of gate driving circuit Multiple pixel groups are included, and each pixel group includes two row sub-pixels, a line sub-pixel is connect with the first grid line and the second grid line, separately The display panel that a line sub-pixel is connect with the second grid line and third grid line.Since the gate driving circuit includes at least two grades Cascade second shift register cell of the first shift register cell and at least two of connection, and in multiple pixel groups First pixel group, the first grid line and third grid line the output grid that the first shift register cell is connected to the first pixel group drive The period of dynamic signal, the second grid line that the second shift register cell can be connected to the first pixel group export gate driving Signal, the first shift register cell that the first pixel group is connect with the grid line that adjacent pixel group shares, can be second At the time of the second grid line that shift register cell is connected to the first pixel group stops output gate drive signal, stop output Gate drive signal, and can be in target of the duration less than the duration of the second shift register cell output gate drive signal Gate drive signal is continued to output after length.Due to shift register cell be it is a kind of using array substrate row actuation techniques will be each Structure of the electronic component integration on display base plate, therefore display under the premise of guaranteeing reliable driving, for certain volume Device is driven relative to the relevant technologies using driving IC, which only needs to occupy the lesser space of the display device, Correspondingly, the space that can enable the display device that display panel is arranged is larger, so that can in the display panel The pixel of setting is more, promotes the resolution ratio of display device.

Fig. 3 is a kind of structural schematic diagram of first shift register cell provided in an embodiment of the present invention.As shown in figure 3, First shift register cell 101 may include: that the first input module 1011, first pull-up control module 1012, first is defeated Module 1013, the first pull-down control module 1014 and the first pull-down module 1015 out.

Wherein, first input module 1011 can respectively with the first input signal end IN1, the first power end VDD and One pull-up node PU1 connection.The input that first input module 1011 can be provided in response to the first input signal end IN1 is believed Number, the first power supply signal from the first power end VDD is exported to the first pull-up node PU1.

Exemplary, the current potential of first power supply signal can be the first current potential, and first current potential can be effective current potential. First input module 1011 can the first input signal end IN1 provide input signal current potential be the first current potential when, to First pull-up node PU1 exports the first power supply signal from the first power end VDD, to realize to the first pull-up node PU1's Charging.

The first pull-up control module 1012 can connect with the first pull-up node PU1 and the first clock signal terminal CLK1 respectively It connects.What the first pull-up control module 1012 can be provided in response to the first pull-up node PU1 and the first clock signal terminal CLK1 First clock signal controls the current potential of the first pull-up node PU1.

Exemplary, which can believe in the current potential of the first pull-up node PU1 and the first clock Number current potential when being the first current potential, the first clock signal of the first current potential is in the first pull-up node PU1 output, is realized pair The lasting charging of first pull-up node PU1.

First output module 1013 can be controlled with the first pull-up node PU1, the first clock signal terminal CLK1, first respectively Signal end CLK_A processed and the first output end OUT1 connection.First output module 1013 can be in response to the first pull-up node PU1 Current potential and first control signal end CLK_A provide first control signal, to the first output end OUT1 export the first clock letter Number.

Exemplary, the first output module 1013 can be in the current potential of the first pull-up node PU1 and the electricity of first control signal When position is the first current potential, the first clock signal is exported to the first output end OUT1.

Since the first pull-up control module 1012 can be in the current potential and the first clock signal of the first pull-up node PU1 When current potential is the first current potential, realize charging again to the first pull-up node PU1, and the current potential of the first pull-up node PU1, When the current potential of first clock signal and the current potential of first control signal are the first current potential, the first output module 1013 can be to One output end OUT1 output is in the first clock signal of the first current potential, i.e., exports grid to the first grid line G1 or third grid line G3 Driving signal.Therefore can be controlled by the first control signal provided first control signal end CLK_A, with realization to First grid line G1 or third grid line G3 persistently export gate drive signal, it can realize the characteristic of output for a long time.

In addition, since first output module 1013 can be in the first pull-up node PU1 and first control signal end CLK_B Under the control of the first control signal of offer, the first clock signal is exported to the first output end OUT1, therefore control can be passed through Whether the current potential of first control signal, the first output module 1013 of control to the first output end OUT1 export the first clock signal. The feature exported twice in single frames can be realized by controlling the current potential of the first control signal.Due in two pixel groups Two adjacent row sub-pixels share a grid line, therefore can guarantee that the two rows sub-pixel can be in the grid line control that it is connected Lower reliable display.

First pull-down control module 1014 can be electric with the first pull-up node PU1, second source end GCH, third respectively Source VGL and the first pull-down node PD1 connection.First pull-down control module 1014 can be in response to the first pull-up node PU1 Current potential and second source end GCH provide second source signal, to the first pull-down node PD1 output come from third power end The third power supply signal of VGL, alternatively, exporting second source signal to the first pull-down node PD1.

Wherein, the current potential of the second source signal can be the first current potential, and the current potential of the third power supply signal can be the Two current potentials, second current potential can be invalid current potential.

It is exemplary, first pull-down control module 1014 can the current potential of the first pull-up node PU1 be the first current potential when, It is in the third power supply signal of the second current potential, to the first pull-down node PD1 output to realize the drop to the first pull-down node PD1 It makes an uproar.And first pull-down control module 1014 can be when the current potential of the first pull-up node PU1 be the second current potential, in second source Under the control of signal, it is in the second source signal of the first current potential to the first pull-down node PD1 output, is pulled down with realizing to first The charging of node PD1.

First pull-down module 1015 can be electric with second control signal end CLK_B, initial signal end STV0, third respectively Source VGL, the first pull-down node PD1, the first pull-up node PU1 and the first output end OUT1 connection.First pull-down module 1015 initial signals that can be provided in response to the current potential and initial signal end STV0 of the first pull-down node PD1, to the first pull-up Node PU1 exports third power supply signal, and the second control signal that can be provided in response to second control signal end CLK_B, Third power supply signal is exported to the first output end OUT1.

Wherein, the current potential of the second control signal can be complementary with the current potential of first control signal.I.e. in the first control letter Number current potential be the first current potential when, the current potential of the second control signal can be the second current potential；In the current potential of first control signal When for the second current potential, the current potential of the first control signal can be the first current potential.

Exemplary, which can be the first current potential in the current potential of the first pull-down node PD1, when, to First pull-up node PU1 output is in the third power supply signal of the second current potential, can be the first current potential in the current potential of initial signal When, the third power supply signal of the second current potential is in the first pull-up node PU1 output, to realize to the first pull-up node PU1 Noise reduction.First pull-down module 1015 can also be in the current potential of the second control signal end CLK_B second control signal provided When for the first current potential, the third power supply signal of the second current potential is in the first output end OUT1 output.It is defeated to first to realize The noise reduction of outlet OUT1.

Since the current potential of the second control signal and the current potential of first control signal are complementary, control second can be passed through The current potential for controlling signal, when the first output module 1013 stops exporting the first clock signal to the first output end OUT1, in time Noise reduction is carried out to the first output end OUT1.It avoids driving two rows of a shared grid line in the first shift register cell 101 When pixel, the problem of resetting the output signal of the first output end OUT1 not in time, and cause signal cross-talk.

Fig. 4 is a kind of structural schematic diagram of first output module provided in an embodiment of the present invention.As shown in figure 4, this first Output module 1013 may include: output sub-module 1013A and output control submodule 1013B.

Wherein, output sub-module 1013A can respectively with the first pull-up node PU1, the first clock signal terminal CLK1 and Output node PO1 connection.Output sub-module 1013A can be in response to the current potential of the first pull-up node PU1, to output node PO1 exports the first clock signal.

Exemplary, output sub-module 1013A can be when the current potential of the first pull-up node PU1 be the first current potential, to defeated Egress PO1 exports the first clock signal.

Output control submodule 1013B can respectively with output node PO1, first control signal end CLK_A and first Output end OUT1 connection.Output control submodule 1013B can be defeated to the first output end OUT1 in response to first control signal The first clock signal that output sub-module 1013A is exported to output node PO1 out.

Exemplary, output control submodule 1013B can be when the current potential of first control signal be the first current potential, to the One output end OUT1 exports the first clock signal.

Correspondingly, with reference to Fig. 4, the first pull-down module 1015 can also respectively with the 4th power end GCL and output node PO1 Connection.First pull-down module 1015 may also respond to the first pull-down node PD1 current potential and the 4th power end GCL provide 4th power supply signal exports third power supply signal to output node PO1.

It is exemplary, first pull-down module 1015 can also the current potential of the first pull-down node PD1 be the first current potential when, to Output node PO1 output is in the third power supply signal of the second current potential；And it can be in the 4th electricity that the 4th power end GCL is provided When the current potential of source signal is effective current potential, the third power supply signal of the second current potential is in output node PO1 output, to realize To the noise reduction of output node PO1.

Since the first pull-down module 1015 can carry out output node PO1 in response to the current potential of the first pull-down node PD1 Noise reduction, therefore can realize to the timely noise reduction of output node PO1 after the completion of being driven to every row sub-pixel, avoid output The phenomenon that node PO1 leaks electricity and causes voltage drift.In addition, since the first pull-down module 1015 may also respond to the 4th power supply Signal carries out noise reduction to output node PO1, therefore can also be after every frame scan, to the output section of entire display panel The phenomenon that point PO1 is once resetted, and is further avoided output node PO1 electric leakage and is caused voltage drift.

Fig. 5 is a kind of structural schematic diagram of second shift register cell provided in an embodiment of the present invention.As shown in figure 5, Second shift register cell 102 may include: that the second input module 1021, second pull-up control module 1022, second is defeated Module 1023, the second pull-down control module 1024 and the second pull-down module 1025 out.

Wherein, second input module 1021 can respectively with the second input signal end IN2, the first power end VDD and Two pull-up node PU2 connections.The input that second input module 1021 can be provided in response to the second input signal end IN2 is believed Number, the first power supply signal is exported to the second pull-up node PU2.

Exemplary, which can be in the current potential of the second input signal end IN2 input signal provided When for the first current potential, it is in the first power supply signal of the first current potential to the second pull-up node PU2 output, realizes and the second pull-up is saved The charging of point PU2.

The second pull-up control module 1022 can connect with the second pull-up node PU2 and second clock signal end CLK2 respectively It connects.The second pull-up control module 1022 can be in response to the current potential and second clock signal end CLK2 of the second pull-up node PU2 The second clock signal of offer controls the current potential of the second pull-up node PU2.

Exemplary, which can be in the current potential and second clock of the second pull-up node PU2 When the current potential of second clock signal that signal end CLK2 is provided is the first current potential, to the second pull-up node PU2 output in the The second clock signal of one current potential, to realize the charging again to the second pull-up node PU2.

Second output module 1023 can respectively with the second pull-up node PU2, second clock signal end CLK2 and second Output end OUT2 connection.Second output module 1023 can be in response to the current potential of the second pull-up node PU2, to second output terminal OUT2 exports second clock signal.

Exemplary, which can be when the current potential of the second pull-up node PU2 be the first current potential, to the Two output end OUT2 export second clock signal.

Similarly, since the second pull-up control module 1022 can be in the current potential and second clock of the second pull-up node PU2 When the current potential of signal is the first current potential, the charging again to the second pull-up node PU2 is realized, and in the second pull-up node PU2 Current potential and the current potential of second clock signal when being the first current potential, the second output module 1023 can be to second output terminal OUT2 Output is in the second clock signal of the first current potential, i.e., provides gate drive signal to the second grid line G2.It therefore can be second When output module 1023 is in the second clock signal of the first current potential to second output terminal OUT2 output, guarantee the second pull-up node The current potential of PU2 stabilizes to the first current potential, to realize the characteristic for exporting gate drive signal for a long time.

Second pull-down control module 1024 can be electric with the second pull-up node PU2, second source end GCH, third respectively Source VGL and the second pull-down node PD2 connection.Second pull-down control module 1024 can be in response to the second pull-up node PU2 Current potential and second source signal, to the second pull-down node PD2 export third power supply signal, alternatively, to the second pull-down node PD2 Export second source signal.

It is exemplary, second pull-down control module 1024 can the current potential of the second pull-up node PU2 be the first current potential when, The third power supply signal of the second current potential is in the second pull-down node PD2 output, to realize the drop to the second pull-down node PD2 It makes an uproar.And second pull-down control module 1024 can be when the current potential of the second pull-up node PU2 be the second current potential, in second source Under the control of signal, the second source signal of the first current potential is in the second pull-down node PD2 output, to realize under second Draw the charging of node PD2.

Second pull-down module 1025 can respectively with the 4th power end GCL, initial signal end STV0, third power end VGL, the second pull-down node PD2, the second pull-up node PU2 are connected with second output terminal OUT2.Second pull-down module 1025 can With the current potential and initial signal in response to the second pull-down node PD2, third power supply signal is exported to the second pull-up node PU2, with And third power supply can be exported to second output terminal OUT2 in response to the current potential of the 4th power supply signal and the second pull-down node PD2 Signal.

Exemplary, which can be the first current potential in the current potential of the second pull-down node PD2, when, to Second pull-up node PU2 and second output terminal OUT2 output is in the third power supply signal of the second current potential；It can be in initial signal Current potential when being the first current potential, the third power supply signal of the second current potential is in the second pull-up node PU2 output, and can be Under the control of 4th power supply signal, the second source signal of the second current potential is in second output terminal OUT2 output.To realize To the noise reduction of the second pull-up node PU2 and second output terminal OUT2.

Similarly, since the second pull-down module 1025 can be in response to the current potential of the second pull-down node PD2, to second output terminal OUT2 carries out noise reduction, therefore can realize the timely noise reduction to second output terminal OUT2 after the completion of driving to every row sub-pixel, The problem of avoiding second output terminal OUT2 electric leakage and causing voltage drift.Since the second pull-down module 1025 may also respond to 4th power supply signal carries out noise reduction to second output terminal OUT2, therefore can also be after every frame scan, to entire display surface The phenomenon that second output terminal OUT2 of plate carries out an integral reset, further avoids voltage drift.

Optionally, with reference to Fig. 4 and Fig. 6, the first pull-up control module 1012 and the second pull-up control module 1022 are equal It may include: pull-up control submodule and pull-up submodule.

Wherein, which can believe with target pull-up node, target control node and target clock respectively Number end connection.The pull-up control submodule can come from response to the current potential of target pull-up node to target control node output The clock signal at target clock signal end.

Exemplary, which can be when the current potential of target pull-up node be the first current potential, to target control Node processed exports the clock signal from target clock signal end.

The pull-up submodule can be connect with target control node, target clock signal end and target pull-up node respectively. The pull-up submodule can export target clock signal to target pull-up node in response to the current potential of target control node.

Exemplary, which can pull up to target and save when the current potential of target control node is the first current potential Point output target clock signal.

Correspondingly, target pull-down module can be connect with target control node, target pull-down module can be in response to mesh The current potential for marking pull-down node exports third power supply signal to target control node.

Exemplary, target pull-down module can be when the current potential of target pull-down node be the first current potential, to target control section Point output is in the third power supply signal of the second current potential, to realize the noise reduction to target control node.

Alternatively, the pull-up control submodule can be controlled with target pull-up node, first object respectively with reference to Fig. 7 and Fig. 8 Node and the connection of the second target control node, pull-up control submodule can control the in response to the current potential of target pull-up node The on off operating mode of one target control node and the second target control node.

Exemplary, which can be when the current potential of target pull-up node be the first current potential, control first Target control node and the conducting of the second target control node；When the current potential of target pull-up node is the second current potential, control first Target control node and the second target control node disconnect.

Pull up submodule can respectively with first object control node, the second target control node, target clock signal end It is connected with target pull-up node.The pull-up submodule can be connected in first object control node and the second target control node When, the target clock signal from target clock signal end is exported to target pull-up node.

Correspondingly, target pull-down module can also be connect with the second target control node, target pull-down module can be responded In the current potential of target pull-down node, third power supply signal is exported to the second target control node.

Exemplary, target pull-down module can be when the current potential of target pull-down node be the first current potential, to the second target control Node output processed is in the third power supply signal of the second current potential, to realize the noise reduction to the second target control node.By setting It sets pull-up control submodule to connect with two target control nodes, and drop-down submodule and two target control nodes companies is set It connects, the reliable charging to target pull-up node can be further ensured to avoid target clock signal there is a phenomenon where leaking electricity.

Wherein, the corresponding target pull-up node of the first shift register cell is the first pull-up node PU1, target control section Point is the first control node PC1, target clock signal end is the first clock signal terminal CLK1, target pull-down module is the first drop-down Module 1015, target pull-down node be the first pull-down node PD1, first object control node be first object node P1, second Target control node is the second destination node P2.The corresponding target pull-up node of second shift register cell is target pull-up section Point is the second pull-up node PU2, target control node is the second control node PC2, and target clock signal end is second clock letter Number end CLK2, target pull-down module be the second pull-down module 1025, target pull-down node be the second pull-down node PD2, the first mesh Mark control node is third destination node P3, and the second target control node is the 4th destination node P4.

A kind of optional implementation, the pull-up control submodule for including with reference to Fig. 4, the first pull-up control module 1012 1012A can be connect with the first pull-up node PU1, the first control node PC1 and the first clock signal terminal CLK1 respectively.Upper rock Module 1012B can be connect with the first control node PC1, the first clock signal terminal CLK1 and the first pull-up node PU1 respectively.Phase It answers, the first pull-down module 1015 can also be connect with the first control node PC1.With reference to Fig. 6, the second pull-up control module The 1022 pull-up control submodule 1022A for including can respectively with the second pull-up node PU2, the second control node PC2 and second Clock signal terminal CLK2 connection.Pull up submodule 1022B can respectively with the second control node PC2, second clock signal end CLK2 and the second pull-up node PU2 connection.Correspondingly, the second pull-down module 1025 can also be connect with the second control node PC2.

Another optional implementation, the pull-up control submodule for including with reference to Fig. 7, the first pull-up control module 1012 Block 1012A can be connect with the first pull-up node PU1, first object node P1 and the second destination node P2 respectively.Pull up submodule Block 1012B can be saved with first object node P1, the second destination node P2, the pull-up of the first clock signal terminal CLK1 and first respectively Point PU1 connection.Correspondingly, the first pull-down module 1015 can also be connect with the second destination node P2.With reference to Fig. 8, this is on second Draw control module 1022 include pull-up control submodule 1022A can respectively with the second pull-up node PU2, third destination node P3 and the 4th destination node P4 connection.Pull up submodule 1022B can respectively with third destination node P3, the 4th destination node P4, second clock signal end CLK2 and the second pull-up node PU2 connection.Correspondingly, the second pull-down module 1025 can also be with Four destination node P4 connections.

Optionally, pull-up control submodule respectively with target pull-up node, target control node and target clock signal End connection, when pull-up submodule is connect with target control node, target clock signal end and target pull-up node respectively.The pull-up Control submodule may include: pull-up control transistor.Pull-up submodule includes: first to pull up transistor.Pull-up control crystal The grid of pipe is connect with target pull-up node, and the first pole is connect with target clock signal end, and the second pole and target control node connect It connects.First grid to pull up transistor is connect with target control node, and the first pole is connect with target clock signal end, the second pole with The connection of target pull-up node.

Exemplary, Fig. 9 is a kind of structural schematic diagram of first shift register cell provided in an embodiment of the present invention.Such as figure Shown in 9, the grid for the pull-up control transistor L11 that the pull-up control submodule 1012A in the first pull-up control module 1012 includes Pole is connect with the first pull-up node PU1, and the first pole is connect with the first clock signal terminal CLK1, the second pole and the first control node PC1 connection.The first grid for pulling up transistor L12 that pull-up submodule 1012B in first pull-up control module 1012 includes It is connect with the first control node PC1, the first pole is connect with the first clock signal terminal CLK1, the second pole and the first pull-up node PU1 Connection.

Exemplary, Figure 10 is a kind of structural schematic diagram of second shift register cell provided in an embodiment of the present invention.Such as Shown in Figure 10, the pull-up that the pull-up control submodule 1022A in the second pull-up control module 1022 includes controls transistor L21 Grid is connect with the second pull-up node PU2, and the first pole is connect with second clock signal end CLK2, the second pole and the second control node PC2 connection.Second, which pulls up the pull-up control submodule 1022B in control module 1022 includes first, pulls up transistor L22's Grid is connect with the second control node PC2, and the first pole is connect with second clock signal end CLK2, the second pole and the second pull-up node PU2 connection.

Optionally, pull-up control submodule respectively with target pull-up node, first object control node and the second target Control node connection, pull-up submodule respectively with first object control node, the second target control node, target clock signal end When connecting with target pull-up node, pull-up submodule can also include: second to pull up transistor.And the grid of pull-up control transistor It can extremely be connect with target pull-up node, the first of pull-up control transistor can extremely connect with first object control node, on Drawing the second of control transistor can extremely connect with the second target control node, and the first grid to pull up transistor can be with first Target control node connection, first pull up transistor first can extremely be connect with the second pole that second pulls up transistor, first Second to pull up transistor can extremely connect with target pull-up node, and the second grid to pull up transistor can be with the second target control Node processed connection, second pull up transistor first can extremely be connect with target clock signal end.

Exemplary, Figure 11 is the structural schematic diagram of another second shift register cell provided in an embodiment of the present invention. As shown in figure 11, the pull-up control transistor that the pull-up control submodule 1022A in the second pull-up control module 1022 includes The grid of L21 is connect with the second pull-up node PU2, and the first pole is connect with third destination node P3, the second pole and the 4th target section Point P4 connection.The first grid for pulling up transistor L22 that pull-up submodule 1022B includes is connect with the 4th destination node P4, the One pole is connect with the second the second pole for pulling up transistor L23 that the second pull-up control module 1022 includes, on the second pole and second Draw node PU2 connection.Pull-up submodule 1022B include second pull up transistor L23 grid and third destination node P3 connect It connects, the first pole is connect with second clock signal end CLK2.

It optionally, may include: the first output transistor O11 and first capacitor with reference to Fig. 9, output sub-module 1013A Device C11.Exporting control submodule 1013B may include: output control transistor O12.

Wherein, the grid of first output transistor O11 can be connect with the first pull-up node PU1, the first output crystal The first of pipe O11 can extremely connect with the first clock signal terminal CLK1, and the second of the first output transistor O11 extremely can be with output Node PO1 connection.

One end of first capacitor device C11 can be connect with the first pull-up node PU1, and the other end of first capacitor device C11 can To be connect with output node PO1.

The grid of output control transistor O12 can be connect with first control signal end CLK_A, output control transistor The first of O12 can extremely connect with output node PO1, and the second of output control transistor O12 extremely can be with second output terminal OUT2 connection.

Optionally, with reference to Fig. 9, which may include: the first input transistors N11.

The grid of first input transistors N11 can be connect with the first input signal end IN1, the first input transistors The first of N11 can extremely connect with the first power end VDD, and the second of the first input transistors N11 can extremely be saved with the first pull-up Point PU1 connection.

Optionally, with reference to Fig. 9, first pull-down control module 1014 may include: the first drop-down control transistor M11 and Second drop-down control transistor M12.

The grid and first of first drop-down control transistor M11 extremely can be connect with second source end GCH, this first The second of drop-down control transistor M11 can extremely connect with the first pull-down node PD1.Second drop-down control transistor M12's Grid can be connect with the first pull-up node PU1, and the first of the second drop-down control transistor M12 extremely can be with third power end VGL connection, the second of the second drop-down control transistor M12 can extremely connect with the first pull-down node PD1.

Optionally, with reference to Fig. 9, which may include: the first pull-down transistor T11, the second drop-down The lower crystal pulling of transistor T12, third pull-down transistor T13, the 4th pull-down transistor T14, the 5th pull-down transistor T15 and the 6th Pipe T16.

Wherein, the grid of first pull-down transistor T11, the second pull-down transistor T12 and third pull-down transistor T13 can To connect with the first pull-down node PD1, the grid of the 4th pull-down transistor T14 can be connect with initial signal end STV0, the The grid of five pull-down transistor T15 can be connect with second control signal end CLK_B, and the grid of the 6th pull-down transistor T16 can To be connect with the 4th power end GCL.First pull-down transistor T11, the second pull-down transistor T12, third pull-down transistor T13, The first of 4th pull-down transistor T14, the 5th pull-down transistor T15 and the 6th pull-down transistor T16 extremely can with third electricity Source VGL connection.The second of first pull-down transistor T11 and the 4th pull-down transistor T14 extremely can with the first pull-up node PU1 connection, the second of the second pull-down transistor T12 can extremely connect with the first control node PC1, third pull-down transistor T13 It can extremely be connect with output node PO1 with the second of the 6th pull-down transistor T16, the second pole of the 5th pull-down transistor T15 can To be connect with the first output end OUT1.

Optionally, with reference to Figure 10 and Figure 11, which may include: the second input transistors N21.It should The grid of second input transistors N21 can be connect with the second input signal end IN2, the first pole of the second input transistors N21 It can be connect with the first power end VDD, the second of the second input transistors N21 can extremely connect with the second pull-up node PU2.

Optionally, with reference to Figure 10, which may include: third drop-down control transistor M21 With the 4th drop-down control transistor M22.

The grid and first of third drop-down control transistor M21 extremely can be connect with second source end GCH, the third The second of drop-down control transistor M21 can extremely connect with the second pull-down node PD2.4th drop-down control transistor M22's Grid can be connect with the second pull-up node PU2, and the first of the 4th drop-down control transistor M22 extremely can be with third power end VGL connection, the second of the 4th drop-down control transistor M22 can extremely connect with the second pull-down node PD2.

Alternatively, second pull-down control module 1024 can also include: the 5th drop-down control transistor M23 with reference to Figure 11 With the 6th drop-down control transistor M24.

Correspondingly, the second pole of third drop-down control transistor M21 and the 4th drop-down control the second of transistor M22 It can extremely be connect with the second drop-down control node PD2_CN.The grid of 5th drop-down control transistor M23 can be with the second drop-down Control node PD2_CN connection, the 5th drop-down control transistor M23's first can extremely connect with second source end GCH, this The second of five drop-down control transistor M23 can extremely connect with the second pull-down node PD2.6th drop-down control transistor M24's Grid can be connect with the second pull-up node PU2, and the first of the 6th drop-down control transistor M24 extremely can be with third power end VGL connection, the second of the 6th drop-down control transistor M24 can extremely connect with the second pull-down node PD2.

Similarly, the first pull-down control module 1014 also may include similar structures, i.e. the first pull-down control module 1014 It may include additional two drop-downs control transistor, connection type can refer to Figure 11.Control node is pulled down by setting, with And additional two drop-downs control transistor, may further ensure that the reliability of control pull-down node current potential.

Optionally, with reference to Figure 10 and Figure 11, which may include: the 7th pull-down transistor T21, Eight pull-down transistor T22, the 9th pull-down transistor T23, the tenth pull-down transistor T24 and the 11st pull-down transistor T25.

Wherein, the grid of the 7th pull-down transistor T21, the 8th pull-down transistor T22 and the 9th pull-down transistor T23 can be with It being connect with the second pull-down node PD2, the grid of the tenth pull-down transistor T24 can be connect with initial signal end STV0, and the 11st The grid of pull-down transistor T25 can be connect with the 4th power end GCL.7th pull-down transistor T21, the 8th pull-down transistor T22, the 9th pull-down transistor T23, the tenth pull-down transistor T24 and the 11st pull-down transistor T25 first extremely can with The VGL connection of third power end.The second of 7th pull-down transistor T21 and the tenth pull-down transistor T24 extremely can be with the second pull-up Node PU2 connection, the second of the 8th pull-down transistor T22 can extremely connect with the second control node PC2, the 9th pull-down transistor The second of T23 and the 11st pull-down transistor T25 can extremely connect with second output terminal OUT2.

Optionally, with reference to Figure 10 and Figure 11, second input module 1023 may include: the second output transistor O21 and Second capacitor C21.

The grid of second output transistor O21 is connect with the second pull-up node PU2, the first pole and second clock signal end CLK2 connection, the second pole are connect with second output terminal OUT2.One end of second capacitor C21 is connect with the second pull-up node PU2, Second end is connect with second output terminal OUT2.

It should be noted that in order to realize bilateral scanning, the first shift register cell 101 and the second shift register list Member 102 can also include reseting module.

For the first shift register cell 101, reseting module can respectively with the first reset signal end, the 5th power supply End is connected with the first pull-up node, correspondingly, can pass through the current potential for the reset signal that the first reset signal end of control provides The current potential of the input signal provided with the first input signal end realizes forward scan or reverse scan.For the second shift LD Device unit 102, reseting module can be connect with the second reset signal end, the 5th power end and the second pull-up node respectively, phase It answers, it can provided by the current potential and the second input signal end of the reset signal of the second reset signal end of control offer defeated Enter the current potential of signal, realizes forward scan or reverse scan.And first shift register cell 101 and the second shift register The structure for the reseting module that unit 102 includes is identical, and the current potential of the 5th power supply signal may be the second current potential.

Exemplary, with reference to Figure 11, which includes reseting module 1026, the reseting module 1026 include reset transistor F21.The grid of reset transistor F21 is connect with the second reset signal end RST2, the first pole with 5th power end VSS connection, the second pole are connect with the second pull-up node PU2.

It should be noted that being using the transistor being connect with the 4th power end as P-type crystal in the above embodiments Pipe, and other transistors are the explanation that carries out for N-type transistor.Certainly, the transistor connecting with the 4th power end can also be with For N-type transistor, and other transistors are P-type transistor.

Figure 12 is a kind of driving method flow chart of gate driving circuit provided in an embodiment of the present invention, and this method can be used In driving Fig. 2 to Figure 11 it is any shown in gate driving circuit.As shown in figure 12, this method may include:

The first grid line or that step 1201, at least two cascade first shift register cells are successively connected to it Three grid lines export gate drive signal, the second gate that at least two cascade second shift register cells are successively connected to it Line exports gate drive signal.

Wherein, the first grid line and third grid line output grid connected in the first shift register cell to the first pixel group The period of driving signal, the second grid line output gate driving letter that the second shift register cell is connected to the first pixel group Number, and the second shift register cell connected to the first pixel group the second grid line output gate drive signal duration, be greater than The gate drive signal of the first grid line and third grid line that first shift register cell is connected to the first pixel group output it is total Duration, the first pixel group are any one pixel group in multiple pixel groups that display panel includes.Connect with target grid line One shift register cell continues to export grid to target grid line after object time stops output gate drive signal target duration Pole driving signal, target grid line are the grid line that the first pixel group and adjacent pixel group share, and object time is that the second displacement is posted At the time of the second grid line that storage unit is connected to the first pixel group stops output gate drive signal, target duration is less than second The duration of shift register cell output gate drive signal.

In conclusion the embodiment of the invention provides a kind of driving methods of gate driving circuit.And for display panel Including multiple pixel groups in the first pixel group, the first shift register cell which includes to this first First grid line of pixel group connection and the period of third grid line output gate drive signal, the second shift register cell can be to Second grid line of the first pixel group connection persistently exports gate drive signal.What the first pixel group and adjacent pixel group shared The first shift register cell that grid line is connected, can be connected in the second shift register cell to the first pixel group At the time of two grid lines stop output gate drive signal, stop output gate drive signal, and can move in duration less than second Gate drive signal is continued to output after the target duration of the duration of bit register unit output gate drive signal.Since displacement is posted Storage unit is a kind of structure using array substrate row actuation techniques by each electronic component integration on display base plate, therefore Under the premise of guaranteeing reliable driving, for the display device of certain volume, driven relative to the relevant technologies using driving IC, it should Gate driving circuit only needs to occupy the lesser space of the display device, correspondingly, it is aobvious that the display device can be enabled to be arranged Show that the space of panel is larger, so that the pixel that can be arranged in the display panel is more, promotes the resolution ratio of display device.

For the first shift register cell 101 shown in Fig. 9, driving principle is described below:

In input phase, the first input signal end IN1 provides the input signal for being in the first current potential, the first input transistors N11 is opened, and the first power end VDD is by the first input transistors N11 to the first pull-up node PU1 output in the first current potential First power supply signal, to realize the charging to the first pull-up node PU1.

It is the first current potential, pull-up in the current potential for the first clock signal that output stage, the first clock signal terminal CLK1 provide Transistor L11 is controlled to open.First clock signal terminal CLK1 controls transistor L11 to the first control node PC1 by the pull-up Output be in the first current potential the first clock signal, first pull up transistor L12 unlatching.First clock signal terminal CLK2 is by being somebody's turn to do First L12 that pulls up transistor exports the first clock signal in the first current potential to the first pull-up node PU1 again.In the output In the stage, because the first pull-up node PU1 is always maintained at the first current potential, and under the boot strap of first capacitor device C11, this is on first Drawing the current potential of node PU1 can increase again.Therefore the first output transistor O11 can keep stablizing unlatching.First clock letter Number end CLK1 first clock for being in the first current potential can be exported to output node PO1 by the first output transistor O11 Signal.Also, it is the first current potential in the current potential for the first control signal that the output stage, first control signal end CLK_A provide, Output control transistor O12 is opened, and exporting to the current potential of output node PO1 can be continued by output control transistor O12 It exports to the first output end OUT1.

In addition, in the input phase and output stage, the electricity for the second control signal that second control signal end CLK_B is provided Position is the second current potential, and the 5th pull-down transistor T15 shutdown passes through the 5th lower crystal pulling so as to avoid third power end VGL Pipe T15 is in the third power supply signal of the second current potential to the first output end OUT1 output, that is, avoids to the first output end OUT1's Noise reduction.The current potential for the initial signal that initial signal end STV0 is provided also is the second current potential, avoids third power end VGL by being somebody's turn to do 4th pull-down transistor T14 is in third power supply signal to the first pull-up node PU1 output, that is, avoids to the first pull-up node The noise reduction of PU1.And in the input phase and output stage, because the potential duration of the first pull-up node PU1 is the first current potential, therefore Second drop-down control transistor M12 is opened, and third power end VGL can be by the second drop-down control transistor M12 under first Node PD1 output is drawn to be in the third power supply signal of the second current potential.So that the first pull-down transistor T11, the second lower crystal pulling Body pipe T12 and third pull-down transistor T13 are held off, and are avoided third power end VGL and are passed through the first lower crystal pulling Body pipe T11 exports third power supply signal to the first pull-up node PU1, avoids third power end VGL and passes through the second lower crystal pulling Body pipe T12 exports third power supply signal to the first control node PC1 to the first control node PC1, and avoids third power supply It holds VGL to export third power supply signal to output node PO1 by the third pull-down transistor T13, that is, avoids and pulled up to first The current potential of node PU1, the first control node PC1 and output node PO1 impact.

In the drop-down stage, the jump in potential for the second control signal that second control signal end CLK_B is provided is the first current potential, 5th pull-down transistor T15 is opened, and third power end VGL can be by the 5th pull-down transistor T15 to the first output end OUT1 exports third power supply signal, realizes the noise reduction to the first output end OUT1.And in the drop-down stage, the first clock signal It is the second current potential that current potential and the current potential of first control signal, which jump, and the current potential of the first pull-up node PU1 becomes the second current potential, the Two drop-down control transistor M12 shutdowns.First drop-down control transistor M11 is opened under the control of second source signal, and second Second electricity of the power end GCH by the first drop-down control transistor M11 to the first pull-down node PD1 output in the first current potential Source signal, the first pull-down transistor T11, the second pull-down transistor T12 and third pull-down transistor T13 are opened, third power end VGL exports third power supply signal to the first pull-up node PU1 by the first pull-down transistor T11, realizes to the first pull-up node The noise reduction of PU1.Third power end VGL exports third power supply letter to the first control node PC1 by the second pull-down transistor T12 Number, realize the noise reduction to the first control node PC1.Third power end VGL passes through third pull-down transistor T12 to output node PO1 exports third power supply signal, realizes the noise reduction to output node PO1.And after having driven a frame picture, the 4th power end GCL can provide the 4th power supply signal of effective current potential, and the 6th pull-down transistor T16 is opened.Third power end VGL can pass through 6th pull-down transistor T16 exports third power supply signal to output node PO1, realizes the noise reduction again to output node PO1.

For the second shift register cell shown in Fig. 10, driving principle can refer to above-mentioned first shift register The driving principle of unit.And for the second shift register cell shown in Figure 11, under input phase and output stage, the 4th Draw the drop-down control of control transistor M22 and the 6th transistor M24 that can open under the control of the second pull-up node PU2.Third Power end VGL can be in second to the second drop-down control node PD2_CN output by the 4th drop-down control transistor M22 The third power supply signal of current potential, third power end VGL can control transistor M24 to the second pull-down node by the 6th drop-down PD2 output is in the third power supply signal of the second current potential.

In the drop-down stage, third drop-down control transistor M21 can be opened under the control of second source signal, the second electricity Source GCH is by third drop-down control transistor M21 to the second drop-down control node PD2_CN output in the first current potential Second source signal.5th drop-down control transistor M23 is opened, and second source end GCH passes through the five drop-downs control transistor again M23 exports second source signal to the second pull-down node PD2.And can also include reseting stage,

It can be the first current potential in the current potential for the reset signal that reseting stage, reset signal end RST2 provide, reset crystal Pipe F21 is opened, and the 5th power end VSS can be electric in second to the second pull-up node PU2 output by reset transistor F21 5th power supply signal of position realizes the noise reduction to the second pull-up node PU2.

Optionally, Figure 13 is the structural schematic diagram for another gate driving circuit that inventive embodiments provide.Such as Figure 13 institute Show, a gate driving circuit can be respectively set in the left and right sides of display panel 10 and pixel of not going together is driven, and The structure of the gate driving circuit of each side is identical.

Gate driving circuit on the left of Figure 13 includes the first shift register cell 101 (1), the first shift register cell 101 (2), the first shift register cell 101 (3) and first shift register cell 101 (6) etc., including the second shift LD Device unit 102 (1), the second shift register cell 102 (2) and second shift register cell 102 (4) etc..On the right side of Figure 13 Gate driving circuit is posted including the first shift register cell 101 (4), the first shift register cell 101 (5), the first displacement Storage unit 101 and (7) etc., including the second shift register cell 102 (3) and the second shift register cell 102 (5) etc.. Wherein, the number inside bracket can be used to indicate that shift register cell is connect with which sub-pixel.

With gate driving circuit shown in Figure 13, the first shift register cell shown in Fig. 9, shown in Fig. 10 second is moved Bit register unit, each sub- gate driving circuit that gate driving circuit includes are connect with two clock signal terminals, and at least two First clock signal terminal CLK1 of the sub- gate driving circuit connection of a cascade first shift register cell composition includes the One sub-clock signal end CLK11 and the second sub-clock signal end CLK13, at least two cascade first shift register cell groups At sub- gate driving circuit connection second clock signal end CLK2 include third sub-clock signal end CLK21 and the 4th period of the day from 11 p.m. to 1 a.m For clock signal end CLK23, the driving principle of gate driving circuit provided in an embodiment of the present invention is discussed in detail.

Figure 14 is a kind of timing diagram of each signal end of gate driving circuit provided in an embodiment of the present invention.As shown in figure 14, The second control that the timing and second control signal end CLK_B for the first control signal that first control signal end CLK_A is provided provide The timing complete complementary of signal processed.First sub-clock signal end CLK11 and the second sub-clock signal end CLK13 are successively provided and are in The clock signal of first current potential, third sub-clock signal end CLK21 and the 4th sub-clock signal end CLK23 are successively provided in The clock signal of one current potential.And the first sub-clock signal end CLK11, third sub-clock signal end CLK21, the second sub-clock signal End CLK13 and the 4th sub-clock signal end CLK23 successively provides the clock signal in the first current potential.

It is first in the current potential for the clock signal that the current potential of first control signal and the first sub-clock signal end CLK11 are provided When current potential, the grid line output that the first shift register cell 101 (1) of the first row sub-pixel connection is connected to it is in first The gate drive signal of current potential；When the current potential for the clock signal that third sub-clock signal end CLK21 is provided is the first current potential, the The grid line output that second shift register cell 102 (1) of a line sub-pixel connection is connected to it is in the grid of the first current potential Pole driving signal；When the current potential for the clock signal that the second sub-clock signal end CLK13 is provided is the first current potential, the first row sub- picture Gate driving of the grid line output in the first current potential that first shift register cell 101 (2) of element connection is connected to it is believed Number.And stops grid of the output in the first current potential in the first shift register cell 102 (1) of the first row sub-pixel connection and drive When dynamic signal, the first shift register cell 101 (2) of the first row sub-pixel connection stops the grid that output is in the first current potential Driving signal is still providing the clock letter in the first current potential after target duration, and in the second sub-clock signal end CLK13 Number when, the first shift register cell 101 (2) again again output be in the first current potential gate drive signal.Other displacements The driver' s timing of register cell is similarly.

For the gate driving circuit of display panel other side setting, driver' s timing can refer to the unilateral side of above-mentioned introduction Gate driving circuit.The timing of its corresponding first clock signal terminal can be with reference to sub-clock signal end shown in Figure 14 CLK12 and CLK14；The timing of its corresponding second clock signal end can be with reference to sub-clock signal end CLK22 shown in Figure 14 And CLK24.

The embodiment of the invention also provides a kind of display device, which may include display panel, and such as Fig. 2 Or gate driving circuit shown in Figure 13.

Wherein, the structure of the display panel can be with reference to the display panel that gate driving circuit 10 shown in Fig. 2 is connected 01 structure.Also, with reference to Fig. 2 can be seen that the gate driving circuit 10 can respectively with the first grid line in display panel G1, the second grid line G2 are connected with third grid line G3, the gate driving circuit 10 be used for as first grid line G1, the second grid line G2 and Third grid line G3 provides gate drive signal.

Optionally, which can be with are as follows: wearable device, liquid crystal display panel, Electronic Paper, oled panel, the face AMOLED Any products or components having a display function such as plate, mobile phone.Figure 15 is a kind of display device provided in an embodiment of the present invention Structural schematic diagram.As shown in figure 15, which may include: processor 1501 and memory 1502.

Processor 1501 may include one or more processing cores, such as 4 core processors, 8 core processors etc..Place Reason device 1501 can use DSP (Digital Signal Processing, Digital Signal Processing), FPGA (Field- Programmable Gate Array, field programmable gate array), PLA (Programmable Logic Array, may be programmed Logic array) at least one of example, in hardware realize.Processor 1501 also may include primary processor and coprocessor, master Processor is the processor for being handled data in the awake state, also referred to as CPU (Central Processing Unit, central processing unit)；Coprocessor is the low power processor for being handled data in the standby state.In In some embodiments, processor 1501 can be integrated with GPU (Graphics Processing Unit, image processor), GPU is used to be responsible for the rendering and drafting of content to be shown needed for display screen.In some embodiments, processor 1501 can also be wrapped AI (Artificial Intelligence, artificial intelligence) processor is included, the AI processor is for handling related machine learning Calculating operation.

Memory 1502 may include one or more computer readable storage mediums, which can To be non-transient.Memory 1502 may also include high-speed random access memory and nonvolatile memory, such as one Or multiple disk storage equipments, flash memory device.In some embodiments, the non-transient computer in memory 1502 can Storage medium is read for storing at least one instruction.

In some embodiments, display device 1500 is also optional includes: peripheral device interface 1503 and at least one outside Peripheral equipment.It can be connected by bus or signal wire between processor 1501, memory 1502 and peripheral device interface 1503.Respectively A peripheral equipment can be connected by bus, signal wire or circuit board with peripheral device interface 1503.Specifically, peripheral equipment packet It includes: radio circuit 1504, touch display screen 1505, camera 1506, voicefrequency circuit 1507, positioning component 1508 and power supply 1509 At least one of.

Peripheral device interface 1503 can be used for I/O (Input/Output, input/output) is relevant outside at least one Peripheral equipment is connected to processor 1501 and memory 1502.In some embodiments, processor 1501, memory 1502 and periphery Equipment interface 1503 is integrated on same chip or circuit board；In some other embodiments, processor 1501, memory 1502 and peripheral device interface 1503 in any one or two can be realized on individual chip or circuit board, this implementation Example is not limited this.

Radio circuit 1504 is for receiving and emitting RF (Radio Frequency, radio frequency) signal, also referred to as electromagnetic signal. Radio circuit 1504 is communicated by electromagnetic signal with communication network and other communication equipments.Radio circuit 1504 is by telecommunications Number being converted to electromagnetic signal is sent, alternatively, the electromagnetic signal received is converted to electric signal.Optionally, radio circuit 1504 include: antenna system, RF transceiver, one or more amplifiers, tuner, oscillator, digital signal processor, volume solution Code chipset, user identity module card etc..Radio circuit 1504 can by least one wireless communication protocol come with it is other Terminal is communicated.The wireless communication protocol includes but is not limited to: Metropolitan Area Network (MAN), each third generation mobile communication network (2G, 3G, 4G and 5G), WLAN and/or WiFi (Wireless Fidelity, Wireless Fidelity) network.In some embodiments, radio frequency electrical Road 1504 can also include NFC (Near Field Communication, wireless near field communication) related circuit, the application This is not limited.

Display screen 1505 is for showing UI (User Interface, user interface).The UI may include figure, text, Icon, video and its their any combination.When display screen 1505 is touch display screen, display screen 1505 also there is acquisition to exist The ability of the touch signal on the surface or surface of display screen 1505.The touch signal can be used as control signal and be input to place Reason device 1501 is handled.At this point, display screen 1505 can be also used for providing virtual push button and/or dummy keyboard, it is also referred to as soft to press Button and/or soft keyboard.In some embodiments, display screen 1505 can be one, and the front panel of display device 1500 is arranged；In In other embodiments, display screen 1505 can be at least two, be separately positioned on the different surfaces of display device 1500 or be in Foldover design；In still other embodiments, display screen 1505 can be flexible display screen, and the bending of display device 1500 is arranged in On surface or on fold plane.Even, display screen 1505 can also be arranged to non-rectangle irregular figure, namely abnormity screen.It is aobvious Display screen 1505 can use LCD (Liquid Crystal Display, liquid crystal display), OLED (Organic Light- Emitting Diode, Organic Light Emitting Diode) etc. materials preparation.

CCD camera assembly 1506 is for acquiring image or video.Optionally, CCD camera assembly 1506 includes front camera And rear camera.In general, the front panel of terminal is arranged in front camera, the back side of terminal is arranged in rear camera.In In some embodiments, rear camera at least two is that main camera, depth of field camera, wide-angle camera, focal length are taken the photograph respectively As any one in head, to realize that main camera and the fusion of depth of field camera realize background blurring function, main camera and wide Pan-shot and VR (Virtual Reality, virtual reality) shooting function or other fusions are realized in camera fusion in angle Shooting function.In some embodiments, CCD camera assembly 1506 can also include flash lamp.Flash lamp can be monochromatic temperature flash of light Lamp is also possible to double-colored temperature flash lamp.Double-colored temperature flash lamp refers to the combination of warm light flash lamp and cold light flash lamp, can be used for Light compensation under different-colour.

Voicefrequency circuit 1507 may include microphone and loudspeaker.Microphone is used to acquire the sound wave of user and environment, and It converts sound waves into electric signal and is input to processor 1501 and handled, or be input to radio circuit 1504 to realize that voice is logical Letter.For stereo acquisition or the purpose of noise reduction, microphone can be separately positioned on the different portions of display device 1500 to be multiple Position.Microphone can also be array microphone or omnidirectional's acquisition type microphone.Loudspeaker be then used for will from processor 1501 or The electric signal of radio circuit 1504 is converted to sound wave.Loudspeaker can be traditional wafer speaker, be also possible to piezoelectric ceramics Loudspeaker.When loudspeaker is piezoelectric ceramic loudspeaker, the audible sound wave of the mankind can be not only converted electrical signals to, it can also To convert electrical signals to the sound wave that the mankind do not hear to carry out the purposes such as ranging.In some embodiments, voicefrequency circuit 1507 It can also include earphone jack.

Positioning component 1508 is used for the current geographic position of locating and displaying device 1500, to realize navigation or LBS (Location Based Service, location based service).Positioning component 1508 can be the GPS based on the U.S. The dipper system of (Global Positioning System, global positioning system), China, the Gray of Russia receive this system Or the positioning component of the Galileo system of European Union.Power supply 1509 is used to be powered for the various components in display device 1500. Power supply 1509 can be alternating current, direct current, disposable battery or rechargeable battery.When power supply 1509 includes rechargeable battery When, which can support wired charging or wireless charging.Rechargeable battery can be also used for supporting fast charge technology.

In some embodiments, display device 1500 further includes having one or more sensors 1510.The one or more Sensor 1510 includes but is not limited to: acceleration transducer 1511, gyro sensor 1512, pressure sensor 1513, fingerprint Sensor 1514, optical sensor 1515 and proximity sensor 1516.

Acceleration transducer 1511 can detecte adding in three reference axis of the coordinate system established with display device 1500 Velocity magnitude.For example, acceleration transducer 1511 can be used for detecting component of the acceleration of gravity in three reference axis.Processing The acceleration of gravity signal that device 1501 can be acquired according to acceleration transducer 1511 controls touch display screen 1505 with lateral view Figure or longitudinal view carry out the display of user interface.Acceleration transducer 1511 can be also used for game or the movement number of user According to acquisition.

Gyro sensor 1512 can detecte body direction and the rotational angle of display device 1500, gyro sensor 1512 can cooperate with acquisition user to act the 3D of display device 1500 with acceleration transducer 1511.Processor 1501 is according to top The data that spiral shell instrument sensor 1512 acquires, may be implemented following function: action induction (for example changed according to the tilt operation of user Become UI), shooting when image stabilization, game control and inertial navigation.

Pressure sensor 1513 can be set under the side frame of display device 1500 and/or touch display screen 1505 Layer.When the side frame of display device 1500 is arranged in pressure sensor 1513, user can detecte to display device 1500 Signal is held, right-hand man's identification or quick behaviour are carried out according to the gripping signal that pressure sensor 1513 acquires by processor 1501 Make.It is aobvious to touching according to user by processor 1501 when the lower layer of touch display screen 1505 is arranged in pressure sensor 1513 The pressure operation of display screen 1505, realization control the operability control on the interface UI.Operability control includes button At least one of control, scroll bar control, icon control, menu control.

Fingerprint sensor 1514 is used to acquire the fingerprint of user, is collected by processor 1501 according to fingerprint sensor 1514 Fingerprint recognition user identity, alternatively, by fingerprint sensor 1514 according to the identity of collected fingerprint recognition user.Knowing Not Chu the identity of user when being trusted identity, authorize the user to execute relevant sensitive operation by processor 1501, which grasps Make to include solving lock screen, checking encryption information, downloading software, payment and change setting etc..Fingerprint sensor 1514 can be set Set the front, the back side or side of display device 1500.When being provided with physical button or manufacturer Logo in display device 1500, refer to Line sensor 1514 can be integrated with physical button or manufacturer Logo.

Optical sensor 1515 is for acquiring ambient light intensity.In one embodiment, processor 1501 can be according to light The ambient light intensity that sensor 1515 acquires is learned, the display brightness of touch display screen 1505 is controlled.Specifically, work as ambient light intensity When higher, the display brightness of touch display screen 1505 is turned up；When ambient light intensity is lower, the aobvious of touch display screen 1505 is turned down Show brightness.In another embodiment, the ambient light intensity that processor 1501 can also be acquired according to optical sensor 1515, is moved The acquisition parameters of state adjustment CCD camera assembly 1506.

Proximity sensor 1516, also referred to as range sensor are generally arranged at the front panel of display device 1500.Close to sensing Device 1516 is used to acquire the distance between the front of user Yu display device 1500.In one embodiment, work as proximity sensor 1516 when detecting that the distance between the front of user and display device 1500 gradually becomes smaller, and is touched by the control of processor 1501 aobvious Display screen 1505 is switched to breath screen state from bright screen state；When proximity sensor 1516 is detecting user and display device 1500 just When the distance between face becomes larger, touch display screen 1505 is controlled by processor 1501 and is switched to bright screen shape from breath screen state State.

It will be understood by those skilled in the art that structure shown in Figure 15 does not constitute the restriction to display device 1500, It may include perhaps combining certain components than illustrating more or fewer components or being arranged using different components.

It is apparent to those skilled in the art that for convenience and simplicity of description, the grid of foregoing description Driving circuit, shift register cell, each module and submodule specific work process, can be with reference in preceding method embodiment Corresponding process, details are not described herein.

The foregoing is merely alternative embodiments of the invention, are not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims

1. a kind of gate driving circuit, which is characterized in that for driving display panel, the display panel includes multiple pixels Group, each pixel group include two row sub-pixels, and wherein a line sub-pixel is connect with the first grid line and the second grid line, another row picture It is plain to be connect with second grid line and third grid line, and the adjacent rows sub-pixel in two neighboring pixel group shares described in one First grid line shares a third grid line；

The gate driving circuit includes: that at least two cascade first shift register cells and at least two are cascade Second shift register cell, cascade two first shift register cells respectively with first grid line and one The connection of third grid line described in item, each second shift register cell is connect with second grid line, and each displacement The grid line of register cell connection is different, and first shift register cell is used for the first grid line for being connected to it or the Three grid lines export gate drive signal, the second grid line output grid that second shift register cell is used to be connected to it Driving signal；

Wherein, the first grid line and third grid line output grid connected in first shift register cell to the first pixel group The period of driving signal, the second grid line that second shift register cell is connected to the first pixel group export grid Driving signal, and the second grid line output gate driving letter that second shift register cell is connected to the first pixel group Number duration, the first grid line and third grid line connected greater than first shift register cell to the first pixel group be defeated The total duration of gate drive signal out, the first pixel group are any one pixel group in the multiple pixel group；

The first shift register cell connecting with target grid line stops output gate drive signal target duration in object time Afterwards, continue to export gate drive signal to the target grid line, the target grid line is the first pixel group and adjacent picture The shared grid line of element group, the object time are second that second shift register cell is connected to the first pixel group At the time of grid line stops output gate drive signal, the target duration is less than second shift register cell and exports grid The duration of driving signal.

2. circuit according to claim 1, which is characterized in that first shift register cell includes: the first input Module, the first pull-up control module, the first output module, the first pull-down control module and the first pull-down module；

First input module is connect with the first input signal end, the first power end and the first pull-up node respectively, and described One input module is used for the input signal provided in response to first input signal end, and the output of the first pull-up node of Xiang Suoshu comes From the first power supply signal of first power end；

The first pull-up control module is connect with first pull-up node and the first clock signal terminal respectively, on described first The first clock for drawing control module to be used to provide in response to the current potential of first pull-up node and first clock signal terminal Signal controls the current potential of first pull-up node；

First output module respectively with first pull-up node, first clock signal terminal, first control signal end It is connected with the first output end, first output module is used for current potential and first control in response to first pull-up node The first control signal that signal end processed provides, the first output end of Xiang Suoshu export first clock signal；

First pull-down control module is respectively and under first pull-up node, second source end, third power end and first Node connection is drawn, first pull-down control module is used for current potential and the second source in response to first pull-up node The second source signal provided is provided, the first pull-down node of Xiang Suoshu third power supply signal of the output from the third power end or Person exports the second source signal；

First pull-down module is respectively and under second control signal end, initial signal end, the third power end, described first Node, first pull-up node is drawn connect with first output end, first pull-down module is in response to described the The initial signal that the current potential of one pull-down node and the initial signal end provide, the first pull-up node of Xiang Suoshu export the third Power supply signal, and the second control signal for being provided in response to the second control signal end, the first output end of Xiang Suoshu The third power supply signal is exported, the current potential of the second control signal is complementary with the current potential of the first control signal.

3. circuit according to claim 2, which is characterized in that first output module includes: output sub-module and defeated Control submodule out；

The output sub-module is connect with first pull-up node, first clock signal terminal and output node respectively, institute Output sub-module is stated for the current potential in response to first pull-up node, Xiang Suoshu output node exports the first clock letter Number；

The output control submodule connects with the output node, the first control signal end and first output end respectively It connects, the output control submodule is used in response to the first control signal, and the first output end of Xiang Suoshu exports the output Submodule is exported to the first clock signal of the output node；

First pull-down module is also connect with the 4th power end and the output node respectively, and first pull-down module is also used In the 4th power supply signal of current potential and the 4th power end offer in response to first pull-down node, saved to the output Point exports the third power supply signal.

4. circuit according to claim 3, which is characterized in that the output control submodule includes: output control crystal Pipe；

The grid of the output control transistor is connect with the first control signal end, and the first of the output control transistor Pole is connect with the output node, and the second pole of the output control transistor is connect with first output end.

5. circuit according to claim 3 or 4, which is characterized in that second shift register cell includes: second defeated Enter module, the second pull-up control module, the second output module, the second pull-down control module and the second pull-down module；

Second input module is connect with the second input signal end, first power end and the second pull-up node respectively, institute Input signal of second input module for providing in response to second input signal end is stated, the second pull-up node of Xiang Suoshu is defeated First power supply signal out；

The second pull-up control module is connect with second pull-up node and second clock signal end respectively, on described second The second clock for drawing control module to be used to provide in response to the current potential of second pull-up node and the second clock signal end Signal controls the current potential of second pull-up node；

Second output module connects with second pull-up node, the second clock signal end and second output terminal respectively Connect, second output module be used in response to second pull-up node current potential, Xiang Suoshu second output terminal output described in Second clock signal；

Second pull-down control module respectively with second pull-up node, the second source end, the third power end It is connected with the second pull-down node, second pull-down control module is used in response to the current potential of second pull-up node and described Second source signal, the second pull-down node of Xiang Suoshu exports the third power supply signal, alternatively, defeated to second pull-down node The second source signal out；

Second pull-down module respectively with the 4th power end, the initial signal end, the third power end, described Two pull-down nodes, second pull-up node are connected with the second output terminal, and second pull-down module is used in response to institute The current potential and the initial signal, the second pull-up node of Xiang Suoshu for stating the second pull-down node export the third power supply signal, with And for the current potential in response to the 4th power supply signal and second pull-down node, described in the output of Xiang Suoshu second output terminal Third power supply signal.

6. circuit according to claim 5, which is characterized in that the first pull-up control module and the second pull-up control Molding block includes: pull-up control submodule and pull-up submodule；

The pull-up control submodule is connect with target pull-up node, target control node and target clock signal end respectively, institute Pull-up control submodule is stated for the current potential in response to the target pull-up node, the output of Xiang Suoshu target control node comes from institute State the target clock signal at target clock signal end, the pull-up submodule respectively with the target control node, the target Clock signal terminal is connected with the target pull-up node, and the pull-up submodule is used for the electricity in response to the target control node Position, Xiang Suoshu target pull-up node export the target clock signal, and target pull-down module is connect with the target control node, The target pull-down module is used for the current potential in response to target pull-down node, and Xiang Suoshu target control node exports the third electricity Source signal；

Alternatively, the pull-up control submodule respectively with the target pull-up node, first object control node and the second target Control node connection, the pull-up control submodule are used for the current potential in response to the target pull-up node, control described first The on off operating mode of target control node and the second target control node, the pull-up submodule are controlled with the first object respectively Node, second target control node, target clock signal end are connected with the target pull-up node, the pull-up submodule For in the first object control node and the conducting of the second target control node, the output of Xiang Suoshu target pull-up node to be come from The target clock signal at the target clock signal end, target pull-down module is connect with second target control node, described Target pull-down module is used for the current potential in response to target pull-down node, and the second target control node of Xiang Suoshu exports the third electricity Source signal；

Wherein, the corresponding target pull-up node of first shift register cell is first pull-up node, target control Node is the first control node, and target clock signal end is first clock signal terminal, and target pull-down module is described first Pull-down module, target pull-down node are first pull-down node, and first object control node is first object node, the second mesh Mark control node is the second destination node；

The corresponding target pull-up node of second shift register cell is second pull-up node, target control node is Second control node, target clock signal end are the second clock signal end, and target pull-down module is the described second lower drawing-die Block, target pull-down node are second pull-down node, and first object control node is third destination node, the second target control Node is the 4th destination node.

7. circuit according to claim 6, which is characterized in that

It is connect respectively with target pull-up node, target control node and target clock signal end in the pull-up control submodule, The pull-up submodule is connect with the target control node, the target clock signal end and the target pull-up node respectively When, the pull-up control submodule includes: pull-up control transistor, and the pull-up submodule includes: first to pull up transistor, institute State pull-up control transistor grid connect with the target pull-up node, it is described pull up control transistor the first pole with it is described Second pole of the connection of target clock signal end, the pull-up control transistor is connect with the target control node, and described first The grid to pull up transistor is connect with the target control node, when the described first the first pole to pull up transistor is with the target The connection of clock signal end, the described first the second pole to pull up transistor is connect with the target pull-up node；

The pull-up control submodule respectively with the target pull-up node, first object control node and the second target control Node connection, the pull-up submodule respectively with the first object control node, second target control node, target when When clock signal end is connected with the target pull-up node, the pull-up submodule further include: second pulls up transistor, and it is described on The grid of control transistor is drawn to connect with the target pull-up node, the first pole and described first of the pull-up control transistor Second pole of target control node connection, the pull-up control transistor is connect with second target control node, and described the One grid to pull up transistor is connect with the first object control node, the described first the first pole to pull up transistor with it is described Second the second pole connection to pull up transistor, the described first the second pole to pull up transistor are connect with the target pull-up node, Described second grid to pull up transistor is connect with second target control node, the described second the first pole to pull up transistor It is connect with the target clock signal end.

8. circuit according to claim 7, which is characterized in that first input module includes: the first input transistors, Second input module includes: the second input transistors；

The grid of first input transistors is connect with first input signal end, the grid of second input transistors It is connect with second input signal end, the first of first input transistors and second input transistors is extremely and institute The connection of the first power end is stated, the second pole of first input transistors is connect with first pull-up node, and described second is defeated The second pole for entering transistor is connect with second pull-up node；

First pull-down control module include: the first drop-down control transistor and second drop-down control transistor, described second Pull-down control module includes: third drop-down control transistor and the 4th drop-down control transistor；

The grid and the of the grid of the first drop-down control transistor and the first pole and third drop-down control transistor One extremely connect with the second source end, and the grid of the second drop-down control transistor and first pull-up node connect It connects, the grid of the 4th drop-down control transistor is connect with second pull-up node, the first drop-down control transistor The second pole and the second drop-down control transistor second extremely connect with first pull-down node, the third pulls down It controls the second pole of transistor and the second of the 4th drop-down control transistor extremely connect with second pull-down node, institute State the second drop-down control transistor the first pole and it is described 4th drop-down control transistor first extremely with the third power supply End connection；

First pull-down module includes: under the first pull-down transistor, the second pull-down transistor, third pull-down transistor, the 4th Pull transistor, the 5th pull-down transistor and the 6th pull-down transistor, second pull-down module include: the 7th pull-down transistor, 8th pull-down transistor, the 9th pull-down transistor, the tenth pull-down transistor and the 11st pull-down transistor；

The grid of first pull-down transistor, second pull-down transistor and the third pull-down transistor is with described The connection of one pull-down node, the grid and the initial signal end of the 4th pull-down transistor and the tenth pull-down transistor connect It connects, the grid of the 5th pull-down transistor is connect with the second control signal end, the 6th pull-down transistor and described The grid of 11st pull-down transistor is connect with the 4th power end, the 7th pull-down transistor, the 8th lower crystal pulling The grid of body pipe and the 9th pull-down transistor is connect with second pull-down node, first pull-down transistor to institute State the 11st pull-down transistor first extremely connect with the third power end, first pull-down transistor and the described 4th Second pole of pull-down transistor is connect with first pull-up node, the second pole of second pull-down transistor and described first Control node connection, the second pole and the output node of the third pull-down transistor and the 6th pull-down transistor connect It connects, the second pole of the 5th pull-down transistor is connect with first output end, the 7th pull-down transistor and described Second pole of ten pull-down transistors is connect with second pull-up node, the second pole of the 8th pull-down transistor and described the Second pole of the connection of two control nodes, the 9th pull-down transistor and the 11st pull-down transistor and second output End connection；

First output module includes: the first output transistor, first capacitor device and output control transistor, and described second is defeated Module includes: the second output transistor and the second capacitor out；

The grid of first output transistor is connect with first pull-up node, the first pole of first output transistor It being connect with first clock signal terminal, the second pole of first output transistor is connect with the output node, and described One end of one capacitor is connect with first pull-up node, and the other end is connect with the output node, and the output control is brilliant The grid of body pipe is connect with the first control signal end, and the first pole of the output control transistor and the output node connect Connect, the second pole of the output control transistor is connect with first output end, the grid of second output transistor with The second pull-up node connection, the first pole of second output transistor is connect with the second clock signal end, described Second pole of the second output transistor is connect with the second output terminal, one end of second capacitor and second pull-up Node connection, the other end are connect with the second output terminal.

9. a kind of driving method of gate driving circuit, which is characterized in that as described in any of the claims 1 to 8 for driving Gate driving circuit, which comprises

The first grid line or third grid line that at least two cascade first shift register cells are successively connected to it export grid Pole driving signal, the second grid line output grid that at least two cascade second shift register cells are successively connected to it drive Dynamic signal；

Wherein, the first grid line and third grid line output grid connected in first shift register cell to the first pixel group The period of driving signal, the second grid line that second shift register cell is connected to the first pixel group export grid Driving signal, and the second grid line output gate driving letter that second shift register cell is connected to the first pixel group Number duration, the first grid line and third grid line connected greater than first shift register cell to the first pixel group be defeated The total duration of gate drive signal out, the first pixel group are any one picture in multiple pixel groups that display panel includes Plain group；

10. a kind of display device, which is characterized in that the display device includes: display panel, and such as claim 1 to 8 times Gate driving circuit described in one；

The display panel includes multiple pixel groups, and each pixel group includes two row sub-pixels, wherein a line sub-pixel and first Grid line and the connection of the second grid line, another row sub-pixel is connect with second grid line and third grid line, and two neighboring pixel group In adjacent rows sub-pixel share first grid line or share a third grid line, the gate driving circuit It is connect respectively with first grid line, second grid line and the third grid line, the gate driving circuit is used for described First grid line, second grid line and the third grid line provide gate drive signal.