CN110489053B - Method for managing flash memory module, related flash memory controller and electronic device - Google Patents
Method for managing flash memory module, related flash memory controller and electronic device Download PDFInfo
- Publication number
- CN110489053B CN110489053B CN201810736859.7A CN201810736859A CN110489053B CN 110489053 B CN110489053 B CN 110489053B CN 201810736859 A CN201810736859 A CN 201810736859A CN 110489053 B CN110489053 B CN 110489053B
- Authority
- CN
- China
- Prior art keywords
- data page
- flash memory
- target block
- valid data
- page
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
Abstract
The invention discloses a method for managing a flash memory module, a related flash memory controller and an electronic device, wherein the method comprises the following steps: when the flash memory module is powered on and has a garbage collection operation not completed before the flash memory module is powered on: performing a binary search on a target block to determine a first blank data page of the target block; sequentially reading the first blank data page to determine the last valid data page of the target block; and according to the last valid data page, the garbage collection operation is carried out again. The invention determines the last valid data page by reading the first blank data page forward in sequence, and has higher efficiency and processing speed compared with the prior art which needs to search a plurality of data pages to determine the last valid data page of the target block.
Description
Technical Field
The present invention relates to flash memory, and more particularly, to a method for managing a flash memory module, and a related flash memory controller and an electronic device.
Background
In some accesses of flash memory modules, the flash memory controller writes data from the host device into Single-Level Cell (SLC) blocks of the flash memory modules, and then moves valid data in the Single-Level blocks to a target block by garbage collection (TLC) operation, wherein the target block may be a Multi-Level Cell (TLC) block or a Triple-Level Cell (TLC) block. However, if a Power Off Recovery (POR) or a power off recovery (SPOR) condition occurs during the garbage collection process, after the flash memory module is powered up again, the first valid data page in the target block needs to be searched, and the garbage collection operation is restarted according to the determined degree of the previous garbage collection operation. However, searching for the first valid data page in the target block usually requires searching for many data pages, which results in slow searching speed and reduced performance and stability of the flash memory controller.
Disclosure of Invention
Therefore, one of the objectives of the present invention is to design a method for managing a flash memory module, which can quickly determine the first valid data page in the target block under the condition of only searching few data pages, so as to solve the problems in the prior art.
In one embodiment of the present invention, a method for managing a flash memory module is disclosed, comprising the steps of: when the flash memory module is powered on and has an incomplete garbage collection operation before the flash memory module is powered on: performing binary search on a target block to determine a first blank data page of the target block; sequentially reading the first blank data page to determine the last valid data page of the target block; and according to the last valid data page, the garbage collection operation is carried out again.
In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used for accessing a flash memory module, and the flash memory controller comprises a read only memory and a microprocessor, wherein the read only memory is used for storing a program code, and the microprocessor is used for executing the program code to control the access to the flash memory module. In operation of a flash memory controller, when the flash memory module is powered on and has an unfinished garbage collection operation before the flash memory module is powered on, the microprocessor performs a binary search on a target block to determine a first blank data page of the target block, sequentially reads the first blank data page forward to determine a last valid data page of the target block, and performs the garbage collection operation again according to the last valid data page.
In another embodiment of the present invention, an electronic device is disclosed, which includes a flash memory module and a flash memory controller. When the flash memory module is powered on and has unfinished garbage collection operation before the flash memory module is powered on, the flash memory controller performs binary search on a target block to determine a first blank data page of the target block, reads the first blank data page forward in sequence to determine a last valid data page of the target block, and performs the garbage collection operation again according to the last valid data page.
Drawings
FIG. 1 is a diagram illustrating a memory device according to an embodiment of the invention.
FIG. 2 is a flow chart of managing flash memory modules according to an embodiment of the invention.
FIG. 3 is a diagram illustrating the process of garbage collection to move valid data in source blocks to target blocks.
FIG. 4 is a flowchart of finding a first blank page of data in a target block according to an embodiment of the invention.
FIG. 5 is a diagram illustrating a first blank page of data in a target block being sequentially read to determine a last valid page of data in the target block according to an embodiment of the invention.
Wherein the reference numerals are as follows:
100 memory device
110 flash memory controller
112 microprocessor
112C program code
112M read-only memory
114 control logic
116 buffer memory
118 interface logic
120 flash memory module
130 master device
132 encoder
134 decoder
200 to 210, 402 to 428
310_1 to 310_ n source blocks
320_1, 320_2 target Block
P0-P (N) data page
Detailed Description
FIG. 1 is a diagram of a memory device 100 according to an embodiment of the invention. The Memory device 100 includes a Flash Memory (Flash Memory) module 120 and a Flash Memory controller 110, and the Flash Memory controller 110 is used for accessing the Flash Memory module 120. According to the present embodiment, the flash Memory controller 110 includes a microprocessor 112, a Read Only Memory (ROM) 112M, a control logic 114, a buffer 116, and an interface logic 118. The ROM 112M is used for storing a program code 112C, and the microprocessor 112 is used for executing the program code 112C to control Access (Access) to the flash memory module 120. The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used for encoding the data written into the flash memory module 120 to generate a corresponding check Code (or Error Correction Code), ECC, and the decoder 134 is used for decoding the data read from the flash memory module 120.
Typically, the flash memory module 120 includes a plurality of flash memory chips, each of which includes a plurality of blocks (blocks), and the flash memory controller 110 performs the erase data operation on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of pages (pages), wherein the flash memory controller 110 writes data to the flash memory module 120 in units of pages. In the present embodiment, the flash memory module 120 is a three-dimensional NAND-type flash memory (3D NAND-type flash) module.
In practice, the flash controller 110 executing the program code 112C via the microprocessor 112 can utilize its internal components to perform various control operations, such as: the control logic 114 is used to control the access operations of the flash memory module 120 (especially the access operations to at least one block or at least one data page), the buffer memory 116 is used to perform the required buffering, and the interface logic 118 is used to communicate with a Host Device 130. The buffer Memory 116 is implemented by a Random Access Memory (RAM). For example, the buffer memory 116 may be a Static random access memory (Static RAM, SRAM), but the invention is not limited thereto.
In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card conforming to SD/MMC, CF, MS, XD standards), and the host device 130 is an electronic device capable of connecting to the memory device, such as a mobile phone, a notebook computer, a desktop computer …, etc. In another embodiment, the memory device 100 may be a solid state disk or an Embedded Storage device conforming to the standard of Universal Flash Storage (UFS) or Embedded Multimedia Memory Card (EMMC) for being disposed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.
Referring to FIG. 2, a flowchart of managing a flash memory module 120 according to an embodiment of the invention is shown. In step 200, the process begins. In step 202, the flash controller 110 performs a garbage collection operation on the flash memory module 120 to release the block for subsequent use. Specifically, referring to fig. 3, it is assumed that the flash memory module 120 includes a plurality of source blocks 310_1 to 310_ n and a plurality of target blocks 320_1 and 320_2, wherein the source blocks 310_1 to 310_ n may be single-layer storage blocks, and the target blocks 320_1 and 320_2 may be multi-layer storage blocks or three-layer storage blocks. In the operation of the memory device 100, when the flash controller 110 receives a write command from the host 130, the data is written into the source blocks 310_1 to 310_ n in sequence, and since the written data may become invalid data partially due to subsequent data update, when the number of the remaining blocks available for writing in the source blocks 310_1 to 310_ n is not large, the flash controller 110 will move the valid data in the source blocks 310_1 to 310_ n to the target blocks 320_1 and 320_2, so as to release the source blocks 310_1 to 310_ n for subsequent use. The operation is referred to as a garbage collection operation, however, the triggering condition of the garbage collection operation is not limited to the case that the number of the remaining blocks available for writing in the source blocks 310_ 1-310 _ n is insufficient, for example, the triggering condition may be the case that the data quality of some source blocks 310_ 1-310 _ n is not good or the wear leveling technique is considered. Since a person skilled in the art should understand the operation content of the garbage collection operation, the related details are not described herein.
In step 204, during the process that the flash controller 110 sequentially moves the valid data in the source blocks 310_ 1-310 _ n to the target blocks 320_1, 320_2, a power-off recovery (POR) or a burst power-off recovery (SPOR) occurs, i.e., the garbage collection operation is suddenly terminated due to the power-off before the garbage collection operation is completed, and the memory device 100 is then powered on again.
In step 206, after the memory device 100 is powered back up, the flash memory controller 110 determines whether the memory device 100 has been abnormally powered down. Specifically, when the memory device 100 is normally powered off, the flash memory controller 100 stores the temporary tables and data stored in the buffer memory 116 into the flash memory module 120, and includes a flag (flag) for indicating whether the memory device 100 is normally powered off, so that the flash memory controller 110 can read the tag stored in the flash memory module 120 to determine whether the memory device 100 has been previously subjected to an abnormal power failure, for example, when the tag is not set correctly, it is determined that the abnormal power failure has been previously encountered. In the present embodiment, the memory device 100 is subject to abnormal power failure.
Then, when the flash controller 110 determines that there is an abnormal power-off condition and there is a garbage collection operation that has not been completed, the flash controller 110 performs a binary search on the target block (taking the target block 320_1 as an example for the following description) that was written before the power-off recovery or the recovery after the power-off burst (to find the first blank data page in the target block 320_ 1). Specifically, referring to the flowchart shown in fig. 4, the process of finding the first blank page of data in the target block 320_1 is as follows.
Step 402: the search range (R) and the first data page number (P ═ N/2) are determined according to the total data page number (N) of the target block 320_1, and the search direction is forward (D ═ 2, i.e. the direction in which the data page number increases).
Step 404: the spare area (spare region) of the data page (P) is read.
Step 406: whether the data page (P) is a blank data page is determined according to the content in the spare area, for example, whether the data page (P) is a blank data page may be determined according to whether the spare area records related metadata (metadata). If the data page (P) is determined to be a blank data page, the process proceeds to step 408; if the data page (P) is determined not to be a blank data page, the process proceeds to step 410.
Step 408: the data page number of the next search is set to (P ═ P- (R/2)), and the search direction is backward (D ═ 1, i.e., the direction in which the data page number is decremented).
Step 410: the next data page number to be searched is set as (P ═ P + (R/2)), and the search direction is forward (D ═ 2).
Step 412: judging whether the search range (R) is 1, if not, the flow goes to step 414; if so, flow proceeds to block 416.
Step 414: the search range is halved (R ═ R/2), and flow returns to step 404.
Step 416: judging whether the searching direction is backward (D; if so, flow proceeds to block 424.
Step 418: judging whether the data page (P) searched currently is the last data page (N), if yes, the process goes to step 420; if not, flow proceeds to block 422.
Step 420: all data pages of the target block 320_1 are determined to have write data, i.e., the target block 320 has no blank data pages.
Step 422: the data page (P +1) is determined to be the first blank data page of the target block 320_ 1.
Step 424: determining whether the currently searched data page (P) is smaller than a threshold value (in this embodiment, "4"), if yes, the process proceeds to step 426; if false, flow proceeds to step 428.
Step 426: since the valid data page of the target block 320_1 is too low, all the contents of the target block 320_1 are discarded.
Step 428: the data page (P) is determined to be the first blank data page of the target block 320_ 1.
After determining the first blank page, the flash controller 110 reads the first blank page forward in sequence to determine the last valid page of the target block 320_1, and performs garbage collection again according to the last valid page. Specifically, referring to fig. 5, assuming that the first blank page of the target block 320_1 determined by the flash controller 110 is P102, the flash controller 110 first reads the content of the page P101 to determine whether the quality thereof meets a criterion, and determines the page P101 as a valid page if the quality thereof meets the criterion, and determines the page P as an invalid page if the quality thereof does not meet the criterion. For example, the decoder 134 performs a decoding operation (including an error correction operation) on the content of the data page P101 to determine whether the data page P101 can be successfully read (i.e., the decoding operation can be correctly completed), and determines that the data page P101 is a valid data page if the data page P101 can be successfully read, and determines that the data page P101 is an invalid data page if the data page P101 cannot be successfully read. In another example, the criterion may be that the number or proportion of error bits of the data page P101 is lower than a threshold value.
In the present embodiment, the data page P101 is an invalid data page, so the flash controller 110 continues to read the content of the data page P100 to determine whether the quality meets the criteria. In the embodiment, the data page P100 is also an invalid data page, so the flash controller 110 continues to read the content of the data page until the quality meets the standard. In the present embodiment, since the data page P99 is the first data page determined to be of quality meeting the criteria, the data page P99 is determined to be the last valid data page of the target block 320_1, and the flash controller 110 stops reading the data page forward.
After determining the last valid data page P99 of the target block 320_1, the flash controller 110 reads the spare area of the data page P99 to obtain the data page of the corresponding source block, and performs the garbage collection operation again. For example, assuming that the spare area in the data page P99 records that the data in the data page P99 is read from the 13 th data page of the source block 310_3, the flash controller 110 can write all the remaining data pages P102-P (n) of the target block 320_1 with dummy data (dummy data) to maintain the stability of the target block 320_1, and restart the garbage collection operation to sequentially copy the valid data from the 14 th data page of the source block 310_3 to the target block 320_ 2.
As mentioned above, when the memory device 100 has been abnormally powered off and has not completed the garbage collection operation, the flash memory controller 110 uses binary search to quickly find the first blank data page in a target block, and then reads the first blank data page forward in sequence to determine the last valid data page of the target block for performing the garbage collection operation again. Therefore, compared to the prior art that needs to search many data pages to determine the last valid data page of the target block, the present invention has higher efficiency and processing speed.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A method of managing a flash memory module, comprising:
when the flash memory module is powered on and has a garbage collection operation not completed before the flash memory module is powered on:
performing a binary search on a target block to determine a first blank data page of the target block;
sequentially reading the first blank data page to determine the last valid data page of the target block; and
performing the garbage collection operation again according to the last valid data page;
wherein the step of performing a binary search on the target block to determine the first blank page of data of the target block comprises:
judging whether the searched data page is a blank data page or not according to the information in a spare area of the searched data page; and
wherein the step of resuming the garbage collection operation according to the last valid data page comprises:
according to a source block recorded by the last valid data page and data page information in the source block, performing the garbage collection operation again to move data in the source block to another target block; or
When the sequence number of the last valid data page is lower than a threshold value, discarding the contents of all valid data pages in the target block, and performing the garbage collection operation again to move the valid data in at least one source block to another target block, wherein the valid data in the at least one source block comprises the contents of all valid data pages in the target block.
2. The method of claim 1, wherein the step of sequentially reading from the first blank page of data to determine the last valid page of data of the target block comprises:
the first blank data page is sequentially read until the quality of the read data page meets a standard, and the first data page which meets the standard is taken as the last valid data page.
3. The method of claim 2, wherein the criterion is whether the contents of the data page can be correctly read or whether the number or proportion of erroneous bits of the data page is below a threshold.
4. A flash memory controller for accessing a flash memory module, the flash memory controller comprising:
a read-only memory for storing a program code; and
a microprocessor for executing the program code to control access to the flash memory module;
when the flash memory module is powered on and has an unfinished garbage collection operation before the flash memory module is powered on, the microprocessor carries out binary search on a target block to determine a first blank data page of the target block, reads the first blank data page forward in sequence to determine a last valid data page of the target block, and carries out the garbage collection operation again according to the last valid data page;
the microprocessor judges whether the searched data page is a blank data page according to the information in a spare area of the searched data page;
the microprocessor performs the garbage collection operation again according to a source block recorded by the last valid data page and data page information in the source block so as to move data in the source block to another target block; or when the sequence number of the last valid data page is lower than a threshold value, discarding the contents of all valid data pages in the target block, and performing the garbage collection operation again to move the valid data in at least one source block to another target block, wherein the valid data in the at least one source block comprises the contents of all valid data pages in the target block.
5. An electronic device, comprising:
a flash memory module; and
a flash memory controller for accessing the flash memory module;
when the flash memory module is powered on and has unfinished garbage collection operation before the flash memory module is powered on, the flash memory controller carries out binary search on a target block to determine a first blank data page of the target block, reads the first blank data page forward in sequence to determine a last valid data page of the target block, and carries out the garbage collection operation again according to the last valid data page;
the flash memory controller judges whether the searched data page is a blank data page according to the information in a spare area of the searched data page;
the flash memory controller performs the garbage collection operation again according to a source block recorded by the last valid data page and data page information in the source block so as to move data in the source block to another target block; or when the sequence number of the last valid data page is lower than a threshold value, discarding the contents of all valid data pages in the target block, and performing the garbage collection operation again to move the valid data in at least one source block to another target block, wherein the valid data in the at least one source block comprises the contents of all valid data pages in the target block.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107116218 | 2018-05-14 | ||
| TW107116218A TWI670598B (en) | 2018-05-14 | 2018-05-14 | Method for managing flash memory module and associated flash memory controller and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110489053A CN110489053A (en) | 2019-11-22 |
| CN110489053B true CN110489053B (en) | 2022-09-23 |
Family
ID=68544896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810736859.7A Active CN110489053B (en) | 2018-05-14 | 2018-07-06 | Method for managing flash memory module, related flash memory controller and electronic device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110489053B (en) |
| TW (1) | TWI670598B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113885791A (en) * | 2021-09-08 | 2022-01-04 | 北京维普无限智能技术有限公司 | Data writing method, reading method and device of Flash memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105683898A (en) * | 2014-01-17 | 2016-06-15 | 网络装置公司 | Set-associative hash table organization for efficient storage and retrieval of data in a storage system |
| CN105895160A (en) * | 2015-02-13 | 2016-08-24 | 桑迪士克科技有限责任公司 | Boundary Word Line Search and Open Block Read Methods with Reduced Read Disturb |
| CN107068186A (en) * | 2015-12-15 | 2017-08-18 | 三星电子株式会社 | The method of operating memory device |
| CN107112047A (en) * | 2015-01-23 | 2017-08-29 | 桑迪士克科技有限责任公司 | Partial Block for block program in the nonvolatile memory is wiped |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9396103B2 (en) * | 2007-06-08 | 2016-07-19 | Sandisk Technologies Llc | Method and system for storage address re-mapping for a memory device |
| US8626989B2 (en) * | 2011-02-02 | 2014-01-07 | Micron Technology, Inc. | Control arrangements and methods for accessing block oriented nonvolatile memory |
| US8595415B2 (en) * | 2011-02-02 | 2013-11-26 | Micron Technology, Inc. | At least semi-autonomous modules in a memory system and methods |
| TWI457757B (en) * | 2011-12-01 | 2014-10-21 | Silicon Motion Inc | Method for controlling a memory array of a flash memory, and a flash memory using the same |
| KR102593178B1 (en) * | 2016-08-19 | 2023-10-25 | 에스케이하이닉스 주식회사 | Memory device, memory system having the same, and operating method thereof |
-
2018
- 2018-05-14 TW TW107116218A patent/TWI670598B/en active
- 2018-07-06 CN CN201810736859.7A patent/CN110489053B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105683898A (en) * | 2014-01-17 | 2016-06-15 | 网络装置公司 | Set-associative hash table organization for efficient storage and retrieval of data in a storage system |
| CN107112047A (en) * | 2015-01-23 | 2017-08-29 | 桑迪士克科技有限责任公司 | Partial Block for block program in the nonvolatile memory is wiped |
| CN105895160A (en) * | 2015-02-13 | 2016-08-24 | 桑迪士克科技有限责任公司 | Boundary Word Line Search and Open Block Read Methods with Reduced Read Disturb |
| CN107068186A (en) * | 2015-12-15 | 2017-08-18 | 三星电子株式会社 | The method of operating memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201947407A (en) | 2019-12-16 |
| TWI670598B (en) | 2019-09-01 |
| CN110489053A (en) | 2019-11-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109634517B (en) | Method for performing access management, memory device, electronic device and controller thereof | |
| CN109871333B (en) | Method for accessing flash memory module, related flash memory controller and electronic device | |
| TWI650644B (en) | Method for managing flash memory module and related flash memory controller and electronic device | |
| CN110058795B (en) | Method for managing flash memory module, related flash memory controller and electronic device | |
| US10866751B2 (en) | Method for managing flash memory module and associated flash memory controller | |
| US11204864B2 (en) | Data storage devices and data processing methods for improving the accessing performance of the data storage devices | |
| CN109697170B (en) | Method for accessing flash memory module, related flash memory controller and electronic device | |
| CN110633047A (en) | Method for managing flash memory module, related flash memory controller and electronic device | |
| CN111475425A (en) | Method for managing flash memory module and related flash memory controller and electronic device | |
| US11372578B2 (en) | Control method for flash memory controller and associated flash memory controller and memory device | |
| US10776265B2 (en) | Data storage devices and data processing methods | |
| US11487475B2 (en) | Control method for referring to expired block table to perform expired block recycling operation and associated flash memory controller and memory device | |
| CN111399751A (en) | Flash memory controller, method for managing flash memory module and related electronic device | |
| US11194502B1 (en) | Electronic device, flash memory controller and method for performing garbage collection operation on flash memory module | |
| CN111984462B (en) | Pre-warning-free power-off restoration management method, memory device, controller and electronic device | |
| CN110489053B (en) | Method for managing flash memory module, related flash memory controller and electronic device | |
| US11216381B2 (en) | Data storage devices and data processing methods | |
| TWI657339B (en) | Method for managing flash memory module and associated flash memory controller | |
| CN111159069A (en) | Flash memory controller, method for managing flash memory module and related electronic device | |
| US11307786B2 (en) | Data storage devices and data processing methods | |
| TWI653630B (en) | Method for accessing flash memory module and related flash memory controller and electronic device | |
| CN116954489A (en) | Method for accessing a flash memory module, flash memory controller and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |