CN110471336A - The servo control system realized based on Verilog - Google Patents

The servo control system realized based on Verilog Download PDF

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Publication number
CN110471336A
CN110471336A CN201910712721.8A CN201910712721A CN110471336A CN 110471336 A CN110471336 A CN 110471336A CN 201910712721 A CN201910712721 A CN 201910712721A CN 110471336 A CN110471336 A CN 110471336A
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CN
China
Prior art keywords
verilog
fpga
control system
module
servo
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Pending
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CN201910712721.8A
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Chinese (zh)
Inventor
李智
梅杰
郭梦原
王琴
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Shanghai Jiaotong University
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Shanghai Jiaotong University
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Priority to CN201910712721.8A priority Critical patent/CN110471336A/en
Publication of CN110471336A publication Critical patent/CN110471336A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25257—Microcontroller

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electric Motors In General (AREA)
  • Feedback Control In General (AREA)

Abstract

The present invention provides a kind of servo control systems realized based on Verilog, comprising: FPGA: realizing whole control algolithms by Verilog language；Driving plate: connection servo motor and the FPGA, to drive servo motor according to the control signal of FPGA and transmit motor feedback signals to the FPGA；ADC: the analog-to-digital conversion of three-phase current.The present invention enables the system to realize by Verilog using many algorithms, including Cordic algorithm, PI difference control algolithm, a variety of quantization schemes etc.；The present invention makes the more optimized realization of system using algorithm, including M T method test the speed, SVPWM algorithm etc..The present invention reduces resource consumption, lifting system performance, so that servo-system is implemented as possibility in domestic FPGA.Completely without the participation of digital signal processing chip, while guaranteeing to control precision, so that system performance maximizes.

Description

The servo control system realized based on Verilog
Technical field
The present invention relates to Serve Motor Control fields, and in particular, to a kind of servo motor control realized based on Verilog System processed.
Background technique
Servo motor can accurately control present speed and position, have in current automatic control system extremely important Application.Magnetic field steering control (FOC) algorithm becomes current servo with the dynamic response of its high control precision and high speed First choice in motor control algorithms.
Since the realization of magnetic field steering control (FOC) algorithm is complex, current most of hardware realization is all base It is completed in digital signal processing chip (DSP), though there are some schemes based on programmable gate array (FPGA), or with DSP collaboration is completed, or is embedded soft core using FPGA and executed.Such as the patent of Publication No. CN104808582A discloses one kind Embedded digital controller and its control method based on FPGA, including embedded multi-core control system, signal detection module, view Feel tracking module, pulse output photoelectric isolation module, simulation control module, the output end and vision of signal detection module track mould The output end of block is connect with the input terminal of embedded multi-core control system respectively, the output end difference of embedded multi-core control system It is connect with the input terminal of pulse output photoelectric isolation module and the input terminal for simulating control module, pulse output photoelectric isolation module Output end connect with servo-driver, the output end for simulating control module is connect with air pump.
The implementation of pure Verilog, since technical difficulty is larger, still in miss status.Recent domestic FPGA is gradually It rises, but without the demand that the servo-system for integrating soft nuclear resource, therefore producing pure Verilog is realized.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of servo motors realized based on Verilog Control system.
A kind of servo control system realized based on Verilog provided according to the present invention, comprising:
FPGA: whole control algolithms are realized by Verilog language；
Driving plate: the connection servo motor and FPGA, to according to the control signal of FPGA drive servo motor and Motor feedback signals are transmitted to the FPGA.
Analog-digital converter: being converted to digital value for the three-phase current analogue value in motor feedback signals, is transmitted to described Operation is carried out in FPGA.
Preferably, the motor feedback signals include: three-phase current signal and quadrature coding pulse signal.
Preferably, the FPGA includes:
Decoder module: parameter of electric machine calculating is carried out according to the quadrature coding pulse signal, obtains the position of servo motor And velocity information；
FOC module: according to the servo motor position and velocity information, calculate duty ratio corresponding PWM waveform, pass Transport to the driving plate；
Interface module: it is communicated to connect with the end PC, the servo motor position and velocity information is transmitted to the end PC, PC is commented at end Estimate the superiority and inferiority of servo-system.
Preferably, the decoder module includes:
Speed calculates: using M T method, while recording code-disc output pulse and high-frequency clock pulse, between M method and T method Switching is to obtain accurate results；
Position calculates: calculating current location by counting the quadrature coding pulse signal.
Preferably, the FOC module includes:
Clarke conversion module, Park conversion module and iPark transformation: being coordinate transform, wherein trigonometric function calculates It is realized using Cordic algorithm；
PI controller: it adjusts algorithm and is realized so that motor is faster stable using difference form.
SVPWM module: calculating PWM waveform duty ratio, exports PWM waveform.
Preferably, the interface module uses serial line interface, baud rate 115200.
Preferably, the three-phase current signal of the driving plate output is analog signal, passes through external analog-digital converter The FPGA is inputted after being converted to digital signal.
Preferably, the quantity of the servo motor is one or more.
Preferably, the driving plate main control chip type selecting IR2136, built-in power driving and current acquisition electricity in driving plate Road.
Preferably, each module in the FPGA has carried out quantification treatment.
Compared with prior art, the present invention have it is following the utility model has the advantages that
1, the pure Veri log that the present invention realizes servo-system is realized, reduction resource consumption, lifting system performance, so that Servo-system is implemented as possibility in domestic FPGA.
2, completely without the participation of digital signal processing chip (DSP), while guaranteeing to control precision, so that system Performance maximizes.
3. the present invention is comprehensive to use a variety of optimization algorithms to enable the system to realize by Verilog, comprising: Cordic algorithm, difference PI algorithm etc. greatly reduce hardware resource consumption under the premise of loss precision is limited.
4. the present invention use many algorithms, the realization of optimization system, comprising: M T method effectively expand the range that tests the speed, SVPWM Method reduces devices switch loss, promotes voltage utilization efficiency etc..
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention, Objects and advantages will become more apparent upon:
Fig. 1 is overall structure diagram of the invention；
Fig. 2 is FOC algorithm block diagram.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention Protection scope.
As shown in Figure 1, a kind of servo control system realized based on Verilog provided by the invention, comprising:
FPGA: whole control algolithms are realized by Verilog language；
Driving plate: connection servo motor and FPGA, to according to the control signal of FPGA drive servo motor and to FPGA transmits motor feedback signals.Motor feedback signals include: three-phase current signal and quadrature coding pulse signal.
Analog-digital converter: the three-phase current analogue value is converted into digital value, is transmitted in the FPGA and carries out operation.
Quantification treatment has been carried out to each module of FPGA during Verilog is realized, it can be in loss of significance Under the premise of minimum, hardware resource consumption is greatly reduced.
FPGA includes:
Decoder module: according to quadrature coding pulse signal carry out parameter of electric machine calculating, obtain servo motor position and Velocity information.
FOC module: according to the servo motor position and velocity information, calculate appropriate duty ratio PWM waveform, pass Transport to the driving plate.
Interface module: communicating to connect with the end PC, the servo motor position and velocity information is transmitted to the end PC, the end PC will Information shows and assesses the superiority and inferiority of servo-system.Interface module uses Universal Serial Interface (UART).
FOC module includes:
Clarke conversion module, Park conversion module and iPark transformation: being coordinate transform, real using Cordic algorithm It is existing；Under the premise of guaranteeing precision, hardware resource consumption is greatly reduced.
PI controller: being realized using difference form, under the premise of loss of significance is controllable, successfully with Verilog hard Identical function is realized on part.
SVPWM module: generating the impulse wave of appropriate duty ratio, while reducing devices switch loss, than traditional SPWM voltage utilization efficiency is higher by 15%.
Decoder module includes:
Speed calculates: using M T method, while recording code-disc output pulse and high-frequency clock pulse, between M method and T method Switching is to obtain accurate results；
Position calculates: calculating current location by counting motor feedback quadrature coding pulse.
The present invention has carried out the realization of Verilog to parameter of electric machine computing module, and the input of parameter of electric machine computing module is Motor feedback quadrature coding pulse exports the position to be calculated and velocity information.Tachometric survey using above-mentioned M T method, This method combines the advantage of traditional M method and T method, so that motor can accurately measure under high speed or low-speed situations Motor present speed.Position measurement is then realized by counting pulse, and the rising edge and decline by judgement feedback waveform are needed Along realizing.
The present invention carries out the acquisition of three-phase current data using external ADC, is believed the number after conversion by UART interface It number is transmitted in FPGA, the reduction of electric current is carried out in FPGA.
The parameter of electric machine being calculated is fed back in host computer using UART interface and is shown by the present invention, intends exploitation one The graphical interfaces for covering the end PC, is shown, while calculating the control precision of motor for motor feedback data, dynamic response speed The parameters such as degree are to assess the superiority and inferiority of servo-system.
The present invention envisions a set of more motor Collaborative Control schemes based on FPGA, makes full use of the spy of FPGA high degree of parallelism Point.For traditional DSP implementation, the participation that multiple electric motors need muti-piece DSP is controlled, and FPGA is made with its high concurrency It is performed simultaneously more set algorithms to be possibly realized, it is only necessary to which the control of multiple electric motors can be completed in one piece of FPGA, does not need lead between plate Letter, can more easily carry out the Collaborative Control of more motors.Its implementation is also relatively easy, it is only necessary to answer motor control module More parts are made, and adds corresponding control module, the Collaborative Control of more motors can be realized.The technology is in AGV trolley, robot control System etc. needs the field of more motor Collaborative Controls that can be applied well.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase Mutually combination.

Claims (10)

1. a kind of servo control system realized based on Verilog characterized by comprising
FPGA: whole control algolithms are realized by Verilog language；
Driving plate: the connection servo motor and FPGA, to drive servo motor according to the control signal of FPGA and to institute State FPGA transmitting motor feedback signals.
Analog-digital converter: the three-phase current analogue value in motor feedback signals is converted into digital value, is transmitted in the FPGA Carry out operation.
2. the servo control system realized according to claim 1 based on Verilog, which is characterized in that the motor feedback Signal includes: three-phase current signal and quadrature coding pulse signal.
3. the servo control system realized according to claim 2 based on Verilog, which is characterized in that the FPGA includes:
Decoder module: according to the quadrature coding pulse signal carry out parameter of electric machine calculating, obtain servo motor position and Velocity information；
FOC module: according to the servo motor position and velocity information, calculate duty ratio corresponding PWM waveform, be transmitted to The driving plate；
Interface module: communicating to connect with the end PC, the servo motor position and velocity information is transmitted to the end PC, the assessment of the end PC is watched The superiority and inferiority of dress system.
4. the servo control system realized according to claim 3 based on Verilog, which is characterized in that the decoder module Include:
Speed calculates: using M T method, while recording code-disc output pulse and high-frequency clock pulse, switches between M method and T method To obtain accurate results；
Position calculates: calculating current location by counting the quadrature coding pulse signal.
5. the servo control system realized according to claim 3 based on Verilog, which is characterized in that the FOC module packet It includes:
Clarke conversion module, Park conversion module and iPark transformation: being coordinate transform, and wherein trigonometric function, which calculates, uses Cordic algorithm is realized；
PI controller: it adjusts algorithm and is realized so that motor is faster stable using difference form.
SVPWM module: calculating PWM waveform duty ratio, exports PWM waveform.
6. the servo control system realized according to claim 3 based on Verilog, which is characterized in that the interface module Use serial line interface.
7. the servo control system realized according to claim 2 based on Verilog, which is characterized in that the driving plate is defeated The three-phase current signal out is analog signal, is converted to after digital signal described in input by external analog-digital converter FPGA。
8. the servo control system realized according to claim 1 based on Verilog, which is characterized in that the servo motor Quantity be one or more.
9. the servo control system realized according to claim 1 based on Verilog, which is characterized in that the driving plate master Chip type selecting IR2136 is controlled, built-in power driving and current collection circuit in driving plate.
10. the servo control system realized according to claim 3 based on Verilog, which is characterized in that in the FPGA Each module has carried out quantification treatment.
CN201910712721.8A 2019-08-02 2019-08-02 The servo control system realized based on Verilog Pending CN110471336A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116796114A (en) * 2023-06-25 2023-09-22 广州呗呗科技有限公司 FOC algorithm optimization method

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US20030196194A1 (en) * 2001-10-11 2003-10-16 Johns Clifford R. Hardware design protocol and system
CN102354134A (en) * 2011-09-02 2012-02-15 北京邮电大学 FPGA-based modularization double-joint servo control system
CN102840874A (en) * 2011-06-22 2012-12-26 合康变频科技（武汉）有限公司 Frequency division method and system for any integer of orthogonal photoelectric encoder
CN104135212B (en) * 2014-07-21 2017-04-19 华南理工大学 Flexibility motion control IP (Intellectual Property) core and implementation method thereof
CN109302114A (en) * 2018-08-31 2019-02-01 浙江工业大学 The permanent magnet synchronous motor full speed range method for controlling position-less sensor realized based on FPGA
CN109600075A (en) * 2018-07-13 2019-04-09 西南交通大学 A kind of multiple-axis servo drive control device based on multiprocessor systems on chips

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030196194A1 (en) * 2001-10-11 2003-10-16 Johns Clifford R. Hardware design protocol and system
CN102840874A (en) * 2011-06-22 2012-12-26 合康变频科技（武汉）有限公司 Frequency division method and system for any integer of orthogonal photoelectric encoder
CN102354134A (en) * 2011-09-02 2012-02-15 北京邮电大学 FPGA-based modularization double-joint servo control system
CN104135212B (en) * 2014-07-21 2017-04-19 华南理工大学 Flexibility motion control IP (Intellectual Property) core and implementation method thereof
CN109600075A (en) * 2018-07-13 2019-04-09 西南交通大学 A kind of multiple-axis servo drive control device based on multiprocessor systems on chips
CN109302114A (en) * 2018-08-31 2019-02-01 浙江工业大学 The permanent magnet synchronous motor full speed range method for controlling position-less sensor realized based on FPGA

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116796114A (en) * 2023-06-25 2023-09-22 广州呗呗科技有限公司 FOC algorithm optimization method
CN116796114B (en) * 2023-06-25 2024-03-29 广州呗呗科技有限公司 FOC algorithm optimization method

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Application publication date: 20191119