CN201608679U - FPGA (field programmable gate array) chip-based drive control device for REPMSM (rare-earth permanent-magnet synchronous motor) - Google Patents
FPGA (field programmable gate array) chip-based drive control device for REPMSM (rare-earth permanent-magnet synchronous motor) Download PDFInfo
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- CN201608679U CN201608679U CN2010200196461U CN201020019646U CN201608679U CN 201608679 U CN201608679 U CN 201608679U CN 2010200196461 U CN2010200196461 U CN 2010200196461U CN 201020019646 U CN201020019646 U CN 201020019646U CN 201608679 U CN201608679 U CN 201608679U
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Abstract
The utility model discloses a FPGA (field programmable gate array) chip-based drive control device for an REPMSM (rare-earth permanent-magnet synchronous motor), which is mainly characterized in that the FPGA chip is used as a system core control unit; a data acquisition method is disclosed for multi-channel analog quantity and capable of realizing the real-time parallel acquisition of multi-channel analog quantity and high real-time performance and good expandability; and various torque control models are provided for the REPMSM, thereby providing a great convenience for control of electric vehicle and industrial automation. The drive control device is characterized by simple structure, high reliability, precise speed regulation, fast responding, good loading property, high expandability and the like, and can be widely applied in industrial automation and industries concerning with electric vehicles, steamships, trains, national defense, etc.
Description
Technical field:
It is the rare earth permanent magnet synchronous motor driving control device of core based on fpga chip that the utility model relates to a kind of.
Background technology:
Rare earth permanent-magnet synchronization motor is a kind of generally acknowledged energy-saving efficient motor, compares with common electric machine, has efficient energy-saving, and is simple in structure, and power density height, rotating speed be not with the characteristics such as characteristic of the fluctuation of load.China's rare earth element reserves are abundant, for good basis has been established in the extensive use of rare earth permanent-magnet synchronization motor.
The control of rare earth permanent-magnet synchronization motor is more than the common electric machine complexity, and general frequency converter almost can't reliably drive.In the drive system of rare earth permanent-magnet synchronization motor, need to realize that a large amount of real-time parallel datas is handled and control, if adopt single-chip microcomputer or DSP to realize that system response time is difficult to satisfy the control requirement of rare earth permanent-magnet synchronization motor.These problems have influenced the rare earth permanent-magnet synchronization motor practical application to a great extent.
Summary of the invention
The purpose of this utility model provides a kind of simple in structure, the reliability height, and speed governing is steadily accurate, faster system response, load characteristic is good, and what the function expandability was strong is the rare earth permanent magnet synchronous motor driving control device of core based on FPGA.
In order to overcome the deficiencies in the prior art, the technical solution of the utility model is to solve like this: a kind of is the rare earth permanent magnet synchronous motor driving control device of core based on fpga chip, the hardware that special character of the present utility model is this device by fpga chip successively respectively with power supply circuits, PWM drives output circuit, id/td measures, communication interface, input and output control and display part, position transducer, the multi-analog collection connects, the multi-analog collection is isolated conversion with power supply, and measurement is connected with three-phase current, PWM drives output circuit, position transducer is connected with rare earth permanent-magnet synchronization motor, and the system integration has multiple torque controlling models.
Described multi-analog collecting part, be connected with self adaptation sawtooth waveforms generative circuit by analogue collection module in the chip, this self adaptation sawtooth waveforms generative circuit is connected with the amplitude pulse-width conversion circuit, and the amplitude pulse-width conversion circuit is connected with analogue collection module in the chip.
Described current changing rate acquisition process part is made of induction type current rate of change transducer, guard signal generative circuit; induction type current rate of change transducer is connected with the guard signal generative circuit, and the guard signal generative circuit is connected with current changing rate processing module in the fpga chip.
Described multiple torque controlling models comprises:
(1) when controlled motor output torque during less than the default torque, control command is to the increase of motor speed or reduce control effectively;
(2) when controlled motor output torque reaches the default torque, control command is invalid to the increase control of motor speed; Reduce control effectively;
(3) when controlled motor output torque had surpassed the default torque, motor speed can reduce automatically.
Prior art is compared, because the utility model has used with fpga chip to the control core unit and the multi-analog collecting method of running simultaneously, lays a good foundation for system's parallel control, makes system have very high response speed; The facility that multiple torque controlling models provides for the control of electric automobile and industrial automation.The utlity model has simple in structure, the reliability height, speed governing is steadily accurate, faster system response, load characteristic is good, function characteristics such as extendibility is strong again.Can be widely used in industrial automation, electric automobile, steamer, train, a plurality of industries such as national defence.
Description of drawings:
Fig. 1 is the utility model electrical system architecture schematic diagram;
Fig. 2 is a multi-analog collecting part schematic diagram;
Fig. 3 is a current changing rate acquisition process part-structure schematic diagram.
Embodiment
Accompanying drawing is embodiment of the present utility model.
Below in conjunction with accompanying drawing summary of the invention is described further:
With reference to shown in Figure 1, a kind of is the rare earth permanent magnet synchronous motor driving control device of core based on fpga chip, the hardware of this device is connected with power supply circuits 3, PWM driving output circuit 6, id/td measurement 4, multi-analog collection 10, communication interface 9, input and output control and display part 2, position transducer 8 respectively successively by fpga chip 1, multi-analog collection 10 is isolated conversion 5 with power supply and is connected with three-phase current measurement 5, and PWM driving output circuit 6, position transducer 8 are connected with rare earth permanent-magnet synchronization motor.
Shown in Figure 2, the multi-analog collecting part is connected with self adaptation sawtooth waveforms generative circuit 71 by analogue collection module in the chip 73, self adaptation sawtooth waveforms generative circuit 71 is connected with amplitude pulse-width conversion circuit 72, and amplitude pulse-width conversion circuit 72 is gathered analog data with the interior analogue collection module 73 of chip with quilt and is connected.
In order to realize the requirement of rare earth permanent magnet synchronous motor driving control device to multi-parameter parallel acquisitions such as electric current, voltages, improve the sampled data antijamming capability, the collection running is: analogue collection module 73 sends system synchronization pulse and sawtooth waveforms amplitude data to self adaptation sawtooth waveforms generative circuit 71 in the fpga chip, self adaptation sawtooth waveforms generative circuit 71 is sent the sawtooth waveforms performance data of its generation back in sheet analogue collection module 73 formation closed loops, generates stable synchronous sawtooth waveforms.The three-phase current measuring circuit is finished current signal and is measured, power supply is isolated conversion circuit and is finished the supply power voltage measurement, analog signals such as above-mentioned electric current, voltage and synchronously sawtooth waveforms in amplitude pulse-width conversion circuit 72, generates each corresponding square wave data parallel and sends, the interior analogue collection module 73 of chip converts the square wave data parallel to analog data.Realized multi-channel analog data synchronization parallel acquisition.
Shown in Figure 3; current changing rate acquisition process part is made of induction type current rate of change transducer 41, guard signal generative circuit 42; induction type current rate of change transducer 41 is connected with guard signal generative circuit 42, and guard signal generative circuit 42 is connected with supply current rate of change processing module 43 in the fpga chip.
In order to realize, the in real time requirement of monitoring accurate of rare earth permanent-magnet synchronization motor drive controlling to system's supply current state; the function implementation is: gather the main circuit current change information by induction type current rate of change transducer 41; deliver to guard signal generative circuit 42; when the main circuit current rate of change surpasses set point; produce protection information and deliver to supply current rate of change processing module 43 in the fpga chip, finish control.
Described multiple torque controlling models comprises:
(1) when controlled motor output torque during less than the default torque, control command is to the increase of motor speed or reduce control effectively;
(2) when controlled motor output torque reaches the default torque, control command is invalid to the increase control of motor speed; Reduce control effectively;
(3) when controlled motor output torque had surpassed the default torque, motor speed can reduce automatically.
In sum, rare earth permanent-magnet synchronization motor drive unit embodiment function implementation of the present utility model is: kernel control chip FPGA and the multi-channel analog data of running simultaneously and gathering, location status constitutes closed-loop control system, FPGA receives input and sets or communication instruction, produce drive signal and drive output circuit to PWM, PWM drives output circuit and drives permagnetic synchronous motor, finishes the various control operations of rare earth permanent-magnet synchronization motor.In system's running, states such as the real-time monitor current of FPGA, voltage and current changing rate are realized various defencive functions; FPGA communicates by letter with input/output interface simultaneously, transmits relevant information.
Said system control also includes control preface software interior except that described hardware interconnects and finish separately function.
Claims (4)
1. one kind is the rare earth permanent magnet synchronous motor driving control device of core based on fpga chip, the hardware that it is characterized in that this device by fpga chip (1) successively respectively with power supply circuits (3), PWM drives output circuit (6), id/td measures (4), multi-analog is gathered (10), communication interface (9), input and output control and demonstration (2), position transducer (8) connects, multi-analog is gathered (10) and is isolated conversion (5) with power supply, three-phase current is measured (7) and is connected, PWM drives output (6) and is connected with position transducer (8), the other end of position transducer (8) is connected with rare earth permanent-magnet synchronization motor, and has installed multiple torque controlling models integrated.
2. according to claim 1 is the rare earth permanent magnet synchronous motor driving control device of core based on fpga chip, it is characterized in that described multi-analog collection is to be made of self adaptation sawtooth waveforms generative circuit (71) and amplitude pulse-width conversion circuit (72), analogue collection module (73) is connected with self adaptation sawtooth waveforms generative circuit (71) in the chip, self adaptation sawtooth waveforms generative circuit (71) is connected with amplitude pulse-width conversion circuit (72), amplitude pulse-width conversion circuit (72) is gathered analog data with the interior analogue collection module (73) of chip with quilt and is connected, and constitutes the multi-analog collecting part.
3. according to claim 1 is the rare earth permanent magnet synchronous motor driving control device of core based on fpga chip; it is characterized in that described id/td measures (4) and is made of induction type current rate of change transducer (41), guard signal generative circuit (42); induction type current rate of change transducer (41) is connected with guard signal generative circuit (42); guard signal generative circuit (42) is connected with supply current rate of change processing module (43) in the fpga chip, constitutes current changing rate acquisition process part.
4. according to claim 1 is the rare earth permanent magnet synchronous motor driving control device of core based on fpga chip, it is characterized in that described multiple torque controlling models comprises:
(1) when controlled motor output torque during less than the default torque, control command is to the increase of motor speed or reduce control effectively;
(2) when controlled motor output torque reaches the default torque, control command is invalid to the increase control of motor speed; Reduce control effectively;
(3) when controlled motor output torque had surpassed the default torque, motor speed can reduce automatically.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN2010200196461U CN201608679U (en) | 2010-01-07 | 2010-01-07 | FPGA (field programmable gate array) chip-based drive control device for REPMSM (rare-earth permanent-magnet synchronous motor) |
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CN2010200196461U CN201608679U (en) | 2010-01-07 | 2010-01-07 | FPGA (field programmable gate array) chip-based drive control device for REPMSM (rare-earth permanent-magnet synchronous motor) |
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CN2010200196461U Expired - Fee Related CN201608679U (en) | 2010-01-07 | 2010-01-07 | FPGA (field programmable gate array) chip-based drive control device for REPMSM (rare-earth permanent-magnet synchronous motor) |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103701382A (en) * | 2013-12-17 | 2014-04-02 | 华中科技大学 | FPGA (field programmable gate array)-based permanent magnet synchronous motor current loop bandwidth expansion device |
CN104228851A (en) * | 2014-09-09 | 2014-12-24 | 上虞安卡拖车配件有限公司 | Speed tracking and control system of urban railway train |
CN110344706A (en) * | 2018-04-04 | 2019-10-18 | 中山市欧派克五金制品有限公司 | A kind of self-adaptation control method and adaptive control system for sliding door |
-
2010
- 2010-01-07 CN CN2010200196461U patent/CN201608679U/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103701382A (en) * | 2013-12-17 | 2014-04-02 | 华中科技大学 | FPGA (field programmable gate array)-based permanent magnet synchronous motor current loop bandwidth expansion device |
CN103701382B (en) * | 2013-12-17 | 2016-01-20 | 华中科技大学 | A kind of permagnetic synchronous motor electric current loop bandwidth expansion means based on FPGA |
CN104228851A (en) * | 2014-09-09 | 2014-12-24 | 上虞安卡拖车配件有限公司 | Speed tracking and control system of urban railway train |
CN110344706A (en) * | 2018-04-04 | 2019-10-18 | 中山市欧派克五金制品有限公司 | A kind of self-adaptation control method and adaptive control system for sliding door |
CN110344706B (en) * | 2018-04-04 | 2021-11-09 | 中山市欧派克五金制品有限公司 | Self-adaptive control method and self-adaptive control system for sliding door |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101013 Termination date: 20170107 |