CN110416295A - A kind of groove-shaped insulated gate bipolar transistor and preparation method thereof - Google Patents
A kind of groove-shaped insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
A kind of groove-shaped insulated gate bipolar transistor and preparation method thereof, belongs to power semiconductor technologies field.The present invention is by utilizing the feature that the narrow bandgap materials such as silicon channel mobility is high and it is small with the ohmic contact resistance of emitter metal formation, to form conducting channel and Ohmic contact is formed with emitter metal with low-gap semiconductor material, channel resistance and Ohmic resistance are reduced, to reduce the forward conduction voltage drop of device；Furthermore, utilize the high feature of the broad stopbands such as silicon carbide material critical disruptive field intensity, so that device breakdown is not limited that avalanche breakdown occurs by gate oxide, change the position of breakdown point, the breakdown voltage of device is improved to a certain extent, to can suitably reduce drift region thickness under certain voltage grade, forward conduction voltage drop and turn-off power loss are further reduced, to optimize the tradeoff between conduction voltage drop and turn-off power loss.In addition, the present invention also provides a kind of preparation methods of groove-shaped insulated gate bipolar transistor.
Description
Technical field
The invention belongs to power semiconductor technologies fields, and in particular to a kind of groove-shaped insulated gate bipolar transistor and its system
Preparation Method.
Background technique
Fig. 1 shows a kind of half structure cell of conventional groove type total silicon base IGBT device, although IGBT has conductance tune
Effect processed, so that forward conduction voltage drop is reduced to a certain extent, but in order to realize higher pressure resistance, to have to increase
The thickness of drift region, but this measure improves conduction voltage drop again, it is therefore desirable to back injection efficiency is increased to reduce conduction voltage drop, is infused
The increase for entering efficiency causes the number that nonequilibrium carrier extracts in turn off process and increases, so that the turn-off time is increased,
Turn-off power loss is improved, so that the tradeoff between conduction voltage drop and turn-off power loss deteriorates.Therefore, a kind of new IGBT is needed
Structure cell improves the tradeoff between conduction voltage drop and turn-off power loss.
Summary of the invention
The technical problem to be solved by the present invention is in view of the problems of the existing technology, provide a kind of groove-shaped insulated gate
Bipolar transistor and preparation method thereof.
In order to solve the above technical problems, the present invention provides a kind of groove-shaped insulated gate bipolar transistor, comprising: metallization collection
Electrode, the second conductive type semiconductor collecting zone, the first conductive type semiconductor drift region, the resistance of the first conductive type semiconductor field
Only layer, the second conductive type semiconductor base area, second the second base area of conductive type semiconductor, the transmitting of the first conductive type semiconductor
Area, the second conductive type semiconductor emitter region, trench gate structure and emitter metal；
Metallization collector is located at the lower section of the second conductive type semiconductor collecting zone, the resistance of the first conductive type semiconductor field
Only layer and the first conductive type semiconductor drift region are sequentially located on the second conductive type semiconductor collecting zone；
Second the second base area of conductive type semiconductor is located at the side above the first conductive type semiconductor drift region；Second
Conductive type semiconductor base area is located on the first conductive type semiconductor drift region and second the second base area of conductive type semiconductor；
Second conductive type semiconductor emitter region and the first conductive type semiconductor emitter region are located side by side at the second conductive-type
On type semiconductor base area, and side contacts with each other；Emitter metal is located at the second conductive type semiconductor emitter region and first and leads
In electric type semiconductor emitter region；
Trench gate structure is located on the first conductive type semiconductor drift region, and it is close to the side and the of emitter metal
One conductive type semiconductor emitter region, the second conductive type semiconductor base area and the first conductive type semiconductor drift region side
Contact；
First conductive type semiconductor emitter region, the second conductive type semiconductor emitter region and the second conductive type semiconductor
The forbidden bandwidth of semiconductor material used in base area is less than second the second base area of conductive type semiconductor, the first conductive type semiconductor
The taboo of semiconductor material used in drift region, the first conductive type semiconductor field stop layer and the second conductive type semiconductor collecting zone
Bandwidth.
The beneficial effects of the present invention are: the present invention passes through using narrow bandgap material channel mobility is high and itself and emitter
The small feature of ohmic contact resistance that metal is formed forms conducting channel and and emitter metal with low-gap semiconductor material
Ohmic contact is formed, channel resistance and Ohmic resistance are reduced, to reduce the forward conduction voltage drop of device；In addition, utilizing
The high feature of the broad stopbands such as silicon carbide material critical disruptive field intensity, so that device breakdown is not limited to occur by gate dielectric layer
Avalanche breakdown, the position of device breakdown point in forward blocking have been transferred to the second conduction type by original gate dielectric layer and have partly led
In the reverse biased pn junction of the second base area of body and the first conductive type semiconductor drift region, the breakdown of device is improved to a certain extent
Voltage, to can suitably reduce drift region thickness under certain voltage grade, further reduce forward conduction voltage drop and close
Breakdown consumption, so as to improve the tradeoff of conduction voltage drop and turn-off power loss.
It further, further include the first conduction type carrier accumulation layer, the first conduction type carrier accumulation layer is located at
Between second the second base area of conductive type semiconductor and the first conductive type semiconductor drift region, and the first conduction type carrier
The side of accumulation layer is contacted with the side of trench gate structure, and the doping concentration of the first conduction type carrier accumulation layer is greater than first
The doping concentration of conductive type semiconductor drift region.
Beneficial effect using above-mentioned further scheme is: the doping concentration of the first conduction type carrier accumulation layer is greater than
The doping concentration of first conductive type semiconductor drift region greatly reduces leading for device to enhance conductivity modulation effect
Logical pressure drop, further improves the tradeoff between forward conduction voltage drop and turn-off power loss.
It further, further include second conductive type semiconductor layer, it is conductive that second conductive type semiconductor layer is located at second
Between type semiconductor emitter region and emitter metal, the forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer
Less than the forbidden bandwidth of semiconductor material used in the second conductive type semiconductor emitter region.
Beneficial effect using above-mentioned further scheme is: the taboo of semiconductor material used in second conductive type semiconductor layer
Bandwidth less than semiconductor material used in the second conductive type semiconductor emitter region forbidden bandwidth, thus in the contact surface of the two
Hetero-junctions is formed, which enhances conductivity modulation effect when device forward conduction as hole barrier, reduce conducting
Pressure drop, to further improve the tradeoff between forward conduction voltage drop and turn-off power loss.
It further, further include second conductive type semiconductor layer, the second conductive type semiconductor layer is located at second
Inside conductive type semiconductor emitter region, thickness is less than or equal to the thickness of the second conductive type semiconductor emitter region, and second leads
The forbidden bandwidth of semiconductor material used in electric type semiconductor layer is conductive less than the second conductive type semiconductor emitter region and second
The forbidden bandwidth of semiconductor material used in type semiconductor base area.
Beneficial effect using above-mentioned further scheme is: the taboo of semiconductor material used in second conductive type semiconductor layer
Bandwidth less than semiconductor material used in the second conductive type semiconductor base area forbidden bandwidth, to make the second conduction type half
The contact surface of conductor layer and the second conductive type semiconductor base area forms hetero-junctions, enhances the ability of anti-latch.
It further, further include the second conduction type shielded layer, the second conduction type shielded layer is located at the first conduction type
Between drift semiconductor area and trench gate structure, and the side of the second conduction type shielded layer and trench gate structure are far from emitter
One side contacts of metal.
Beneficial effect using above-mentioned further scheme is: the second conduction type shielded layer shield grid and collector it
Between capacitive coupling, reduce the capacitor of device, improve the switching speed of device, reduce switching loss, so as to improve
Tradeoff between forward conduction voltage drop and turn-off power loss, and enhance anti-short circuit capability.
Further, the part gate electrode of the trench gate structure is shorted the emitter metal.
Beneficial effect using above-mentioned further scheme is: a part of grid sending and receiving emitter-base bandgap grading in trench gate structure, is formed
Division grid structure further improves the switching speed of device, reduces switching loss to reduce reverse transfer capacitance,
Improve the tradeoff between forward conduction voltage drop and turn-off power loss.
It further, further include first the second emitter region of conductive type semiconductor and the second conductive type semiconductor third base
Area, first the second emitter region of conductive type semiconductor and the second conductive type semiconductor third base area are located at trench gate structure and
Between one conductive type semiconductor drift region, first the second emitter region of conductive type semiconductor is located at the second conductive type semiconductor
In third base area, and the side of trench gate structure is partly led with first the second emitter region of conductive type semiconductor and the second conduction type
One side contacts of body third base area；Emitter metal is also located at first the second emitter region of conductive type semiconductor, the second conductive-type
On type semiconductor third base area and trench gate structure.
Beneficial effect using above-mentioned further scheme is: improving gully density and the emitter side of entire device
Carrier concentration reduces conduction voltage drop, in addition, it shields the capacitive coupling between grid collector, reduces device
Capacitor improves the switching speed of device, reduces switching loss, so as to improve between forward conduction voltage drop and turn-off power loss
Tradeoff.
It further, further include the 4th base area of the second conductive type semiconductor, the 4th base area of the second conductive type semiconductor
Positioned at the side of the second conductive type semiconductor third base area first part and the top of the first conductive type semiconductor drift region,
And it is located at the lower section of first the second emitter region of conductive type semiconductor and the second conductive type semiconductor third base area second part,
The forbidden bandwidth of semiconductor material used in the 4th base area of second conductive type semiconductor is greater than or equal to the first conduction type and partly leads
The forbidden bandwidth of semiconductor material used in the second emitter region of body and the second conductive type semiconductor third base area.
Beneficial effect using above-mentioned further scheme is: when forward blocking, by the 4th base of the second conductive type semiconductor
The reverse biased pn junction that area and the first conductive type semiconductor drift region are constituted carries out pressure resistance, due to the first conductive type semiconductor second
The 4th base area of the second conductive type semiconductor below emitter region and the second conductive type semiconductor third base area second part by
Wide-band gap material is constituted, so improving the pressure resistance of entire device.
It further, further include the 4th base area of the second conductive type semiconductor, the 4th base area of the second conductive type semiconductor
On the first conductive type semiconductor drift region, and it is located at first the second emitter region of conductive type semiconductor and the second conductive-type
The forbidden bandwidth of the lower section of type semiconductor third base area, semiconductor material used in the 4th base area of the second conductive type semiconductor is greater than
Or it is equal to semiconductor material used in first the second emitter region of conductive type semiconductor and the second conductive type semiconductor third base area
Forbidden bandwidth.
Beneficial effect using above-mentioned further scheme is: when forward blocking, by the 4th base of the second conductive type semiconductor
The reverse biased pn junction that area and the first conductive type semiconductor drift region are constituted carries out pressure resistance, due to the first conductive type semiconductor second
Prohibited by width the 4th base area of the second conductive type semiconductor below emitter region and entire second conductive type semiconductor third base area
Carrying material is constituted, so further improving the pressure resistance of entire device.
It further, further include second the second semiconductor layer of conduction type, second the second semiconductor layer of conduction type is located at
Between emitter metal and the second part of the second conductive type semiconductor third base area, second the second semiconductor layer of conduction type
The forbidden bandwidth of semiconductor material used is wide less than the forbidden band of semiconductor material used in the second conductive type semiconductor third base area
Degree.
Beneficial effect using above-mentioned further scheme is: semiconductor material used in second the second semiconductor layer of conduction type
Forbidden bandwidth less than semiconductor material used in the second conductive type semiconductor third base area forbidden bandwidth, thus in the two
Contact surface forms hetero-junctions, which enhances conductivity modulation effect when device forward conduction as hole barrier, reduces
Conduction voltage drop, to further improve the tradeoff between forward conduction voltage drop and turn-off power loss.
In order to solve the above technical problems, the present invention provides a kind of manufacturing method of groove-shaped insulated gate bipolar transistor, packet
Include following steps:
Second conductive type semiconductor collecting zone of the second conductive type semiconductor substrate as device is chosen, in semiconductor
The first conductive type semiconductor field stop layer and the first conductive type semiconductor drift region are sequentially formed on substrate；
Side above the first conductive type semiconductor drift region forms second the second base area of conductive type semiconductor, In
The second conductive type semiconductor is formed on first conductive type semiconductor drift region and second the second base area of conductive type semiconductor
Base area,
The first conductive type semiconductor emitter region and the second conduction type are formed on the second conductive type semiconductor base area
Semiconductor emission area, the side of the first conductive type semiconductor emitter region and the second conductive type semiconductor emitter region side are mutual
Contact；First conductive type semiconductor emitter region, the second conductive type semiconductor emitter region and the second conductive type semiconductor base
The forbidden bandwidth of semiconductor material used in area is floated less than second the second base area of conductive type semiconductor, the first conductive type semiconductor
The forbidden band of semiconductor material used in shifting area, the first conductive type semiconductor field stop layer and the second conductive type semiconductor collecting zone
Width；
On the first conductive type semiconductor drift region and the first conductive type semiconductor emitter region, the second conduction type
The side of semiconductor base area and the first conductive type semiconductor drift region forms trench gate structure；
Emitter metal is formed in the second conductive type semiconductor emitter region and the first conductive type semiconductor emitter region；
Metallization collector is formed in the lower section of semiconductor chip.
The beneficial effects of the present invention are: the present invention passes through using narrow bandgap material channel mobility is high and itself and emitter
The small feature of ohmic contact resistance that metal is formed forms conducting channel and and emitter metal with low-gap semiconductor material
Ohmic contact is formed, channel resistance and Ohmic resistance are reduced, to reduce the forward conduction voltage drop of device；In addition, utilizing
The high feature of the broad stopbands such as silicon carbide material critical disruptive field intensity, so that device breakdown is not limited to occur by gate dielectric layer
Avalanche breakdown, the position of device breakdown point in forward blocking have been transferred to the second conduction type by original gate dielectric layer and have partly led
In the reverse biased pn junction of the second base area of body and the first conductive type semiconductor drift region, the breakdown of device is improved to a certain extent
Voltage, to can suitably reduce drift region thickness under certain voltage grade, further reduce forward conduction voltage drop and close
Breakdown consumption, so as to improve the tradeoff of conduction voltage drop and turn-off power loss.
Further, before forming emitter metal, second is formed in the second conductive type semiconductor emitter region and is led
Electric type semiconductor layer forms emitter gold in the first conductive type semiconductor emitter region and second conductive type semiconductor layer
Belong to, the forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer is less than the second conductive type semiconductor emitter region institute
With the forbidden bandwidth of semiconductor material.
Beneficial effect using above-mentioned further scheme is: the taboo of semiconductor material used in second conductive type semiconductor layer
Bandwidth less than semiconductor material used in the second conductive type semiconductor emitter region forbidden bandwidth, thus in the contact surface of the two
Hetero-junctions is formed, which enhances conductivity modulation effect when device forward conduction as hole barrier, reduce conducting
Pressure drop, to further improve the tradeoff between forward conduction voltage drop and turn-off power loss.
Detailed description of the invention
Fig. 1 is half cellular structural schematic diagram of conventional groove type insulated gate bipolar transistor；
Fig. 2 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of first embodiment of the invention；
Fig. 3 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of second embodiment of the invention；
Fig. 4 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of third embodiment of the invention；
Fig. 5 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of fourth embodiment of the invention；
Fig. 6 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of fifth embodiment of the invention；
Fig. 7 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of sixth embodiment of the invention；
Fig. 8 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of seventh embodiment of the invention；
Fig. 9 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of eighth embodiment of the invention；
Figure 10 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of ninth embodiment of the invention；
Figure 11 is half cellular structural schematic diagram of the groove-shaped insulated gate bipolar transistor of tenth embodiment of the invention；
Figure 12 is the energy band diagram after present invention formation Si/SiC hetero-junctions；
Figure 13 is the energy band diagram after present invention formation GeSi/Si hetero-junctions.
In attached drawing, parts list represented by the reference numerals are as follows:
1, groove-shaped gate electrode, 2, gate dielectric layer, the 3, first conductive type semiconductor emitter region, 4, emitter metal, 5,
Second conductive type semiconductor emitter region, 6-1, the second conductive type semiconductor base area, 6-2, the second conductive type semiconductor
Two base areas, the 7, first conductive type semiconductor drift region, the 8, first conductive type semiconductor field stop layer, the 9, second conduction type
Semiconductor collecting zone, 10, metallization collector, the 11, first conduction type carrier accumulation layer, the 12, second conduction type are partly led
Body layer, the 13, second conduction type shielded layer, 14-1, the second conductive type semiconductor third base area, 14-2, the second conduction type
The 4th base area of semiconductor, 15, first the second emitter region of conductive type semiconductor, 16, second the second semiconductor layer of conduction type.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
In view of silicon-based devices are compared to semiconductor material with wide forbidden band such as silicon carbide, channel mobility is higher, channel electricity
Hinder smaller, interface state density is smaller, and the wide-band gap materials such as silicon carbide are since forbidden bandwidth is big, and critical breakdown electric field is high, In
Under same structure size, breakdown voltage is more much higher than silicon materials, so if under same breakdown voltage, silicon carbide
The drift region thickness of device can be smaller, to reduce conduction voltage drop, improves the folding between conduction voltage drop and turn-off power loss
Middle relationship.So in order to give full play to that silicon materials channel mobilities is high, channel resistance is small, interface state density is small and silicon carbide etc.
The high feature of wide-band gap material critical breakdown strength needs to propose that a kind of mixed type of above two material advantage feature of combination is new
Structure improves the tradeoff between conduction voltage drop and turn-off power loss with this.
As shown in Fig. 2, a kind of groove-shaped insulated gate bipolar transistor that first embodiment of the invention provides, comprising: metal
Change collector 10, the second conductive type semiconductor collecting zone 9, the first conductive type semiconductor drift region 7, the first conduction type half
Conductor field stop layer 8, the second conductive type semiconductor base area 6-1, second the second base area of conductive type semiconductor 6-2, first are led
Electric type semiconductor emitter region 3, the second conductive type semiconductor emitter region 5, trench gate structure and emitter metal 4；
Metallization collector 10 is located at the lower section of the second conductive type semiconductor collecting zone 9, the first conductive type semiconductor
Field stop layer 8 and the first conductive type semiconductor drift region 7 are sequentially located on the second conductive type semiconductor collecting zone 9；；
Second conductive type semiconductor the second base area 6-2 is located at the side of 7 top of the first conductive type semiconductor drift region；
Second conductive type semiconductor base area 6-1 is located at the first conductive type semiconductor drift region 7 and the second conductive type semiconductor
On two base area 6-2；
Second conductive type semiconductor emitter region 5 and the first conductive type semiconductor emitter region 3 are located side by side at the second conduction
On the 6-1 of type semiconductor base area, and side contacts with each other；Emitter metal 4 is located at 5 He of the second conductive type semiconductor emitter region
In first conductive type semiconductor emitter region 3；
Trench gate structure is located on the first conductive type semiconductor drift region 7, and its close to emitter metal 4 side with
First conductive type semiconductor emitter region 3, the second conductive type semiconductor base area 6-1 and the first conductive type semiconductor drift region
7 side contacts；
First conductive type semiconductor emitter region 3, the second conductive type semiconductor emitter region 5 and the second conduction type are partly led
The forbidden bandwidth of semiconductor material used in the 6-1 of body base area is less than second the second base area of conductive type semiconductor 6-2, the first conductive-type
Type drift semiconductor area 7, the first conductive type semiconductor field stop layer 8 and the second conductive type semiconductor collecting zone 9 used half
The forbidden bandwidth of conductor material.
In above-described embodiment, pass through the Europe using narrow bandgap material channel mobility height and itself and emitter metal formation
The small feature of nurse contact resistance is connect with low-gap semiconductor material to form conducting channel and form ohm with emitter metal
Touching, reduces channel resistance and Ohmic resistance, to reduce the forward conduction voltage drop of device；In addition, wide using silicon carbide
The high feature of forbidden band material critical disruptive field intensity, so that device breakdown is not limited that avalanche breakdown occurs by gate dielectric layer,
The position of device breakdown point in forward blocking has been transferred to second the second base of conductive type semiconductor by original gate dielectric layer
In the reverse biased pn junction of area and the first conductive type semiconductor drift region, the breakdown voltage of device is improved to a certain extent, from
And can suitably reduce drift region thickness under certain voltage grade, forward conduction voltage drop and turn-off power loss are further reduced,
So as to improve the tradeoff of conduction voltage drop and turn-off power loss.
In the present embodiment, the first conductive type semiconductor emitter region 3, the second conductive type semiconductor emitter region 5 and second
The forbidden bandwidth of semiconductor material used in the 6-1 of conductive type semiconductor base area is less than second the second base area of conductive type semiconductor 6-
2, the first conductive type semiconductor drift region 7, the first conductive type semiconductor field stop layer 8 and the second conductive type semiconductor collection
The forbidden bandwidth of semiconductor material used in electric area 9 makes the second conductive type semiconductor base area 6-1 and the second conductive type semiconductor
Second base area 6-2 forms hetero-junctions in its contact interface, makes the second conductive type semiconductor base area 6-1 and the first conduction type half
Conductor drift region 7 forms hetero-junctions in its contact interface, as shown in figure 12；Second the second base area of conductive type semiconductor 6-2's
Width is less than or equal to the width of the second conductive type semiconductor base area 6-1, the thickness of second the second base area of conductive type semiconductor 6-2
Degree is less than or equal to the thickness of the second conductive type semiconductor base area 6-1, the doping of second the second base area of conductive type semiconductor 6-2
Concentration and the doping concentration of the second conductive type semiconductor base area 6-1 may be the same or different, by adjusting doping concentration
To change the barrier height of nonequilibrium carrier.Trench gate structure includes groove-shaped gate electrode 1, and is arranged in groove-shaped gate electrode
The gate dielectric layer 2 of 1 bottom surface and side.
In addition, the first conductive type semiconductor emitter region 3, the second conductive type semiconductor emitter region 5 and second are led
Semiconductor used in electric type semiconductor base area 6-1 can be monocrystal material, be also possible to polycrystalline material.The trench gate structure packet
The gate dielectric layer 2 for including groove-shaped gate electrode 1 and being enclosed in groove-shaped 1 surface of gate electrode, the groove-shaped gate electrode 1 can be more
Crystal silicon gate electrode, the gate dielectric layer 2 can be gate oxide.The second base area of second conductive type semiconductor 6-2 can be with
Extend to the left and is directly directly contacted with gate dielectric layer 2.Semiconductor material used in device of the present invention is silicon carbide, silicon, GaAs, nitrogen
Change gallium, gallic oxide or diamond.
First conduction type is N-type, and the second conduction type is p-type or the second conduction type is p-type, and first leads
Electric type is N-type.First conductive type semiconductor emitter region 3 can be N+ silicon emitter region, the transmitting of the second conductive type semiconductor
Area 5 can be P+ silicon emitter region, and the second conductive type semiconductor base area 6-1 can be P-type silicon base area, and the second conduction type is partly led
The second base area of body 6-2 can be p-type silicon carbide base area, and the first conductive type semiconductor drift region 7 can drift about for N- silicon carbide
Area, the first conductive type semiconductor field stop layer 8 can be N-type silicon carbide field trapping layer, the second conductive type semiconductor current collection
Area 9 can be p-type silicon carbide collecting zone, and the first conduction type carrier accumulation layer 11 can store for N-type silicon carbide carrier
Layer, second conductive type semiconductor layer 12 can be p-type germanium silicon layer, and the second conduction type shielded layer 13 can be p-type silicon carbide
Shielded layer, the second conductive type semiconductor third base area 14-1 can be the second base area of P-type silicon, the second conductive type semiconductor the
Four base area 14-2 can be the second base area of p-type silicon carbide, and first the second emitter region of conductive type semiconductor 15 can be N+ silicon the
Two emitter region, second the second semiconductor layer of conduction type 16 can be the second germanium of p-type silicon layer.
In addition, the doping of the second conductive type semiconductor base area 6-1 and second the second base area of conductive type semiconductor 6-2 are dense
Degree is 5 × 1016cm-3~2 × 1017cm-3, with a thickness of 0.5~2 μm；The doping concentration of first conductive type semiconductor emitter region 3
It is 5 × 1018cm-3~1 × 1020cm-3, with a thickness of 0.2~0.5 μm；Gate oxide thickness is 50~100nm；Groove-shaped gate electrode
1 trench depth is 1~10 μm；The doping concentration of first conductive type semiconductor drift region is 7 × 1013cm-3~8 ×
1014cm-3, with a thickness of 60~150 μm；The doping concentration of first conductive type semiconductor field stop layer 8 is 5 × 1015cm-3~5 ×
1017cm-3, with a thickness of 1~5 μm；The doping concentration of second conductive type semiconductor collecting zone 9 is 1 × 1018cm-3~1 ×
1019cm-3, with a thickness of 1~5 μm；Cellular width is 1~10 μm.
It is in principle explanation that forbidden band is wide below by the principle that the present invention will be described in detail for the groove-shaped IGBT of N-channel
It spends a lesser side and is known as low-gap semiconductor (for opposite another party), be similarly known as the biggish side of forbidden bandwidth
(for opposite another party) wide bandgap semiconductor.Concrete principle is as follows:
Since the critical breakdown electric field of low-gap semiconductor is smaller, according to Gauss law, the trench type device that is constituted
Breakdown voltage be often limited to the electric field across oxide of gate oxide, device has occurred that oxide layer is hit before avalanche breakdown
It wears, to limit the breakdown voltage of device.Therefore, by introducing wide-band gap material, the high critical breakdown of wide-band gap material is utilized
The advantage of electric field, so that device breakdown is not limited that avalanche breakdown occurs by gate oxide, the breakdown point of device is by original
Gate oxide be transferred to second conductive type semiconductor the second base area 6-2 and the first conductive type semiconductor drift region 7/
In the reverse biased pn junction of one conduction type carrier accumulation layer 11, the breakdown voltage of device is improved to a certain extent, thus
Drift region thickness can suitably be reduced under certain voltage grade, reduce forward conduction voltage drop and turn-off time, wherein second leads
Electric type semiconductor the second base area 6-2 is the second base area of p-type, and the first conductive type semiconductor drift region 7 is N-type drift region, the
One conduction type carrier accumulation layer 11 is N-type carrier accumulation layer.Further, since the second conductive type semiconductor base area 6-1,
It is narrow bandgap material used in second conductive type semiconductor emitter region 5 and the first conductive type semiconductor emitter region 3, utilization is narrow
The feature that forbidden band material channel mobility is high and it is small with the ohmic contact resistance of emitter metal formation, is partly led with low energy gap
Body material come formed conducting channel and with emitter metal formed Ohmic contact, reduce channel resistance and Ohmic resistance, thus
Reduce the forward conduction voltage drop of device, wherein the second conductive type semiconductor base area 6-1 is p-type base area, the second conduction type
Semiconductor emission area 5 is p-type emitter region and the first conductive type semiconductor emitter region 3 is N-type emitter region.Therefore, in summary
Two principle analysis, so as to improve the tradeoff of conduction voltage drop and turn-off power loss.
As shown in figure 3, second embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, the present embodiment be
First conduction type carrier accumulation layer 11, the first conduction type carrier accumulation layer 11 are set on the basis of first embodiment
Between second conductive type semiconductor the second base area 6-2 and the first conductive type semiconductor drift region 7, and the first conduction type
The side of carrier accumulation layer 11 is contacted with the side of trench gate structure, and the doping of the first conduction type carrier accumulation layer 11 is dense
Degree is greater than the doping concentration of the first conductive type semiconductor drift region 7.
In above-described embodiment, the doping concentration of the first conduction type carrier accumulation layer 11 is greater than the first conduction type and partly leads
The doping concentration of body drift region 7 greatly reduces the conduction voltage drop of device, further changes to enhance conductivity modulation effect
The tradeoff being apt between forward conduction voltage drop and turn-off power loss.
As shown in figure 4, third embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, the present embodiment be
Second conductive type semiconductor layer 12 is set on the basis of second embodiment, and second conductive type semiconductor layer 12, which is located at second, leads
Between electric type semiconductor emitter region 5 and emitter metal 4, the taboo of semiconductor material used in second conductive type semiconductor layer 12
Forbidden bandwidth of the bandwidth less than semiconductor material used in the second conductive type semiconductor emitter region 5.
In above-described embodiment, the forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer 12 is led less than second
The forbidden bandwidth of semiconductor material used in electric type semiconductor emitter region 5, so that the contact surface in the two forms hetero-junctions, this is different
Matter knot is as hole barrier, as shown in figure 13, enhances conductivity modulation effect when device forward conduction, reduces conducting pressure
Drop, to further improve the tradeoff between forward conduction voltage drop and turn-off power loss.
As shown in figure 5, fourth embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, the present embodiment be
Second conductive type semiconductor layer 12 is set on the basis of second embodiment, and the second conductive type semiconductor layer 12 is located at the
Inside two conductive type semiconductor emitter region 5, thickness is less than or equal to the thickness of the second conductive type semiconductor emitter region 5, the
The forbidden bandwidth of semiconductor material used in two conductive type semiconductor layers 12 is less than the second conductive type semiconductor emitter region 5 and
The forbidden bandwidth of semiconductor material used in two conductive type semiconductor base area 6-1.
In above-described embodiment, the forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer 12 is led less than second
The forbidden bandwidth of semiconductor material used in electric type semiconductor base area 6-1, to make second conductive type semiconductor layer 12 and
The contact surface of two conductive type semiconductor base area 6-1 forms hetero-junctions, enhances the ability of anti-latch.
As shown in fig. 6, fifth embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, the present embodiment be
Second conduction type shielded layer 13 is set on the basis of fourth embodiment, and the second conduction type shielded layer 13 is located at the first conductive-type
Between type drift semiconductor area 7 and trench gate structure, and the side of the second conduction type shielded layer 13 and trench gate structure are separate
One side contacts of emitter metal 4.
In above-described embodiment, the second conduction type shielded layer 13 shields the capacitive coupling between grid and collector, subtracts
The small capacitor of device, improves the switching speed of device, reduces switching loss, so as to improve forward conduction voltage drop and closes
Tradeoff between breakdown consumption, and enhance anti-short circuit capability.
As shown in fig. 7, sixth embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, the present embodiment be
On the basis of 5th embodiment, the part gate electrode of the trench gate structure is made to be shorted emitter metal 4.
In above-described embodiment, a part of grid sending and receiving emitter-base bandgap grading in trench gate structure forms division grid structure, to reduce
Reverse transfer capacitance, further improves the switching speed of device, reduces switching loss, improve forward conduction voltage drop with
Tradeoff between turn-off power loss.At this point, trench gate structure is divided into two parts, a part is used as gate electrode, another part electricity
Pole and emitter metal 4, which are shorted, is used as emitter, to form division grid structure.
As shown in figure 8, seventh embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, the present embodiment be
First conductive type semiconductor the second emitter region 15 and the second conductive type semiconductor third are set on the basis of fourth embodiment
Base area 14-1, first conductive type semiconductor the second emitter region 15 and the second conductive type semiconductor third base area 14-1 are located at ditch
Between slot grid structure and the first conductive type semiconductor drift region 7, first the second emitter region of conductive type semiconductor 15 is located at the
In two conductive type semiconductor third base area 14-1, and the side of trench gate structure and the first conductive type semiconductor second emit
One side contacts in area 15 and the second conductive type semiconductor third base area 14-1；Emitter metal 4 is also located at the first conduction type
On semiconductor the second emitter region 15, the second conductive type semiconductor third base area 14-1 and trench gate structure.
This embodiment improves the carrier concentrations of the gully density of entire device and emitter side, reduce conducting pressure
Drop, in addition, it shields the capacitive coupling between grid collector, reduces the capacitor of device, improves the switch speed of device
Degree, reduces switching loss, so as to improve the tradeoff between forward conduction voltage drop and turn-off power loss.First conduction type
Semiconductor the second emitter region 15, the second conductive type semiconductor third base area 14-1, emitter metal 4 are formed with trench gate structure
Plane IGBT structure, the doping concentration and the second conductive type semiconductor base of the second conductive type semiconductor third base area 14-1
Area 6-1 is equal, so that plane IGBT structure is equal with groove-shaped IGBT structure threshold voltage.
As shown in figure 9, eighth embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, the present embodiment be
The 4th base area 14-2 of second conductive type semiconductor, the 4th base of the second conductive type semiconductor are set on the basis of the 7th embodiment
Area 14-2 is located at side and the drift of the first conductive type semiconductor of the second conductive type semiconductor third base area 14-1 first part
The top in area 7 is moved, and is located at first conductive type semiconductor the second emitter region 15 and the second conductive type semiconductor third base area
The forbidden bandwidth of the lower section of 14-1 second part, semiconductor material used in the 4th base area 14-2 of the second conductive type semiconductor is greater than
Or it is partly led equal to used in first conductive type semiconductor the second emitter region 15 and the second conductive type semiconductor third base area 14-1
The forbidden bandwidth of body material.
In above-described embodiment, when forward blocking, by the 4th base area of the second conductive type semiconductor and the first conduction type half
The reverse biased pn junction that conductor drift region is constituted carries out pressure resistance, due to first the second emitter region of conductive type semiconductor and the second conductive-type
The 4th base area of the second conductive type semiconductor below the second part of type semiconductor third base area is made of wide-band gap material, so
Improve the pressure resistance of entire device.
When the forbidden bandwidth of the 4th base area 14-2 of the second conductive type semiconductor is greater than the first conductive type semiconductor second
When emitter region 15 and the forbidden bandwidth of the second conductive type semiconductor third base area 14-1, the 4th base of the second conductive type semiconductor
Area 14-2 and first conductive type semiconductor the second emitter region 15 and the second conductive type semiconductor third base area 14-1 connect at it
Contacting surface forms hetero-junctions.The 4th base area 14-2 of second conductive type semiconductor and the second conductive type semiconductor third base area 14-1
Doping concentration may be the same or different, and change the barrier height of nonequilibrium carrier by adjusting doping concentration.
As shown in Figure 10, ninth embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, and the present embodiment is
The 4th base area 14-2 of second conductive type semiconductor, the second conductive type semiconductor the 4th are set on the basis of seven embodiments
Base area 14-2 is located on the first conductive type semiconductor drift region 7, and is located at first the second emitter region of conductive type semiconductor 15
With the lower section of the second conductive type semiconductor third base area 14-1, partly lead used in the 4th base area 14-2 of the second conductive type semiconductor
The forbidden bandwidth of body material is greater than or equal to first conductive type semiconductor the second emitter region 15 and the second conductive type semiconductor
The forbidden bandwidth of semiconductor material used in the 14-1 of third base area.
In above-described embodiment, when forward blocking, by the 4th base area of the second conductive type semiconductor and the first conduction type half
The reverse biased pn junction that conductor drift region is constituted carries out pressure resistance, since first the second emitter region of conductive type semiconductor and entire second is led
The 4th base area of the second conductive type semiconductor below electric type semiconductor third base area is made of wide-band gap material, so into one
Step improves the pressure resistance of entire device.
As shown in figure 11, tenth embodiment of the invention provides a kind of groove-shaped insulated gate bipolar transistor, and the present embodiment is
Second the second semiconductor layer of conduction type 16, second the second semiconductor layer of conduction type 16 are set on the basis of nine embodiments
Between emitter metal 4 and the second part of the second conductive type semiconductor third base area 14-1, the second conduction type
The forbidden bandwidth of semiconductor material used in two semiconductor layers 16 is less than used in the second conductive type semiconductor third base area 14-1 half
The forbidden bandwidth of conductor material.
In above-described embodiment, the forbidden bandwidth of semiconductor material used in second the second semiconductor layer of conduction type 16 is less than
The forbidden bandwidth of semiconductor material used in two conductive type semiconductor third base area 14-1, thus the two contact surface formed it is different
Matter knot, as shown in figure 13, the hetero-junctions enhance conductivity modulation effect when device forward conduction as hole barrier, reduce
Conduction voltage drop, to further improve the tradeoff between forward conduction voltage drop and turn-off power loss.
Second conduction type the second semiconductor layer 16 and the second conductive type semiconductor third base area 14-1 doping concentration can
It with identical, can also be different, change the barrier height of nonequilibrium carrier by adjusting doping concentration.
Eleventh embodiment of the invention provides a kind of manufacturing method of groove-shaped insulated gate bipolar transistor, including following step
It is rapid:
Second conductive type semiconductor collecting zone 9 of the second conductive type semiconductor substrate as device is chosen, is partly being led
The first conductive type semiconductor field stop layer 8 and the first conductive type semiconductor drift region 7 are sequentially formed on body substrate；
Side above the first conductive type semiconductor drift region 7 forms second the second base area of conductive type semiconductor 6-
2, the second conductive-type is formed on the first conductive type semiconductor drift region 7 and second the second base area of conductive type semiconductor 6-2
Type semiconductor base area 6-1,
It is conductive that the first conductive type semiconductor emitter region 3 and second is formed on the second conductive type semiconductor base area 6-1
Type semiconductor emitter region 5, the side of the first conductive type semiconductor emitter region 3 and the second conductive type semiconductor emitter region 5
Side contacts with each other；First conductive type semiconductor emitter region 3, the second conductive type semiconductor emitter region 5 and the second conductive-type
The forbidden bandwidth of semiconductor material used in type semiconductor base area 6-1 is less than second the second base area of conductive type semiconductor 6-2, first
Conductive type semiconductor drift region 7, the first conductive type semiconductor field stop layer 8 and the second conductive type semiconductor collecting zone 9
The forbidden bandwidth of semiconductor material used；
On the first conductive type semiconductor drift region 7 and the first conductive type semiconductor emitter region 3, the second conductive-type
The side of type semiconductor base area 6-1 and the first conductive type semiconductor drift region 7 forms trench gate structure；
Emitter gold is formed in the second conductive type semiconductor emitter region 5 and the first conductive type semiconductor emitter region 3
Belong to 4；
Metallization collector 10 is formed in the lower section of semiconductor chip.
In above-described embodiment, led for example, forming the first conductive type semiconductor field stop layer 8 and first by epitaxy technique
Electric type semiconductor drift region 7；
By epitaxy technique on the first conductive type semiconductor drift region 7 one layer of silicon carbide layer of extension, pass through photoetching work
Skill etches away a part of silicon carbide layer, then by epitaxy technique in one layer of silicon layer of device surface extension, by photoetching process, and
Ion implanting the second conductive type semiconductor type impurity, is then made annealing treatment, in the first conductive type semiconductor drift region 7
The side of top forms second the second base area of conductive type semiconductor 6-2, and in the first conductive type semiconductor drift region 7 and the
The second conductive type semiconductor base area 6-1 is formed on two the second base area of conductive type semiconductor 6-2；
By photoetching process, and to second conductive type semiconductor base area the second conductive type semiconductor of 6-1 ion implanting
Type impurity, is then made annealing treatment, and the side above the second conductive type semiconductor base area 6-1 forms the second conduction type
Semiconductor emission area 5；By photoetching process, and to second conductive type semiconductor base area the first conduction type of 6-1 ion implanting
Semi-conductor type impurity, is then made annealing treatment, and the other side above the second conductive type semiconductor base area 6-1 forms first
Conductive type semiconductor emitter region 3；
By photoetching process, the side above the first conductive type semiconductor drift region 7 carries out etching groove, etches
Gate trench, the depth of groove are more than the junction depth of the second conductive type semiconductor type base area, molten by HF after the completion of etching groove
Then the TEOS rinsed clean on surface is passed sequentially through oxidation and depositing technics and grows gate medium and grid conduction material in the trench by liquid
Material, thus on the first conductive type semiconductor drift region 7 and the first conductive type semiconductor emitter region 3, the second conductive-type
The side of type semiconductor base area 6-1 and the first conductive type semiconductor drift region 7 forms trench gate structure；
By evaporation or sputtering technology, then by etching technics, emitter metal 4 is formed；
Metallization collector 10 is formed by evaporation or sputtering technology, is thinned before forming metallization collector 10 and partly leads
The thickness of body substrate.
Optionally, before forming emitter metal 4, second is formed in the second conductive type semiconductor emitter region 5 and is led
Electric type semiconductor layer 12 forms hair in the first conductive type semiconductor emitter region 3 and second conductive type semiconductor layer 12
The forbidden bandwidth of emitter-base bandgap grading metal 4, semiconductor material used in second conductive type semiconductor layer 12 is partly led less than the second conduction type
The forbidden bandwidth of semiconductor material used in body emitter region 5.Wherein, by epitaxy technique in the second conductive type semiconductor emitter region
Second conductive type semiconductor layer 12 is epitaxially formed on 5.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with
It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists
Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of
First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below "
One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (12)
1. a kind of groove-shaped insulated gate bipolar transistor, comprising: metallization collector (10), the second conductive type semiconductor current collection
Area (9), the first conductive type semiconductor drift region (7), the first conductive type semiconductor field stop layer (8), the second conduction type
Semiconductor base area (6-1), second the second base area of conductive type semiconductor (6-2), the first conductive type semiconductor emitter region (3),
Second conductive type semiconductor emitter region (5), trench gate structure and emitter metal (4)；
Metallization collector (10) is located at the lower section of the second conductive type semiconductor collecting zone (9), the first conductive type semiconductor
Field stop layer (8) and the first conductive type semiconductor drift region (7) are sequentially located at the second conductive type semiconductor collecting zone (9)
On；
Second the second base area of conductive type semiconductor (6-2) is located at the side above the first conductive type semiconductor drift region (7)；
Second conductive type semiconductor base area (6-1) is located at the first conductive type semiconductor drift region (7) and the second conduction type is partly led
On the second base area of body (6-2)；
Second conductive type semiconductor emitter region (5) and the first conductive type semiconductor emitter region (3) are located side by side at the second conduction
On type semiconductor base area (6-1), and side contacts with each other；Emitter metal (4) is located at the transmitting of the second conductive type semiconductor
In area (5) and the first conductive type semiconductor emitter region (3)；
Trench gate structure is located on the first conductive type semiconductor drift region (7), and its close to emitter metal (4) side with
First conductive type semiconductor emitter region (3), the second conductive type semiconductor base area (6-1) and the drift of the first conductive type semiconductor
Move a side contacts of area (7)；
It is characterized in that, the first conductive type semiconductor emitter region (3), the second conductive type semiconductor emitter region (5) and second
The forbidden bandwidth of semiconductor material used in conductive type semiconductor base area (6-1) is less than second the second base area of conductive type semiconductor
(6-2), the first conductive type semiconductor drift region (7), the first conductive type semiconductor field stop layer (8) and the second conduction type
The forbidden bandwidth of semiconductor material used in semiconductor collecting zone (9).
2. a kind of groove-shaped insulated gate bipolar transistor according to claim 1, it is characterised in that: further include the first conduction
Type of carrier accumulation layer (11), the first conduction type carrier accumulation layer (11) are located at second the second base of conductive type semiconductor
Between area (6-2) and the first conductive type semiconductor drift region (7), and the side of the first conduction type carrier accumulation layer (11)
It is contacted with the side of trench gate structure, the doping concentration of the first conduction type carrier accumulation layer (11) is greater than the first conduction type
The doping concentration in drift semiconductor area (7).
3. a kind of groove-shaped insulated gate bipolar transistor according to claim 1, it is characterised in that: further include the second conduction
Type semiconductor layer (12), second conductive type semiconductor layer (12) are located at the second conductive type semiconductor emitter region (5) and hair
Between emitter-base bandgap grading metal (4), the forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer (12) is less than the second conduction
The forbidden bandwidth of semiconductor material used in type semiconductor emitter region (5).
4. a kind of groove-shaped insulated gate bipolar transistor according to claim 1, it is characterised in that: further include the second conduction
Type semiconductor layer (12), the second conductive type semiconductor layer (12) are located at the second conductive type semiconductor emitter region (5)
Inside, thickness are less than or equal to the thickness of the second conductive type semiconductor emitter region (5), second conductive type semiconductor layer (12)
The forbidden bandwidth of semiconductor material used is less than the second conductive type semiconductor emitter region (5) and the second conductive type semiconductor base
The forbidden bandwidth of semiconductor material used in area (6-1).
5. a kind of groove-shaped insulated gate bipolar transistor according to claim 1, it is characterised in that: further include the second conduction
Type shielded layer (13), the second conduction type shielded layer (13) are located at the first conductive type semiconductor drift region (7) and trench gate
Between structure, and the side and trench gate structure of the second conduction type shielded layer (13) one flanking far from emitter metal (4)
Touching.
6. a kind of groove-shaped insulated gate bipolar transistor according to claim 1-5, it is characterised in that: the ditch
The part gate electrode of slot grid structure is shorted the emitter metal (4).
7. a kind of groove-shaped insulated gate bipolar transistor according to claim 1-5, it is characterised in that: further include
First the second emitter region of conductive type semiconductor (15) and the second conductive type semiconductor third base area (14-1), the first conductive-type
The second emitter region of type semiconductor (15) and the second conductive type semiconductor third base area (14-1) are located at trench gate structure and first
Between conductive type semiconductor drift region (7), first the second emitter region of conductive type semiconductor (15) is located at the second conduction type
In semiconductor third base area (14-1), and the side of trench gate structure and first the second emitter region of conductive type semiconductor (15) and
One side contacts of the second conductive type semiconductor third base area (14-1)；Emitter metal (4) is also located at the first conduction type half
On the second emitter region of conductor (15), the second conductive type semiconductor third base area (14-1) and trench gate structure.
8. a kind of groove-shaped insulated gate bipolar transistor according to claim 7, it is characterised in that: further include the second conduction
The 4th base area (14-2) of type semiconductor, the 4th base area (14-2) of the second conductive type semiconductor are located at the second conduction type and partly lead
The top of the side of body third base area (14-1) first part and the first conductive type semiconductor drift region (7), and it is located at first
The lower section of the second emitter region of conductive type semiconductor (15) and second conductive type semiconductor third base area (14-1) second part,
The forbidden bandwidth of semiconductor material used in the 4th base area (14-2) of second conductive type semiconductor is greater than or equal to the first conductive-type
The forbidden band of semiconductor material used in the second emitter region of type semiconductor (15) and the second conductive type semiconductor third base area (14-1)
Width.
9. a kind of groove-shaped insulated gate bipolar transistor according to claim 7, it is characterised in that: further include the second conduction
The 4th base area (14-2) of type semiconductor, the 4th base area (14-2) of the second conductive type semiconductor are located at the first conduction type and partly lead
On body drift region (7), and it is located at first the second emitter region of conductive type semiconductor (15) and the second conductive type semiconductor third
The forbidden bandwidth of the lower section of base area (14-1), semiconductor material used in the 4th base area (14-2) of the second conductive type semiconductor is greater than
Or it is equal to used in first the second emitter region of conductive type semiconductor (15) and the second conductive type semiconductor third base area (14-1)
The forbidden bandwidth of semiconductor material.
10. a kind of groove-shaped insulated gate bipolar transistor according to claim 9, it is characterised in that: further include second leading
Electric the second semiconductor layer of type (16), second the second semiconductor layer of conduction type (16), which is located at emitter metal (4) and second, leads
Between the second part of electric type semiconductor third base area (14-1), second the second semiconductor layer of conduction type (16) is used partly to be led
Forbidden bandwidth of the forbidden bandwidth of body material less than semiconductor material used in the second conductive type semiconductor third base area (14-1).
11. a kind of manufacturing method of groove-shaped insulated gate bipolar transistor, which comprises the following steps:
Second conductive type semiconductor collecting zone (9) of the second conductive type semiconductor substrate as device is chosen, in semiconductor
The first conductive type semiconductor field stop layer (8) and the first conductive type semiconductor type drift region (7) are sequentially formed on substrate；
Side above the first conductive type semiconductor drift region (7) forms second the second base area of conductive type semiconductor (6-
2), second is formed on the first conductive type semiconductor type drift region (7) and second the second base area of conductive type semiconductor (6-2)
Conductive type semiconductor base area (6-1),
The first conductive type semiconductor emitter region (3) and the second conduction are formed on the second conductive type semiconductor base area (6-1)
Type semiconductor emitter region (5), the side of the first conductive type semiconductor emitter region (3) and the transmitting of the second conductive type semiconductor
Area (5) side contacts with each other；First conductive type semiconductor emitter region (3), the second conductive type semiconductor emitter region (5) and
The forbidden bandwidth of semiconductor material used in two conductive type semiconductor base areas (6-1) is less than second the second base of conductive type semiconductor
Area (6-2), the first conductive type semiconductor drift region (7), the first conductive type semiconductor field stop layer (8) and the second conductive-type
The forbidden bandwidth of semiconductor material used in type semiconductor collecting zone (9)；
On the first conductive type semiconductor drift region (7) and the first conductive type semiconductor emitter region (3), the second conductive-type
The side of type semiconductor base area (6-1) and the first conductive type semiconductor drift region (7) forms trench gate structure；
Emitter gold is formed in the second conductive type semiconductor emitter region (5) and the first conductive type semiconductor emitter region (3)
Belong to (4)；
Metallization collector (10) is formed in the lower section of semiconductor chip (9).
12. a kind of manufacturing method of groove-shaped insulated gate bipolar transistor according to claim 11, it is characterised in that: also
Comprising steps of it is conductive to form second in the second conductive type semiconductor emitter region (5) before forming emitter metal (4)
Type semiconductor layer (12), the shape in the first conductive type semiconductor emitter region (3) and second conductive type semiconductor layer (12)
At emitter metal (4), the forbidden bandwidth of semiconductor material used in second conductive type semiconductor layer (12) is conductive less than second
The forbidden bandwidth of semiconductor material used in type semiconductor emitter region (5).
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| CN111834450A (en) * | 2020-08-31 | 2020-10-27 | 电子科技大学 | SOI LIGBT device integrated with Zener diode |
| JP2021125536A (en) * | 2020-02-04 | 2021-08-30 | 株式会社デンソー | Nitride semiconductor device |
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| CN107452803A (en) * | 2016-05-24 | 2017-12-08 | 英飞凌科技股份有限公司 | Wide bandgap semiconductor device with trench gate structure |
| CN108258040A (en) * | 2017-12-26 | 2018-07-06 | 西安电子科技大学 | Igbt with wide band gap semiconducter substrate material and preparation method thereof |
| CN108389902A (en) * | 2018-04-28 | 2018-08-10 | 四川大学 | A kind of inverse conductivity type IGBT containing reverse groove grid |
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| US20170256642A1 (en) * | 2016-03-04 | 2017-09-07 | United Silicon Carbide, Inc. | Tunneling Field Effect Transistor |
| CN107452803A (en) * | 2016-05-24 | 2017-12-08 | 英飞凌科技股份有限公司 | Wide bandgap semiconductor device with trench gate structure |
| CN108258040A (en) * | 2017-12-26 | 2018-07-06 | 西安电子科技大学 | Igbt with wide band gap semiconducter substrate material and preparation method thereof |
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