CN110413116B

CN110413116B - FPGA-based steady-state visual evoked potential brain-computer interface system design method

Info

Publication number: CN110413116B
Application number: CN201910669448.5A
Authority: CN
Inventors: 谢俊; 张彦军; 曹国智; 薛涛; 徐光华; 李敏
Original assignee: Xian Jiaotong University
Current assignee: Xian Jiaotong University
Priority date: 2019-07-24
Filing date: 2019-07-24
Publication date: 2021-01-15
Anticipated expiration: 2039-07-24
Also published as: CN110413116A

Abstract

A steady state visual evoked potential brain-computer interface system design method based on FPGA, place the electroencephalogram signal acquisition electrode in the user's head occipital area, transmit the electroencephalogram signal measured to FPGA circuit board in real time and process; the visual stimulation unit is displayed on a user interface through an FPGA circuit board, a stimulation rectangle is turned over according to red and black colors in the stimulation process to form a flicker stimulation unit with fixed frequency, a user watches any stimulation unit of the user interface, a computer synchronously collects, stores and sends electroencephalograms of the user to the FPGA circuit board in real time, after the FPGA receives an ending instruction, the obtained electroencephalograms are subjected to fast Fourier transform, frequency components related to a stimulation paradigm are analyzed, and the stimulation target position where the frequency domain induced peak value of the electroencephalograms is located is calculated; the invention improves the execution efficiency of the brain-computer interface system and reduces the realization cost of the steady-state visual evoked potential brain-computer interface.

Description

FPGA-based steady-state visual evoked potential brain-computer interface system design method

Technical Field

The invention relates to the field of digital IC design of neural engineering, brain-computer interface technology and electronic information engineering in biomedical engineering, in particular to a design method of a steady-state visual evoked potential brain-computer interface system based on an FPGA (field programmable gate array).

Background

The brain-computer interface is a technology for establishing an abnormal neural pathway between the human brain and an external device, which converts an electroencephalogram signal into a control command of the device finally by measuring and analyzing the electroencephalogram signal. Because the data volume of the brain electrical signals is large and the processing algorithm is complex, the conventional brain-computer interface generally utilizes a computer to process the brain electrical signals and generate control instructions, and the implementation mode has higher cost and is not easy to widely popularize brain-computer interface equipment.

The Steady State Visual Evoked Potential (SSVEP) appears in a specific time and a specific area of the cerebral cortex, and compared with P300 event related potential, event related synchronous potential (ERS)/event related desynchronized potential (ERD) and the like, the brain-computer interface based on the steady state visual evoked potential has the advantages of high information transmission rate, strong anti-interference capability and the like, and has higher identification accuracy, so the brain-computer interface is more suitable for brain-computer interaction application. However, the evoked potential of the steady state visual evoked potential needs the light flicker with stable frequency for stimulation, and the phenomena of 'frame dropping' and the like are easy to occur in the process of the ordinary computer, so that a hardware device with better performance is needed to complete the process of generating the stimulation.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention aims to provide a design method of a steady-state visual evoked potential brain-computer interface system based on an FPGA, which combines the advantage that the FPGA can realize parallel operation, and correspondingly generates parallel modules of the FPGA from different functional modules of the steady-state visual evoked potential brain-computer interface, so that the operation of the parallel modules is not interfered with each other, thereby improving the execution efficiency of the brain-computer interface system and reducing the realization cost of the steady-state visual evoked potential brain-computer interface.

In order to achieve the purpose, the invention adopts the technical scheme that:

a design method of a steady-state visual evoked potential brain-computer interface system based on an FPGA comprises the following steps:

step 1, placing n electroencephalogram signal measuring electrodes in a visual occipital area of the head of a user through an electroencephalogram cap, placing a ground electrode in the forehead position, placing a reference electrode in any earlobe position, and transmitting the measured electroencephalogram signals to a computer after amplification and analog-to-digital conversion operations of acquisition equipment to realize acquisition of electroencephalogram signals in a visual area;

step 2, presenting m steady-state stimulation units which are turned over according to different frequencies at corresponding positions of a user interface, wherein m is larger than or equal to 2, the stimulation units are red-black flickering rectangles generated by an FPGA circuit board, and the distance from the head of the stimulation units to a computer screen is 50-80 cm when a user watches the stimulation units;

the stimulation units flickering at different frequencies are displayed at m fixed positions on the screen, and the display frequency is determined according to the screen refresh rate to obtain a good display effect; the number of frames for holding the red-black flashing rectangle is determined by the specific set frequency of each stimulation unit, and the specific calculation formula is as follows:

in the formula, i: the serial number of the representative stimulation target takes the values as follows: 1 to m

R: for the screen refresh rate

f_i: the flicker frequency of the ith stimulation unit

F_i: number of frames for which the red or black rectangle in the ith stimulation unit persists

Calculating color turnover frame numbers of the four stimulation units according to the formula (1), and performing color turnover in the region where the stimulation units are located according to the turnover frame numbers in the stimulation time to generate continuous stimulation display;

step 3, after m stimulation units are generated, the computer controls the stimulation units to start displaying the visual stimulation units generated in the step 2 by sending instructions, the acquired electroencephalogram signals are sent to the FPGA circuit board in real time and stored in the FPGA end, after stimulation is started for a certain time, the computer sends a stimulation ending instruction, the FPGA circuit board controls the stimulation unit to end displaying, the electroencephalogram signals are processed at the FPGA end through Fast Fourier Transform (FFT), frequency domain peak values corresponding to stimulation frequencies are compared after FFT, and the stimulation unit to which the flicker frequency corresponding to the maximum value belongs is judged as a stimulation target watched by a user;

and 4, after the judgment of the stimulation target in the step 3 is completed, displaying the judged result on a user interface, completing a steady-state visual evoked potential brain-computer interface identification task, returning to the step 2 after a plurality of seconds, and ending the next task until all the set steady-state visual evoked potential brain-computer interface tasks are completed.

The step 2 is realized by the stimulation unit in the following way: the FPGA-based video signal interface control is realized through an FPGA programming language, stimulation targets with different flicker frequencies are displayed on a user interface, the FPGA programming language is Verilog HDL or VHDL, and the FPGA video signal interface is VGA, HDMI or DVI.

The step 2 is realized by the stimulation unit in the following way: adopting VGA interface video signals, selecting the model of a display screen, determining the parameters of the display screen and corresponding transmission parameters, compiling a corresponding FPGA stimulation generation module at an FPGA end, and controlling a user interface to display a corresponding stimulation unit; the display screen parameters are screen refresh rate, resolution and driving clock, and the transmission parameters are timing parameters.

The FPGA stimulation generation module realizes the following functions: generating a video driving clock corresponding to the resolution and the refresh rate, and generating scanning signals in the line direction and the field direction through the video driving clock, wherein the scanning process in the line direction or the field direction is divided into the following steps according to the scanning time sequence: four stages of synchronous pulse, back porch pulse, display pulse and front porch pulse; in the VGA scanning process, the synchronous pulse is used for generating a line and field synchronous signal, namely the line synchronous signal is pulled up by a line synchronous pulse scanning unit at the initial position of a line to generate line synchronous logic signal output, and similarly, the field synchronous logic signal output can be generated, wherein the scanning unit is the video driving clock period in the line direction and the sum of the video driving clock periods used for scanning one line in the field direction; after generating the synchronous signal, preparing to start scanning along pulse scanning units after delaying; after the back edge pulse stage, scanning a display effective area formed by display pulse crossing areas in the line direction and the field direction, wherein the size of the display effective area corresponds to the resolution of a screen; after the effective area is displayed, scanning the leading edge pulse scanning units to prepare for next synchronization; in the display effective area, the scanning points at the determined positions on the screen are required to be color-reversed only when the display effect required by the electroencephalogram stimulator is required to be generated.

The specific operation steps of the step 3 are as follows:

step 3-1, appointing a start instruction and an end instruction at a computer end and an FPGA end, then sending the start instruction at the computer end in a serial port mode, enabling stimulation units to start presenting, enabling a user to watch any stimulation unit, and recording the stimulation unit as a stimulation target, and enabling other stimulation units as non-stimulation targets;

step 3-2, after the stimulation unit is displayed on the user interface in the step 3-1, acquiring electroencephalogram signals through a computer, preprocessing the electroencephalogram signals, and sending the electroencephalogram signals to the FPGA circuit board in real time;

step 3-3, after the electroencephalogram signal is sent by the computer terminal in the step 3-2, storing the electroencephalogram signal to an FPGA terminal, realizing FFT based on the FPGA, and including FFT conversion and electroencephalogram signal feature identification after the conversion; in the FFT conversion state, the FPGA starts to read electroencephalogram data from a corresponding RAM, transmits the electroencephalogram data into an FFT core according to continuous clock rising edges for conversion, waits for data output and stores a converted result in the RAM, and controls a state control module to jump to a data processing state through an FFT conversion end mark after the data storage is finished; and in the electroencephalogram signal characteristic identification state, further processing the result after the FFT conversion to obtain electroencephalogram signal frequency response corresponding to each flicker frequency, and judging the stimulation unit to which the flicker frequency corresponding to the maximum value belongs as the stimulation target watched by the user.

The specific process of the step 3-2 is as follows: filtering and trapping the electroencephalogram signals at a computer terminal, reading the electroencephalogram signals according to a electroencephalogram acquisition device register reading mode, and sending the electroencephalogram signals to an FPGA terminal;

the specific sending process comprises the following steps: firstly, preprocessing data so as to facilitate data transmission and FPGA end processing; secondly, carrying out point-by-point transmission or multipoint transmission on the electroencephalogram signals at the computer terminal according to the data acquisition rule of the electroencephalogram acquisition equipment; then, receiving data at the FPGA end according to a computer end data sending protocol, considering the electroencephalogram data precision requirement, the number of the sent single-point data is wide, bit splicing needs to be carried out at the FPGA end, and a single data point end mark is appointed at the receiving and sending parties; finally, when the FPGA end receives the end mark, the data is stored in an RAM inside the FPGA; and after the set stimulation time is over, the computer end sends a stop instruction, the FPGA controls the stimulation unit to stop displaying, and the computer end stops sending data.

The invention has the beneficial effects that:

(1) compared with the method for generating steady-state visual evoked stimulus by a computer system, the method relies on the mode of generating stimulus by the FPGA, and can construct a special display module which runs in parallel with other modules, thereby realizing the stable running of a flicker paradigm, preventing the problems of frame dropping and the like in stimulus presentation, reducing the requirements on computer software and hardware, and saving the development cost of a brain-computer interface device;

(2) aiming at electroencephalogram signal processing algorithms which are similar to FFT and can be operated in parallel, the FPGA provides a real-time and efficient parallel processing solution for massive electroencephalogram data, and therefore the operation efficiency of a brain-computer interface is improved to a certain extent.

Drawings

FIG. 1 is a schematic diagram of the process of the present invention.

FIG. 2 is a diagram of the placement of the EEG signal collecting electrodes according to the present invention.

Fig. 3 is a diagram of a distribution of stimulation units according to the present invention.

FIG. 4 is a flowchart of the VGA visual stimulation module of the present invention.

FIG. 5 shows the VGA display active area of the present invention.

FIG. 6 is a flow chart of FPGA data processing of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Referring to fig. 1, a method for designing a steady-state visual evoked potential brain-computer interface system based on an FPGA includes the following steps:

step 1, as shown in figure 2, according to the international standard lead 10-20 system, placing an EEG signal measuring electrode on PO of the head visual pillow area of a user through an EEG cap₃、PO_z、PO₄、O₁、O_zAnd O₂Position, placing ground electrode at Fpz position of forehead, at any earlobe position A₁Or A₂A reference electrode is arranged, and the measured electroencephalogram signals are amplified, subjected to analog-to-digital conversion and the like by professional acquisition equipment and then transmitted to a computer terminal;

step 2, referring to fig. 3, four steady-state stimulation units which are turned over according to different frequencies are presented at corresponding positions of a user interface, each stimulation unit is a red-black flickering rectangle generated by an FPGA, when a user gazes at each stimulation unit, the head of each stimulation unit is about 60cm away from a computer screen, the four stimulation units are displayed on the user interface according to the layout shown in fig. 3, the screen resolution is selected to be 1680 × 1050 pixels, each stimulation unit is 210 pixels long and 158 pixels wide, the distance between each stimulation unit and the left and right screen boundaries is 210 pixels, and the distance between each stimulation unit and the upper and lower screen boundaries is 105 pixels;

the stimulation unit is realized by the following steps: the VGA interface control based on the FPGA is realized through an FPGA programming language Verilog HDL, and stimulation targets with different flicker frequencies are displayed on a user interface, and the specific process is as follows:

firstly, selecting a display screen model, determining display screen parameters and corresponding transmission parameters, wherein a VGA interface protocol is used as a transmission protocol between an FPGA and a display, and the display selects an associative LT2252wD type liquid crystal display, wherein the main parameters are shown in Table 1.

TABLE 1 LT2252wD display parameters

Model number	Size of screen	Best resolution	Video interface	Refresh rate
					LT2252wD	22 inches	1680×1050	D-Sub(VGA)、DVI-D	60Hz

For the display screen parameters, according to the recommended parameters of the associative LT2252wD type display screen: the refresh rate is 60Hz, the resolution is 1680 × 1050, the video display clock is selected to be 147MHz, the counting pulse parameters are shown in Table 2, wherein the scanning process in the line or field direction is divided into: a synchronization pulse, a back porch pulse, a display pulse and a front porch pulse; the 15-pin VGA interface transmits signals through analog quantity, and the display interface comprises three transmission signals: the color voltage transmission device comprises three color voltage transmission signals of a line synchronizing signal HSYNC, a field synchronizing signal VSYNC and RGB, wherein the color voltage range is 0-0.7V, synchronization is completed by coordination of the HSYNC and the VSYNC, and the state is determined by fixed clock beats among the HSYNC, the VSYNC and the color signals.

TABLE 2 Driving timing parameter Table

Row/column	Synchronization pulse	Posterior border pulse	Display pulse	Leading edge pulse	Frame length
						Column(s) of	3	33	1050	1	1087
Line of	184	288	1680	104	2256

And then writing a corresponding FPGA stimulation unit generation module at the FPGA end, and controlling a user interface to display the corresponding stimulation unit.

The flow of the stimulation signal generated by the FPGA stimulation generation module is shown in fig. 4, and the function realized by the FPGA stimulation generation module is as follows: inputting a video driving clock corresponding to the resolution and the refresh rate, namely introducing a video display clock corresponding to the display resolution into a stimulation unit generation module, and adding an input serial port display control signal;

generating line direction and field direction scan signals by a video drive clock: generating scanning signals by counting in X and Y directions of a display, recording the X-direction count as xcnt, the Y-direction count as ycnt, generating a rectangular area by the xcnt and the ycnt through the rising edge of a video driving clock along the driving count, wherein the maximum value of the xcnt count is the length of a horizontal frame in a table 2, and adding one to the Y-direction count when the X-direction count reaches one maximum value under the condition that the Y-direction value is judged to be not larger than the length of the horizontal frame;

generation of line and field synchronizing signals: in the process of counting in the X direction, the line synchronizing signal is pulled up by line synchronizing pulses (HST) scanning units (the scanning unit is the video driving clock period in the line direction and is the sum of the video driving clock periods used for scanning a line in the field direction) in the table 2 at the initial position of each line, and line synchronizing logic signal output is generated; generating a field sync logic signal output according to a field sync pulse (VST) during the Y-direction counting in the same manner;

generation of display effective area: consistent with the generation mode of the line and field synchronization signals, as shown in fig. 5, when X, Y completes the generation of the synchronization signal, xcnt or ycnt counts in the line direction or the field direction and then enters the effective display area (Valid area in the figure) along the pulse scanning unit HBP or VBP, and the size of the effective display area is 1680 × 1050; when the X, Y direction effective display area count is finished, the xcnt or ycnt count is leading pulse scanning units (HFP and VFP in fig. 4) to finish scanning of one frame of display data;

final stimulation unit signal transformation: in the VGA scanning process, the position of each scanning point on the rising edge of each clock is determined, and the scanning points at the determined positions on the screen are required to be subjected to color inversion at the determined time points to generate the display effect required by the electroencephalogram stimulator, so that rectangles flickering at different frequencies are required to be displayed at 4 positions shown in figure 3, wherein the display frequency is determined by taking a screen refreshing frame as a unit to obtain a better display effect; the number of red-black holding frames of the stimulation units is determined by the specific set frequency of each stimulation unit, and the specific calculation formula is as follows:

in the formula, i: the serial numbers representing the stimulation targets may be 1, 2, 3 and 4

R: for the screen refresh rate

f_i: flicker frequency for the ith stimulation target

F_i: number of frames in which red or black persists for the ith stimulation target

Calculating the color turnover frame number of the four stimulation units according to the formula (1), and carrying out color turnover in the region where the screen paradigm is located according to the turnover frame number in the stimulation time to generate continuous stimulation unit display; in the experimental process, the selected LT2252wD VGA display screen has a refresh rate of 60Hz, and when the visual stimulation frequency is selected to be 7-15 Hz, the display requirements of the stimulation unit can be basically met, and it can be known through calculation according to formula (1), parameters such as selectable frequency, refresh frame number and the like are shown in Table 3, wherein the red-black duty ratio is the percentage of the total frame number of one complete turnover of a red rectangular block.

TABLE 3 stimulation paradigm of frequency of turns over and number of refresh frames

Stimulation unit numbering	Refresh frame number (frame)	Turnover frequency (Hz)	Red-black duty cycle
				1	7	8.57	57.14％
2	6	10	50％
				3	5	12	60％
4	4	15	50％

In order to determine a graph display area, the xcnt or ycnt value is judged through four parallel running processes in the FPGA, and when the display area is scanned, the determined display area mark is changed into 1 (the non-paradigm display area mark is 0), so that a position switch signal is obtained; after the xcnt or ycnt value finishes scanning a frame of data, judging whether to turn over the color according to the refresh frame number of each stimulation unit, thereby obtaining a turning-over switch signal; after the position switch signal and the turnover switch signal are obtained, whether a display area on a display screen meets the turnover requirement is determined through AND operation, and when the UART display control signal is judged to be also in a high level under the condition that the position switch signal and the turnover switch signal meet, the color at the position is finally turned over and is continued until next frame data is scanned to the position;

step 3, after four stimulation units are generated according to the mode of the step 2, the computer controls the stimulation units to start or end stimulation by sending instructions, and the specific operation steps are as follows:

step 3-1, a corresponding start instruction (such as a colon mark:) and an end instruction are appointed at the computer end and the FPGA end, the start instruction colon mark:' appointed with the FPGA end is sent at the computer end in an ASCII code mode through a serial port, a stimulation unit starts to be presented, the total stimulation duration is set to be 4 seconds, a user watches any stimulation unit, the stimulation unit is recorded as a stimulation target, and other stimulation units are non-stimulation targets;

step 3-2, acquiring electroencephalogram signals through a computer, sending the electroencephalogram signals to an FPGA (field programmable gate array) end in real time, and performing Fast Fourier Transform (FFT) on the FPGA end after stimulation is finished to calculate a stimulation target corresponding to an evoked peak value of the electroencephalogram signal frequency domain;

the detailed process comprises the following steps: collecting electroencephalogram signals by using an amplifier and an electroencephalogram cap at a computer terminal, carrying out 0.5-100 Hz band-pass filtering, carrying out 48-52 Hz trapping operation on 50Hz power frequency interference, reading the electroencephalogram signals according to a register reading mode of electroencephalogram collecting equipment, and sending the electroencephalogram signals to an FPGA (field programmable gate array) terminal; the specific sending process comprises the following steps: firstly, rounding electroencephalogram data by adopting MTALAB programming at a computer end, converting the data into a 16-bit binary complement form, and finally converting the data into hexadecimal for sending in order to save sending time, wherein for example, the data of the electroencephalogram is-5.43, rounded and converted into FFFB, so that the data preprocessing process is completed; secondly, carrying out point-by-point sending or multipoint sending of electroencephalogram signals at a computer end according to data acquisition rules of electroencephalogram acquisition equipment, wherein the sending of the electroencephalogram signals is completed through a universal asynchronous receiver/transmitter (UART) transmission protocol, the baud rate is 115200bps, the data frame format is composed of 1-bit start bits, 8-bit data bits, no-data check bits and 1-bit stop bits, when data are transmitted, the 1-bit start bits are sent firstly, then the 8 data bits and the 1-bit stop bits are continuously transmitted, and the data are transmitted according to an ASCII code mode;

step 3-3, after sending the electroencephalogram signal at the computer end, receiving and storing the electroencephalogram signal to the FPGA, realizing Fast Fourier Transform (FFT) based on the FPGA, which comprises the steps of electroencephalogram signal data access, FFT conversion and feature identification of the electroencephalogram signal after conversion, as shown in FIG. 6, adding a state machine for realizing the ordered data processing process, mainly realizing three processes of data storage, FFT operation state and final data processing, and introducing the detailed process as follows:

(1) when the FPGA is powered on or reset, the state machine controls the current state to be a data storage state and sets the current state to be a data storage operation only after sending a stimulation starting instruction; after receiving a data storage instruction, the data processing module waits for the rising edge of a data input zone bit (generated after receiving a space instruction by the FPGA), performs data storage once after obtaining the rising edge of the data input zone bit, and accumulates storage addresses at the falling edge of the data input zone bit until all data are completely stored; the data storage process comprises the following steps: the obtained data bits are decoded and converted at the FPGA end according to an ASCII code mode, four bits in 16-bit electroencephalogram data can be obtained, bit splicing is carried out according to the sequence, the 16-bit electroencephalogram data can be restored, and a blank space is used as an end mark for completing transmission of an electroencephalogram signal in the embodiment, so that a one-bit data receiving end mark is output on a data receiving module after the blank space is received, and the electroencephalogram data is output; considering that the data volume of the electroencephalogram signal is relatively small, the data are stored in an RAM inside an FPGA (field programmable gate array) in an FPGA data processing module, the electroencephalogram data are only stored and read at different times in the design, and a mode Simple Dual-port RAM is adopted; after data acquisition is carried out for 4 seconds, sending a specified ending instruction semicolon at a computer end; "end current data acquisition and transmission operation; setting a data storage end mark and transmitting the data storage end mark to a next-stage state control module by a data processing module;

(2) after the state control module receives a data storage end mark signal, the state machine converts the current state into an FFT data operation state, starts to read electroencephalogram data from the RAM and transmits the electroencephalogram data into an FFT core for conversion according to continuous clock rising edges, waits for data output and stores the converted result in the RAM, and after the data storage is finished, controls the state control module to jump to a data processing state through the FFT conversion end mark;

(3) further processing the result after FFT conversion in the electroencephalogram signal characteristic identification state to obtain an electroencephalogram signal frequency response corresponding to each flicker frequency, comparing frequency domain peak values of each point in 8.5Hz, 8.75Hz, 9.75Hz, 10Hz, 10.25Hz, 11.75Hz, 12Hz, 12.25Hz, 14.75Hz, 15Hz and 15.25Hz in consideration of non-whole period truncation influence, and determining a stimulation unit to which the flicker frequency corresponding to the maximum value belongs as a stimulation target watched by the user;

and 4, after the FPGA end finishes position judgment, the FPGA displays a judged target on a user interface, a steady-state visual evoked potential brain-computer interface identification task is finished, after a plurality of seconds, the FPGA returns to the step 2 to carry out the next task until all the set steady-state visual evoked potential brain-computer interface tasks are finished.

Claims

1. A design method of a steady-state visual evoked potential brain-computer interface system based on FPGA is characterized by comprising the following steps:

step 1, placing n electroencephalogram signal measuring electrodes in a visual occipital area of the head of a user through an electroencephalogram cap, placing a ground electrode at the forehead position, placing a reference electrode at any earlobe position, and transmitting the measured electroencephalogram signals to a computer terminal after amplification and analog-to-digital conversion operations of acquisition equipment;

step 2, presenting m steady-state stimulation units which are turned over according to different frequencies at corresponding positions of a user interface, wherein m is larger than or equal to 2, the stimulation units are red-black flickering rectangles generated by the FPGA, and the distance from the head of the stimulation units to a computer screen is 50-80 cm when a user watches the stimulation units;

R: for the screen refresh rate

f_i: the flicker frequency of the ith stimulation unit

2. The method for designing the FPGA-based steady-state visual evoked potential brain-computer interface system according to claim 1, wherein the step 2 stimulation unit is realized by: the FPGA-based video signal interface control is realized through an FPGA programming language, stimulation targets with different flicker frequencies are displayed on a user interface, the FPGA programming language is Verilog HDL or VHDL, and the FPGA video signal interface is VGA, HDMI or DVI.

3. The method for designing the FPGA-based steady-state visual evoked potential brain-computer interface system according to claim 2, wherein the step 2 stimulation unit is realized by: adopting VGA interface video signals, selecting the model of a display screen, determining the parameters of the display screen and corresponding transmission parameters, compiling a corresponding FPGA stimulation generation module at an FPGA end, and controlling a user interface to display a corresponding stimulation unit; the display screen parameters are screen refresh rate, resolution and driving clock, and the transmission parameters are timing parameters.

4. The method for designing the FPGA-based steady-state visual evoked potential brain-computer interface system according to claim 3, wherein the FPGA stimulus generation module implements the following functions: generating a video driving clock corresponding to the resolution and the refresh rate, and generating scanning signals in the line direction and the field direction through the video driving clock, wherein the scanning process in the line direction or the field direction is divided into the following steps according to the scanning time sequence: four stages of synchronous pulse, back porch pulse, display pulse and front porch pulse; in the VGA scanning process, the synchronous pulse is used for generating line and field synchronous signals, namely the line synchronous signals are pulled up by scanning units of the line synchronous pulse at the initial position of a line to generate line synchronous logic signal output, and field synchronous logic signal output can be generated in the same way; the scanning unit is the video driving clock period in the row direction and the sum of the video driving clock periods used for scanning one row in the field direction; after generating the synchronous signal, preparing to start scanning along pulse scanning units after delaying; after the back edge pulse stage, scanning a display effective area formed by display pulse crossing areas in the line direction and the field direction, wherein the size of the display effective area corresponds to the resolution of a screen; after the effective area is displayed, scanning the leading edge pulse scanning units to prepare for next synchronization; in the display effective area, the scanning points at the determined positions on the screen are required to be color-reversed only when the display effect required by the electroencephalogram stimulator is required to be generated.

5. The method for designing the FPGA-based steady-state visual evoked potential brain-computer interface system according to claim 1, wherein the specific operation steps of step 3 are as follows:

step 3-1, a start instruction and an end instruction appointed by a computer end and an FPGA end are sent at the computer end in a serial port mode, a stimulation unit starts to be presented, a user watches any stimulation unit and records the stimulation unit as a stimulation target, and other stimulation units are non-stimulation targets;

step 3-3, after the electroencephalogram signal is sent by the computer terminal in the step 3-2, storing the electroencephalogram signal in the FPGA, and realizing Fast Fourier Transform (FFT) based on the FPGA, including FFT conversion and electroencephalogram signal feature identification after the FFT conversion; in the FFT conversion state, the FPGA starts to read electroencephalogram data from a corresponding RAM, transmits the electroencephalogram data into an FFT core according to continuous clock rising edges for conversion, waits for data output and stores a converted result in the RAM, and controls a state control module to jump to a data processing state through an FFT conversion end mark after the data storage is finished; and in the electroencephalogram signal characteristic identification state, further processing the result after the FFT conversion to obtain electroencephalogram signal frequency response corresponding to each flicker frequency, and judging the stimulation unit to which the flicker frequency corresponding to the maximum value belongs as the stimulation target watched by the user.

6. The method for designing the FPGA-based steady-state visual evoked potential brain-computer interface system according to claim 5, wherein the specific process of the step 3-2 is as follows: filtering and trapping the electroencephalogram signals at a computer terminal, reading the electroencephalogram signals according to a electroencephalogram acquisition device register reading mode, and sending the electroencephalogram signals to an FPGA terminal;