CN110411392B - Method for measuring width of nano-strip or nano-sheet of semiconductor device - Google Patents
Method for measuring width of nano-strip or nano-sheet of semiconductor device Download PDFInfo
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- CN110411392B CN110411392B CN201910643890.0A CN201910643890A CN110411392B CN 110411392 B CN110411392 B CN 110411392B CN 201910643890 A CN201910643890 A CN 201910643890A CN 110411392 B CN110411392 B CN 110411392B
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- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
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Abstract
The invention discloses a method for measuring the width of a nano strip or a nano sheet of a semiconductor device, which comprises the following steps: step one, obtaining a relation curve of temperature change generated by self-heating effect of the nano-strip or nano-sheet and self-heating effect index; step two, providing a tested semiconductor device with nano strips or nano sheets; step three, testing the temperature change of the nano-strip or nano-sheet of the tested semiconductor device by adopting a self-heating effect; and step four, combining the temperature change and the relation curve of the nano-strip or nano-sheet of the tested semiconductor device to obtain the self-heating effect index of the nano-strip or nano-sheet of the tested semiconductor device and further obtain the width of the nano-strip or nano-sheet of the tested semiconductor device. The invention has non-destructive property, can improve the measuring speed and reduce the test complexity, can carry out multi-surface measurement, can carry out multi-sample measurement and form a distribution diagram, and has high connection with the electrical yield.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for measuring the width of a nano-strip or a nano-sheet of a semiconductor device.
Background
Compared with a planar transistor, the fin transistor (FinFET) has a three-dimensional channel structure, so that the fin transistor has better on-current and off-current characteristics; short Channel Effects (SCE) can also be improved, as can Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (SS). Fig. 1 is a perspective view of a conventional fin transistor; the fin transistor includes a fin 102, the fin 102 being composed of nano-strips or nano-sheets formed of a semiconductor material formed on a semiconductor substrate 101. The semiconductor material of the fin 102 includes silicon or silicon germanium. The fins 102 on the same semiconductor substrate 101 are arranged in parallel, and a dielectric layer 103 is isolated between the fins 102.
The gate structure covers the top surface and the side surfaces of the fin body 102 with a partial length, and the surface of the fin body 102 covered by the gate structure is used for forming a channel. As can be seen in fig. 1, the fin 102 has channels on the top surface and on both sides as indicated by arrows 108.
In fig. 1, the gate structure includes a gate dielectric layer 104 and a gate conductive material layer 105 stacked together. The gate dielectric layer 104 is made of a gate oxide layer; alternatively, the material of the gate dielectric layer 104 includes a high dielectric constant material (HK). The gate conductive material layer 105 is a Metal Gate (MG); alternatively, the gate conductive material layer 105 is a polysilicon gate.
A source region 106 and a drain region 107 are formed in the fin 102 on either side of the gate structure.
Since the channel is formed directly on the surface of the fin 102 covered by the gate structure, the width of the fin 102 has a significant impact on the device performance, and the width of the fin 102 is often measured. The widths of the fin bodies 102 are all in the nanometer level, and the widths of the fin bodies 102 cannot be directly measured after the devices are formed, so that the semiconductor devices are often sliced in the existing method and then are measured by imaging with a Transmission Electron Microscope (TEM). When TEM pictures are used for analysis, the method has the following defects:
because slicing is performed, it is destructive; meanwhile, the measuring speed is also slower; a TEM picture can only analyze one side, so only one plane can be tested; in addition, the number of samples that can be measured by the TEM is small and the process is complicated; as well as electrical yield connections.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for measuring the width of a nano strip or a nano sheet of a semiconductor device, which is non-destructive and can improve the measuring speed and reduce the test complexity.
In order to solve the technical problem, the method for measuring the width of the nano-strip or nano-sheet of the semiconductor device provided by the invention comprises the following steps:
step one, obtaining a relation curve between temperature change generated by Self-Heating Effect (SHE) of a nano strip or a nano sheet and Self-Heating Effect index (index); the self-heating effect index is related to the height and width of the nanoslabs or nanoplatelets.
And step two, providing the tested semiconductor device with the nano-strip or the nano-sheet.
And step three, testing the temperature change of the nano-strip or nano-sheet of the tested semiconductor device by adopting a self-heating effect.
And step four, combining the temperature change of the nano-strip or nano-sheet of the tested semiconductor device with the relation curve to obtain the self-heating effect index of the nano-strip or nano-sheet of the tested semiconductor device, and obtaining the width of the nano-strip or nano-sheet of the tested semiconductor device through the obtained self-heating effect index of the nano-strip or nano-sheet of the tested semiconductor device.
In a further improvement, the self-heating effect index is proportional to the ratio of the height to the width of the corresponding nanoslabs or nanoplatelets.
In a further improvement, in the first step, a linear regression model (linear regression model) with a linear relationship between the temperature change and the self-heating effect index is obtained through the relationship curve.
In a further refinement, the relationship curve is obtained over a plurality of learning cycles (learning cycles).
In a further improvement, the semiconductor device is a fin transistor.
In a further refinement, the fin transistor includes a fin comprised of a nanoribbon or nanosheet formed of a semiconductor material.
In a further improvement, the gate structure covers the top surface and the side surfaces of the fin body with a part of the length, and the surface of the fin body covered by the gate structure is used for forming a channel.
In a further improvement, a source region and a drain region are formed in the fin body on both sides of the gate structure.
In a further improvement, the gate structure comprises a gate dielectric layer and a gate conductive material layer which are stacked.
The further improvement is that the gate dielectric layer is made of a gate oxide layer; or the material of the gate dielectric layer comprises a high dielectric constant material.
The further improvement is that the grid conductive material layer is a polysilicon grid; or, the grid conductive material layer is a metal grid.
In a further refinement, the semiconductor material of the fin includes silicon or silicon germanium.
The further improvement is that the fin bodies on the same semiconductor substrate are arranged in parallel, and dielectric layers are isolated among the fin bodies.
In a further improvement, an embedded epitaxial layer is formed in the source region or the drain region.
In a further improvement, the material of the embedded epitaxial layer comprises silicon germanium.
The method combines the self-heating effect of the nano-strip or nano-sheet, obtains the self-heating effect index by measuring the temperature change of the self-heating effect and combining the relation curve of the temperature change generated by the self-heating effect of the nano-strip or nano-sheet and the self-heating effect index, and obtains the width of the nano-strip or nano-sheet from the self-heating effect index, and compared with the technical scheme that the width of the nano-strip or nano-sheet is tested by adopting a TEM (transmission electron microscope) photo in the prior art, the method does not need to be sliced, so that the method is nondestructive measurement, and has high testing speed and low testing cost; the invention can realize the measurement of the widths of a plurality of planes, thereby being beneficial to the measurement of the widths of the nano strips or nano sheets of the three-dimensional structure on each surface; the invention has simple test, can measure the width of each nano strip or nano sheet on the whole semiconductor substrate and form a measuring result distribution map (mapping), thereby being beneficial to monitoring the width of each nano strip or nano sheet on the whole semiconductor substrate; the invention has very high connection with the electrical yield of the product and can well detect the yield of the product.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a perspective view of a conventional fin transistor;
FIG. 2 is a flow chart of a method of measuring the width of a nano-strip or nano-sheet of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a relationship curve obtained in one step of the method according to the embodiment of the present invention.
Detailed Description
As shown in fig. 2, it is a flowchart of a method for measuring the width of a nano-strip or a nano-sheet of a semiconductor device according to an embodiment of the present invention; the method for measuring the width of the nano strip or the nano sheet of the semiconductor device comprises the following steps:
step one, obtaining a relation curve of temperature change generated by self-heating effect of the nano-strip or nano-sheet and self-heating effect index; the self-heating effect index is related to the height and width of the nanoslabs or nanoplatelets. The self-heating effect index is proportional to the ratio of the height and width of the corresponding nano-strip or nano-sheet.
In the embodiment of the invention, a linear regression model with a linear relation between the temperature change and the self-heating effect index is obtained through the relation curve; the relationship curve is obtained through a plurality of learning cycles. Referring to fig. 3, which is a relationship curve obtained in one step of the method according to the embodiment of the present invention, the abscissa is the index of self-heating effect, and the ordinate is the temperature variation value Δ T, it can be seen that the curve 201 is a linear curve.
The semiconductor device is a fin transistor, and the structure of the fin transistor is shown in fig. 1. The fin transistor includes a fin 102, the fin 102 being composed of nano-strips or nano-sheets formed of a semiconductor material formed on a semiconductor substrate 101. The semiconductor material of the fin 102 includes silicon or silicon germanium. The fins 102 on the same semiconductor substrate 101 are arranged in parallel, and a dielectric layer 103 is isolated between the fins 102.
The gate structure covers the top surface and the side surfaces of the fin body 102 with a partial length, and the surface of the fin body 102 covered by the gate structure is used for forming a channel. As can be seen in fig. 1, the fin 102 has channels on the top surface and on both sides as indicated by arrows 108.
In fig. 1, the gate structure includes a gate dielectric layer 104 and a gate conductive material layer 105 stacked together. The material of the gate dielectric layer 104 includes a high dielectric constant material. In other embodiments, this can also be: the gate dielectric layer 104 is made of a gate oxide layer.
The gate conductive material layer 105 is a metal gate. In other embodiments can also be: the gate conductive material layer 105 is a polysilicon gate.
A source region 106 and a drain region 107 are formed in the fin 102 on either side of the gate structure.
An embedded epitaxial layer is formed in the source region 106 or the drain region 107.
The material of the embedded epitaxial layer comprises silicon germanium.
And step two, providing the tested semiconductor device with the nano-strip or the nano-sheet.
And step three, testing the temperature change of the nano-strips or nano-sheets of the tested semiconductor device by adopting the self-heating effect, as shown in the delta T test in figure 3.
And step four, combining the temperature change of the nano-strip or nano-sheet of the tested semiconductor device with the relation curve to obtain the self-heating effect index of the nano-strip or nano-sheet of the tested semiconductor device, and obtaining the width of the nano-strip or nano-sheet of the tested semiconductor device through the obtained self-heating effect index of the nano-strip or nano-sheet of the tested semiconductor device. As shown in fig. 3, the self-heating effect index can be obtained by measuring the corresponding Δ T through the Δ T test, and the self-heating effect index is inversely proportional to the width of the nano-strip or nano-sheet, so that the width of the nano-strip or nano-sheet can be obtained, and the width obtained is 8nm as shown in fig. 3.
The embodiment of the invention combines the self-heating effect of the nano-strip or nano-sheet, obtains the self-heating effect index by measuring the temperature change of the self-heating effect and combining the relation curve of the temperature change generated by the self-heating effect of the nano-strip or nano-sheet and the self-heating effect index, and obtains the width of the nano-strip or nano-sheet from the self-heating effect index, and the invention can be well applied to the measurement of the width of the fin body 102 of the fin transistor, compared with the technical scheme of testing the width of the nano-strip or nano-sheet by adopting a TEM (transmission electron microscope) photo in the prior art, the embodiment of the invention does not need to be sliced, so the embodiment of the invention is non-destructive measurement, and has high testing speed; the embodiment of the invention can realize the measurement of the widths of a plurality of planes, thereby being beneficial to the measurement of the widths of the nano strips or nano sheets of the three-dimensional structure on each surface; the embodiment of the invention has simple test, can measure the width of each nano strip or nano sheet on the whole semiconductor substrate 101 and form a measuring result distribution map (mapping), thereby being beneficial to monitoring the width of each nano strip or nano sheet on the whole semiconductor substrate 101; the embodiment of the invention has very high connection with the electrical yield of the product, and can well detect the yield of the product. Compared with the technical effects obtained by the existing TEM measuring method, the method provided by the embodiment of the invention can also refer to the table I:
watch 1
| Item | Method of an embodiment of the invention | Existing TEM measurement method |
| Test piece | Non-destructive | Destructive property |
| Measuring speed | Fast-acting toy | Slow |
| Measuring breadth | Each plane is equivalent | Only one plane |
| Measuring the number of samples | Supporting mapping | Less and complicated processes |
| Is connected with the electrical yield | Is very high | In general |
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (13)
1. A method for measuring the width of a nano strip or a nano sheet of a semiconductor device is characterized by comprising the following steps:
step one, obtaining a relation curve of temperature change generated by self-heating effect of the nano-strip or nano-sheet and self-heating effect index; the self-heating effect index is related to the height and width of the nano-strips or nano-sheets;
the self-heating effect index is proportional to the ratio of the height and width of the corresponding nano-strip or nano-sheet;
in the first step, a linear regression model with a linear relation between the temperature change and the self-heating effect index is obtained through the relation curve;
step two, providing a tested semiconductor device with nano strips or nano sheets;
step three, testing the temperature change of the nano-strip or nano-sheet of the tested semiconductor device by adopting a self-heating effect;
and step four, combining the temperature change of the nano-strip or nano-sheet of the tested semiconductor device with the relation curve to obtain the self-heating effect index of the nano-strip or nano-sheet of the tested semiconductor device, and obtaining the width of the nano-strip or nano-sheet of the tested semiconductor device through the obtained self-heating effect index of the nano-strip or nano-sheet of the tested semiconductor device.
2. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 1, characterized in that: the relationship curve is obtained through a plurality of learning cycles.
3. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 1, characterized in that: the semiconductor device is a fin transistor.
4. A method of measuring the width of a nano-strip or nano-sheet of a semiconductor device according to claim 3, characterized in that: the fin transistor includes a fin body composed of nano-strips or nano-sheets formed of a semiconductor material.
5. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 4, characterized in that: the grid structure covers the top surface and the side surfaces of the fin body with a part of length, and the surface of the fin body covered by the grid structure is used for forming a channel.
6. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 5, characterized in that: and the source region and the drain region are formed in the fin bodies on two sides of the grid structure.
7. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 5, characterized in that: the grid structure comprises a grid dielectric layer and a grid conductive material layer which are overlapped.
8. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 7, characterized in that: the gate dielectric layer is made of a gate oxide layer; or the material of the gate dielectric layer comprises a high dielectric constant material.
9. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 8, characterized in that: the grid conductive material layer is a polysilicon grid; or, the grid conductive material layer is a metal grid.
10. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 4, characterized in that: the semiconductor material of the fin body comprises silicon or silicon germanium.
11. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 4, characterized in that: the fin bodies on the same semiconductor substrate are arranged in parallel, and dielectric layers are isolated among the fin bodies.
12. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 6, characterized in that: an embedded epitaxial layer is formed in the source region or the drain region.
13. The method of measuring a width of a nano-strip or a nano-sheet of a semiconductor device according to claim 12, characterized in that: the material of the embedded epitaxial layer comprises silicon germanium.
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