CN110380462B - 充电器 - Google Patents

充电器 Download PDF

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Publication number
CN110380462B
CN110380462B CN201910175853.1A CN201910175853A CN110380462B CN 110380462 B CN110380462 B CN 110380462B CN 201910175853 A CN201910175853 A CN 201910175853A CN 110380462 B CN110380462 B CN 110380462B
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charger
transistor
voltage level
motherboard
thermally conductive
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CN110380462A (zh
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陈佑民
林天麒
林冠宇
陈廷玮
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本公开提供一种充电器，该充电器包含用于散热的一导热板、以及一晶体管。该晶体管包含一第一脉动电压位准的一漏极终端，以及一第二脉动电压位准的一源极终端。该第二脉动电压电平低于该第一脉动电压电平。其中，该源极终端连接至该导热板，该导热板位在一母板的一第一表面上，该母板包括一或多个导热层，该导热层包埋在该第一表面及与该第一表面对立的第二表面之间的该母板中，以及该一或多个导热层连接至该导热板。

Description

充电器
技术领域
本公开涉及电源充电装置。更特别地，本公开涉及为电子装置充电的充电器。
背景技术
诸如手机充电器之类的充电器已为人所知。由于有越来越多的应用程序，尤其是在手机上运作的多媒体应用程序，可使手机的电池电量非常快速地消耗。其他消费电子装置(例如MP3播放器、游戏机、相机和手机蓝牙耳机)也可能发生同样的情况。这些电子装置可能需要频繁充电。为了满足这种电力需求，开发了便携式电源供应器。
发明内容
本公开的一些实施例提供一种充电器。该充电器包含用于散热的一导热板、以及一晶体管。该晶体管包含一第一脉动电压电平的一漏极终端，以及一第二脉动电压电平的一源极终端。该第二脉动电压电平低于该第一脉动电压电平。其中，该源极终端连接至该导热板，该导热板位在一母板的一第一表面上，该母板包括一或多个导热层，该导热层包埋在该第一表面及与该第一表面对立的第二表面之间的该母板中，以及该一或多个导热层连接至该导热板。
在一实施例中，该源极终端附接至一载体，而该漏极终端是引线键合并且连接至该载体的多个第一接脚。
在另一实施例中，该载体包含附接至该导热板的多个第二接脚。
在另一实施例中，该导热板包含一铜包覆(copper clad)。
在另一实施例中，该一或多个导热层包含一或多个铜包覆。
在另一实施例中，该充电器另包含一控制器，经配置以控制该晶体管的导通时间。
在另一实施例中，控制器包含脉冲宽度调制(pulse-width modulation，PWM)控制器或恒定导通时间(constant on-time，COT)控制器其中之一。
在另一实施例中，该控制器与该晶体管共同封装于一半导体装置中。
在另一实施例中，该充电器另包含一变压器(transformer)，其中该晶体管的该漏极终端耦合至该变压器的初级绕组(primary winding)的同位端(dotted terminal)。
本公开的一些实施例提供还提供一种充电器。该充电器包含用于散热的一导热板、以及一半导体装置。该半导体装置包含一载体，其包含一晶粒垫(die pad)、第一接脚与第二接脚，并且包含附接至该载体的一晶体管。该晶体管包含一第一脉动电压电平的一漏极终端、以及一第二脉动电压电平的一源极终端，该第二脉动电压电平低于该第一脉动电压电平。该漏极终端是引线键合并且连接至该载体的这些第一接脚。该源极终端附接至该载体的该晶粒垫。这些第二接脚自该半导体装置暴露并且附接至该导热板。
附图说明
请注意，根据产业标准施行，各种特征并未依比例绘制。事实上，各种特征的尺寸可放大或缩小以利清楚说明。
图1为电路图，说明了本公开实施例之充电器。
图2A为示意图，说明了本公开实施例之图1所示的充电器之晶体管。
图2B为剖面图，说明了图2A沿着线AA所示之晶体管。
图3A为示意俯视图，说明了本公开实施例之包含图1所示该充电器之晶体管与控制器的半导体装置。
图3B为仰视图，说明了图3A所示之半导体装置。
图4为示意图，说明了本公开实施例之图1所示的充电器。
图5为剖面图，说明了本公开实施例之充电器。
附图标号说明
18 输出级
25 模塑料
30 半导体装置
35 模塑料
40 母板
42 散热片
50 充电气
60 母板
61 第一表面
62 第二表面
68 传导通路
71 铜包覆层
72 铜包覆层
120 晶粒垫
128 主动层
155 桥式整流器
S 源极
D 漏极
G 栅极
BW 接合线
BW1 第一接合线
BW2 第二接合线
LF 引线框架
LF1 第一载体
LF2 第二载体
GND 接地
CS 电流感测接脚
Source 源极
Controller 控制器
CTRL 控制信号
MOSFET 金属氧化物半导体场效晶体管
Drain 漏极
VCC 电源
Vac 交流电压
Vin 输入电压
C1 电容元件
C2 电容元件
C3 电容元件
D1 二级管
D2 二级管
R1 电阻元件
R2 电阻元件
Vout 输出电压
Load 负载。
具体实施方式
以下公开内容提供许多不同的实施例或实例，用于实施所提供标的之不同的特征。以下描述组件与配置的特定实例以简化本公开。当然，这些仅为例式而非用以限制本公开。例如，在说明内容中，第一特征形成于第二特征上方或形成于第二特征上可包含形成第一与第二特征直接接触的实施例，亦可包含形成其他特征于第一与第二特征之间的实施例，使得第一与第二特征可不直接接触。此外，本公开可于不同实例中重复元件符号与/或文字。此重复是为了简化与澄清之目的，且其本身并不决定所讨论的各种实施例和/或架构之间的关系。
根据本公开的一些实施例，图1为充电器10的电路图。充电器10可包含便携式充电器，用于对手机或其他便携式电子装置即时充电。
参阅图1，充电器10包含控制器11、晶体管12以及变压器14。控制器11经配置以产生控制信号CTRL，其控制晶体管12的导通时间与关闭时间。在一实施例中，控制器11包含脉冲宽度调制(pulse-width modulation，PWM)控制器或恒定导通时间(constant on-time，COT)控制器。该控制器11在电流感测接脚CS侦测流经晶体管12的源极接脚之电流强度，并且测定控制信号CTRL的工作周期(duty cycle)。通过改变提供至晶体管12的控制信号CTRL之工作周期，控制器11使变压器14产生用于电子装置，即图1中的负载，的所欲之输出电压Vout。在本实施例中，控制器11与晶体管12作为AC至DC转换器。
晶体管12可包含金属氧化物半导体场效晶体管(metal-oxide-semiconductorfield-effect transistor，MOSFET)。晶体管12的漏极终端连接至变压器14的初级绕组(primary winding)的同位端(dotted terminal)(表示极性)。晶体管12的源极终端(将详述于下)附接至导热板，例如散热用的散热片。晶体管12的栅极连接至控制器11，以接收控制信号CTRL。在操作中，漏极脉动电压可至少高达数百伏特(V)，而源极脉动电压可低至1V。漏极电压显著大于源极电压，并且可大至少两个量级(一百倍)。晶体管12作为在高压环境中操作的开关。
在本实施例中，充电器10亦包含输入级(input stage)15、滤波器16、缓冲器(snubber)17以及输出级(output stage)18。响应交流(ac)电压Vac(其可为主要供应电压)，输入级15经配置以提供输入电压Vin。在一些亚洲国家，Vac可为110V，在美国或欧洲可为220V至240V之范围。输入级15包含桥式整流器155，用于将Vac转变为直流(dc)电压。电压Vin在滤波器16过滤以移除AC波纹，并且在缓冲器(snubber)17处理以抑制电压瞬变。在例示实施例中，滤波器16包含电容元件C1连接于桥式整流器155与参考电压(例如，接地电压)之间。再者，缓冲器(snubber)17包含并联连接的电容元件C2与电阻元件R1，而后一起与变压器14的初级绕组的终端之间的二级管D串联连接。二级管D1的阳极连接至变压器14的初级绕组的同位端。
变压器14经配置以将相对大的输入电压Vin转变为相对小的输出电压Vout。Vout与Vin之间的关系可用以下方程式表示。
其中D代表控制信号CRTL的工作周期，以及N1与N2分别代表变压器14的初级绕组与次级绕组(secondary winding)的线圈数。
在一实施例中，Vin接近而Vout取决于应用而通常范围可自约5至12V，或是在一些情况下可达到接近20V。在输出级18提供输出电压Vout。在例示实施例中，输出级18包含电阻元件R2与电容元件C3，串联连接于二级管D2的阴极与变压器14的次级绕组的非同位端之间。电阻元件R2功能作为等效串联电阻(equivalent series resistor，ESR)。二级管D2的阳极连接至变压器14的次级绕组的同位端。
图2A为示意图，例示本公开实施例之图1所示的充电器10的晶体管12。
参阅图2A，晶体管12于其源极终端附接至支撑基板或载体，例如引线框架LF。引线框架LF包含晶粒垫120、第一接脚D与第二接脚S。晶体管12的栅极与漏极终端经由接合线BW而引线键合至引线框架LF的对应接脚G与D。晶体管的源极终端附接至引线框架LF的晶粒垫120。晶体管12与接合线BW一起封装在模塑料25(如虚线矩形框所示)中。该技艺中具有通常技术者可理解取决于施加到其上的电压电平，MOS晶体管的漏极和源极终端可互换。例如，在操作中，漏极电压通常高于n型MOS(NMOS)晶体管中的源极电压，并且低于p型MOS(PMOS)晶体管中的源极电压。
图2B为剖面图，例示图2A沿着线AA所示之晶体管。
参阅图2B，晶体管12包含栅极终端G、漏极终端D、源极终端S、以及漏极终端D与源极终端S之间的主动层128。主动层128可包含半导体层与互连结构以开启晶体管功能。源极终端S与漏极终端D位于主动层128的相对侧上。晶体管12的源极终端S附接至引线框架LF，其附接至母板(例如印刷电路板)上的散热片。因此，可说晶体管12具有底部源极结构，其中源极终端S比漏极终端D更接近散热片。以下讨论晶体管12的优点，其中源极S耦合至散热片。
在现有的充电器中，对比于本公开之充电器10中的顶部漏极底部源极晶体管结构，晶体管的漏极终端附接至载体，而后附接至印刷电路板上的散热片。如前所述，在ACDC应用中，漏极电压高于数百伏特。为了散热，需要相对大的铜包覆作为散热片以冷却晶体管。然而，在底部漏极晶体管结构中，漏极接脚脉动电压为电磁干扰的射极(emitter ofelectromagnetic influence，EMI)。虽然使用大的铜包覆以获得较佳的热性能，但是可能发生更强的辐射并且恶化EMI问题。因此，需要有效率的EMI滤波器，以减轻EMI辐射，这可能无可避免地使电路设计复杂化并增加充电器的成本。
不像现有的充电器，底部源极晶体管结构具有相对低的源极脉动电压，其可为如前所述之低至1V，显著低于漏极脉动电压。相较于基于底部漏极晶体管结构之现有方法，本公开之充电器10享有相对大的散热片，其增强了热性能，同时避免由于作为发射源的高脉动电压所引起的EMI问题。
可在美国专利第7,394,151号(‘151专利)(标题为「Semiconductor package withPlated Connection」)或是美国专利第8,008,716(‘716专利)(标题为「Inverted-TrenchGrounded-Source FET Structure with Trenched Source Body Short Electrode」)中找到底部源极结构，该两个专利皆授权给相同的受让人。特别地，底部源极结构公开于例如‘151专利中的图7A与7B及相关说明中，或是例如‘716专利中的图2与3及相关说明中。‘151与‘716专利的相关说明并入本案作为参考。
具有底部漏极结构之现有的晶体管(例如平面MOSFET与沟渠MOSFET)亦可应用于本实施例中而不需修饰。在一些实施例中，该晶体管经「翻转」以其源极终端面向引线框架，并且于源极终端附接至该引线框架，形成图2A与2B所示之底部源极结构。
图3A为俯视示意图，例示本公开实施例之半导体装置30，其包含图1所示的充电器10的控制器11与晶体管12。
参阅图3A，充电器10的控制器11与晶体管12共同封装于半导体装置30中。具体而言，附接至第一载体LF1的控制器11与附接至第二载体LF2的晶体管12封装在模塑料35中。为了控制晶体管12，控制器11经由第一接合线BW1传送控制信号CTRL至晶体管12的栅极。晶体管12的漏极终端经由第二接合线BW2而电连接至第二载体LF2的第一接脚(漏极接脚D)。考虑到相对大的漏极电压，第二载体LF2包含多个漏极接脚。
图3B为仰视图，说明图3A所示之半导体装置30。参阅图3B，第二载体LF2的一些第二接脚(源极接脚S)自半导体装置30暴露。这些暴露的源极接脚S与散热片一起作用以助于散热。
图4为示意图，说明本公开实施例之图1所示的充电器10。
参阅图4，第二载体LF2通过例如焊膏而附接至母板40上的散热片42。在本实施例中，晶体管12的源极终端所位在的晶粒垫120附接至散热片42。半导体装置30(特别是晶体管12)所产生的热可经由底部源极终端而向散热片42消散，并且亦可经由暴露的源极接脚S而向散热片42消散。因此，暴露的源极接脚S提供额外的散热路径。
图5为剖面图，说明本公开实施例之充电器50。
参阅图5，充电器50包含晶体管12与变压器14，其位于母板60的第一表面61上。在本实施例中，晶体管12经封装为单一半导体装置。或者，如图3A所示，晶体管12可与控制器11共同封装于半导体装置中。晶体管12的源极终端附接至载体，其附接至位在第一表面61上的铜包覆42。铜包覆42作为散热片。母板60包含至少一导热层，用于散热。在本实施例中，该至少一导热层包含包埋在母板60中的铜包覆71与72。在其他实施例中，铜包覆层的数目不限于两层。额外的铜包覆层71与72经由传导通路68而与铜包覆42耦合，使得从晶体管12经由第一表面61上的铜包覆42与铜包覆层71、72朝向母板60的第二表面62散热。
本领域的技术人员可理解可进行本文所公开的实施例之修饰。例如，可改变接脚的总数。本领域的技术人员可进行其他修饰，并且所有这些修饰皆落入申请专利范围所定义之本公开中。

Claims (18)

1.一种充电器，包括：
一导热板，用于散热；以及
一晶体管，包括：
一第一脉动电压电平的一漏极终端；以及
一第二脉动电压电平的一源极终端，该第二脉动电压电平低于该第一脉动电压电平；
其中该源极终端连接至该导热板；
其中该导热板位于一母板的一第一表面上；
其中该母板包括一个或多个导热层，该导热层包埋在该第一表面及与该第一表面对立的第二表面之间的该母板中；以及
其中该一个或多个导热层连接至该导热板；以及
其中所述导热板位于所述晶体管和所述母板之间。
2.根据权利要求1所述的充电器，其特征在于，该导热板包含一铜包覆。
3.根据权利要求1所述的充电器，其特征在于，该一个或多个导热层包含一个或多个铜包覆。
4.根据权利要求1所述的充电器，还包括：
一控制器，经配置以控制该晶体管的导通时间。
5.根据权利要求4所述的充电器，其特征在于，该控制器包含脉冲宽度调制控制器或恒定导通时间控制器其中之一。
6.根据权利要求5所述的充电器，其特征在于，该控制器与该晶体管共同封装在一半导体装置中。
7.根据权利要求1所述的充电器，其特征在于，该晶体管的该漏极终端耦合至变压器的初级绕组的同位端。
8.一种充电器，包括：
一导热板，用于散热；以及
一晶体管，包括：
一第一脉动电压电平的一漏极终端；以及
一第二脉动电压电平的一源极终端，该第二脉动电压电平低于该第一脉动电压电平；
其中该源极终端连接至该导热板；
其中该导热板位于一母板的一第一表面上；
其中该母板包括一个或多个导热层，该导热层包埋在该第一表面及与该第一表面对立的第二表面之间的该母板中；以及
其中该一个或多个导热层连接至该导热板；
该源极终端附接至一载体，以及其中该漏极终端的接合线连接至该载体的多个第一接脚。
9.根据权利要求8所述的充电器，其特征在于，该载体包含附接至该导热板的多个第二接脚。
10.一种充电器，包括：
一导热板，用于散热；以及
一半导体装置，其包括：
一载体，其包括一晶粒垫、多个第一接脚与多个第二接脚；以及
一晶体管，其附接至该载体，该晶体管包括：
一第一脉动电压电平的一漏极终端，该漏极终端的接合线连接至该载体的该多个第一接脚；以及
一第二脉动电压电平的一源极终端，该第二脉动电压电平低于该第一脉动电压电平，该源极终端附接至该载体的该晶粒垫，
其中该多个第二接脚连接至该晶粒垫；
其中该多个第二接脚暴露自该半导体装置；以及
其中该多个第二接脚附接至该导热板。
11.根据权利要求10所述的充电器，其特征在于，该载体的该晶粒垫附接至该导热板。
12.根据权利要求10所述的充电器，其特征在于，该导热板包含一铜包覆。
13.根据权利要求10所述的充电器，其特征在于，该导热板位在一母板上；
其中该母板包括：
一导热层，其包埋在该母板中；以及
其中该导热层连接至该导热板。
14.根据权利要求13所述的充电器，其特征在于，该导热层包含一铜包覆。
15.根据权利要求10所述的充电器，还包括：
一控制器，经配置以控制该晶体管的导通时间。
16.根据权利要求15所述的充电器，其特征在于，该控制器包含脉冲宽度调制控制器或恒定导通时间控制器其中之一。
17.根据权利要求16所述的充电器，其特征在于，该控制器与该晶体管共同封装在该半导体装置中。
18.根据权利要求10所述的充电器，还包括一变压器，其中该晶体管的该漏极终端耦合至该变压器的初级绕组的同位端。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043650A (en) * 1988-02-26 1991-08-27 Black & Decker Inc. Battery charger
US6387732B1 (en) * 1999-06-18 2002-05-14 Micron Technology, Inc. Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby
CN101572491A (zh) * 2008-04-28 2009-11-04 群康科技(深圳)有限公司 开关电源电路及其运作方法
CN107833885A (zh) * 2016-09-15 2018-03-23 威电科技有限公司 用于高压和高电流切换的功率器件

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6940724B2 (en) * 2003-04-24 2005-09-06 Power-One Limited DC-DC converter implemented in a land grid array package
US7302247B2 (en) * 2004-06-03 2007-11-27 Silicon Laboratories Inc. Spread spectrum isolator
US8018056B2 (en) * 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
ITMI20111213A1 (it) * 2011-06-30 2012-12-31 St Microelectronics Srl Dispositivo elettronico a semi-ponte con dissipatore di calore ausiliario comune

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043650A (en) * 1988-02-26 1991-08-27 Black & Decker Inc. Battery charger
US6387732B1 (en) * 1999-06-18 2002-05-14 Micron Technology, Inc. Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby
CN101572491A (zh) * 2008-04-28 2009-11-04 群康科技(深圳)有限公司 开关电源电路及其运作方法
CN107833885A (zh) * 2016-09-15 2018-03-23 威电科技有限公司 用于高压和高电流切换的功率器件

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