CN110379762B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN110379762B CN110379762B CN201910496013.5A CN201910496013A CN110379762B CN 110379762 B CN110379762 B CN 110379762B CN 201910496013 A CN201910496013 A CN 201910496013A CN 110379762 B CN110379762 B CN 110379762B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
Abstract
The invention provides a semiconductor structure and a manufacturing method thereof, comprising the following steps: providing a layer of stacked structure, forming a first concave structure in the layer of stacked structure, wherein the first concave structure extends downwards into the insulating medium interlayer but does not penetrate through the insulating medium interlayer; etching the insulating medium interlayer by taking the first hard mask layer as a mask to obtain a second sunken structure in the layer stacking structure, wherein the second sunken structure extends to the surface of the etching barrier layer, and the side wall of the second sunken structure is vertical; laterally trimming the second hard mask layer to enlarge the size of the top opening of the two hard mask layers; and etching the insulating medium interlayer by taking the second hard mask layer as a mask so as to enlarge the size of the opening of the first concave structure in the insulating medium interlayer. The method can adapt to dual damascene hole type, slit type or groove type structures with different film thicknesses, is beneficial to increasing the processing window of the chemical mechanical polishing of the insulating layer in the preorder process, and increases the processing window of the critical dimension of the bottom of the dual damascene hole.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuits, and relates to a semiconductor structure and a manufacturing method thereof.
Background
At present, a dual damascene hole type (or slit type, trench type) structure can be realized by only one development and etching process, that is, after a mask (mask) with a smaller Critical Dimension (CD) is developed, the mask is enlarged by a lateral trimming (Trim) method after a part of a hole is etched, and then the remaining hole is further etched.
Therefore, how to design a new semiconductor structure and a method for fabricating the same to improve the above-mentioned problems is an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a semiconductor structure and a method for fabricating the same, which are used to solve the problem in the prior art that the bottom critical dimension of the hole is easily affected by the film thickness and is not favorable for controlling the bottom critical dimension process window.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, comprising:
providing a layer of stacked structure, wherein the layer of stacked structure comprises an insulating medium interlayer, an etching barrier layer positioned below the insulating medium interlayer, a first hard mask layer positioned above the insulating medium interlayer and a second hard mask layer positioned above the first hard mask layer;
forming a first recess structure in the layer stack structure, wherein the first recess structure is open from the top surface of the second hard mask layer and extends downward into the insulating dielectric interlayer, but does not penetrate through the insulating dielectric interlayer;
etching the insulating medium interlayer by taking the first hard mask layer as a mask to obtain a second concave structure in the layer stacking structure, wherein the second concave structure is connected with the first concave structure and extends downwards to the surface of the etching barrier layer, and the side wall of the second concave structure is vertical;
laterally trimming the second hard mask layer to enlarge the size of a top opening of the second hard mask layer;
and etching the insulating medium interlayer by taking the second hard mask layer as a mask so as to enlarge the size of the opening of the first concave structure in the insulating medium interlayer.
Optionally, the second recess structure is formed by dry etching.
Optionally, the forming of the first recess structure comprises the steps of:
sequentially forming a bottom anti-reflection layer and a light resistance layer on the surface of the layer stacking structure from bottom to top;
patterning the light resistance layer to obtain an opening in the light resistance layer, wherein the opening exposes part of the surface of the bottom anti-reflection layer;
and etching the layer stacking structure by using the photoresist layer as a mask to obtain the first concave structure.
Optionally, the method further includes a step of etching to remove the etching barrier layer under the second recess structure.
Optionally, a contact portion is disposed in the layer stack structure, the contact portion is located below the etching barrier layer, and a part of a surface of the contact portion is exposed by the second recess structure.
Optionally, after the insulating medium interlayer is etched by using the second hard mask layer as a mask, an inclination angle of a lower side wall of the second recess structure is less than 20 °.
Optionally, before forming the second recess structure, at least one of dry etching and wet etching is used to form the first recess structure with an inclined sidewall.
Optionally, at least one of dry etching and wet etching is used to enlarge the opening size of the first recess structure
Optionally, the first hard mask layer includes at least one of a nitrogen-doped silicon carbide layer and a silicon nitride layer, and the second hard mask layer is made of polycarbonate.
Optionally, an insulating layer is disposed between the first hard mask layer and the second hard mask layer.
Optionally, the insulating dielectric interlayer is made of silicon dioxide, and the etching barrier layer is made of silicon nitride.
The present invention also provides a semiconductor structure comprising:
the layer stack structure comprises an insulating medium interlayer, an etching barrier layer positioned below the insulating medium interlayer, a hard mask layer positioned above the insulating medium interlayer and an insulating layer positioned above the hard mask layer;
the first concave structure is opened from the top surface of the insulating layer, extends downwards into the insulating medium interlayer and does not penetrate through the insulating medium interlayer;
the second concave structure is provided with an opening at the bottom surface of the first concave structure and extends downwards to penetrate through the etching barrier layer, the size of the opening at the upper part of the second concave structure is smaller than that of the opening at the lower part of the first concave structure, and the inclination angle of the side wall at the lower part of the second concave structure is smaller than 20 degrees.
Optionally, a contact portion is disposed in the layer stack structure, the contact portion is located below the etching barrier layer, and a part of a surface of the contact portion is exposed by the second recess structure.
Optionally, the sidewalls of the first recessed features are sloped.
Optionally, the hard mask layer includes at least one of a nitrogen-doped silicon carbide layer and a silicon nitride layer, the insulating layer includes silicon dioxide, the insulating dielectric interlayer includes silicon dioxide, and the etching blocking layer includes silicon nitride.
As described above, the semiconductor structure and the manufacturing method thereof of the present invention initially define a first recess structure with a smaller size, and etch and stop in the middle of the insulating dielectric interlayer, then cover the film thickness variation of the insulating dielectric interlayer by an etching gas (etch body) with a high selectivity ratio of the insulating dielectric interlayer/etch stop layer to form a second recess structure with vertical side walls, then make the opening of the second hard mask layer larger by using a lateral trimming etching method, and then further etch to enlarge the opening size of the first recess structure in the insulating dielectric interlayer, thereby obtaining a dual damascene via, slit or trench structure adapted to different film thicknesses. The method is beneficial to enlarging the processing window of the chemical mechanical polishing of the insulating layer in the previous process and enlarging the processing window of the critical dimension of the bottom of the dual damascene hole.
Drawings
FIG. 1 is a schematic diagram illustrating a first exemplary method of fabricating a semiconductor structure with a bottom anti-reflective layer and a patterned photoresist layer formed on a layer stack.
FIG. 2 is a schematic diagram illustrating a first exemplary method of fabricating a semiconductor structure with a recessed structure formed in the layer stack.
FIG. 3 is a schematic diagram illustrating a first exemplary method for fabricating a semiconductor structure with an enlarged hard mask layer opening at a top layer of the layer stack structure.
FIG. 4 is a schematic diagram illustrating the formation of a channel material layer for a first exemplary method of fabricating a semiconductor structure.
FIG. 5 is a diagram illustrating a bottom anti-reflective layer and a patterned photoresist layer formed on a layer stack structure according to a second exemplary method for fabricating a semiconductor structure.
FIG. 6 is a schematic diagram illustrating the formation of a recess structure in the layer stack structure for a second exemplary method of fabricating a semiconductor structure.
FIG. 7 is a diagram illustrating a second exemplary method for fabricating a semiconductor structure with an enlarged hard mask layer opening at a top layer of the layer stack.
FIG. 8 is a schematic diagram illustrating the formation of a channel material layer for a second exemplary method of fabricating a semiconductor structure.
FIG. 9 is a process flow diagram illustrating a method of fabricating a semiconductor structure according to the present invention.
FIG. 10 is a schematic diagram illustrating a layer stack structure provided in the method for fabricating a semiconductor structure according to the present invention.
FIG. 11 is a schematic view of a bottom anti-reflective coating and a patterned photoresist layer formed on a layer stack structure according to a method of fabricating a semiconductor structure of the present invention.
Fig. 12 is a schematic diagram illustrating the first recess structure obtained by etching the layer stack structure with the photoresist layer as a mask according to the method for fabricating a semiconductor structure of the present invention.
Fig. 13 is a schematic diagram showing the method for manufacturing a semiconductor structure according to the present invention, in which the first hard mask layer is used as a mask to etch the insulating dielectric interlayer, so as to obtain a second recess structure in the layer stack structure.
FIG. 14 is a schematic view of the method of fabricating a semiconductor structure of the present invention laterally trimming the second hard mask layer to enlarge the size of the top opening of the second hard mask layer.
Fig. 15 is a schematic view showing that the second hard mask layer is used as a mask to etch the insulating dielectric interlayer to enlarge the size of the opening of the first recess structure in the insulating dielectric interlayer in the manufacturing method of the semiconductor structure of the present invention.
Fig. 16 is an enlarged view of a portion of the structure shown in fig. 15.
FIG. 17 is a schematic structural diagram of a semiconductor structure according to the present invention.
Description of the element reference numerals
101-layer stacked structure
101a hard mask layer
102 bottom anti-reflection layer
103 photoresist layer
104 concave structure
201-layer stacked structure
201a hard mask layer
202 bottom anti-reflection layer
203 photoresist layer
204 recessed structure
301 layer stack structure
301a insulating dielectric interlayer
301b etch stop layer
301c first hard mask layer
301d second hard mask layer
301e insulating layer
301f contact part
302 bottom antireflective layer
303 photoresist layer
304 opening
305 first recess structure
306 second recess structure
401 layer stacked structure
401a insulating dielectric interlayer
401b etch stop layer
401c hard mask layer
401d insulating layer
401e contact part
402 first recess structure
403 second recess structure
angle of inclination of lower sidewall of alpha second recess structure
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 17. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The semiconductor structure of the invention is suitable for a dual damascene hole type (or slit type or trench type) structure. Referring to fig. 1 to 4, schematic structural views of steps of a method for fabricating a first exemplary semiconductor structure are shown.
As shown in fig. 1, a bottom anti-reflection layer 102 and a photoresist layer 103 are formed on a layer stack structure 101, and the photoresist layer 103 is patterned by a photolithography process. The layer stack structure 101 includes a hard mask layer 101a on a top layer.
As shown in fig. 2, the layer stack structure 101 is etched using the photoresist layer 103 as a mask, and a recess structure 104 is formed in the layer stack structure 101.
As shown in fig. 3, the opening of the hard mask layer 101a at the top layer of the layer stack structure 101 is enlarged by a lateral trimming process (Trim).
As shown in fig. 4, the layer stack structure 101 is continuously etched with the hard mask layer 101a as a mask, so that the size of the upper portion of the recess structure 104 is enlarged, and the recess structure 104 is T-shaped.
Referring to fig. 5 to 8, shown are schematic structural views of steps of a method for fabricating a second exemplary semiconductor structure, wherein the structure shown in fig. 5 to 8 is fabricated by substantially the same method as the structure shown in fig. 1 to 4, except that the structure shown in fig. 5 to 8 has a thicker layer stack structure.
As shown in fig. 5, a bottom anti-reflection layer 202 and a photoresist layer 203 are formed on the layer stack structure 201, and the photoresist layer 203 is patterned by a photolithography process. The layer stack structure 201 includes a hard mask layer 201a on a top layer.
As shown in fig. 6, the layer stack structure 201 is etched by using the photoresist layer 203 as a mask, and a recess structure 204 is formed in the layer stack structure 201.
As shown in fig. 7, the opening of the hard mask layer 201a at the top layer of the layer stack structure 201 is enlarged by a lateral trimming process (Trim).
As shown in fig. 8, the layer stack structure 201 is continuously etched with the hard mask layer 201a as a mask, so that the size of the upper portion of the recess structure 204 is enlarged, and the recess structure 204 is T-shaped.
It can be seen that in the first example described above, the layer stack is thinner and the critical dimension at the bottom of the recessed feature is larger, and in the second example described above, the layer stack is thicker and the critical dimension at the bottom of the recessed feature is correspondingly reduced. That is, the bottom critical dimension of the recess structure varies with the thickness of the layer stack structure, which is not conducive to the control of the bottom critical dimension process window.
Therefore, the present invention improves the above problems by a new design. The technical solution of the present invention will be described below by way of more specific examples.
Example one
In the present embodiment, a method for fabricating a semiconductor structure is provided, referring to fig. 9, which is a process flow diagram of the method, and includes the following steps:
referring to fig. 10, a layer stack structure 301 is provided, which includes an insulating dielectric interlayer 301a, an etch stop layer 301b disposed below the insulating dielectric interlayer 301a, a first hard mask layer 301c disposed above the insulating dielectric interlayer 301a, and a second hard mask layer 301d disposed above the first hard mask layer 301 c. In this embodiment, an insulating layer 301e is further disposed between the first hard mask layer 301c and the second hard mask layer 301d, and the insulating layer 301e is made of a material including, but not limited to, silicon dioxide. A contact 301f is also disposed in the layer stack structure 301, and the contact 301f is located below the etching barrier layer 301 b.
By way of example, the insulating dielectric interlayer 301a may be an Oxide (OX) layer including, but not limited to, silicon dioxide (SiO)2) The material of the etch stop layer 301b includes, but is not limited to, silicon nitride (SiN), the first hard mask layer 301c includes, but is not limited to, at least one of a nitrogen-doped silicon carbide (NDC) layer, an LDR layer, and a silicon nitride (SiN) layer, and the second hard mask layer 301d includes, but is not limited to, AC.
Referring to fig. 11 and 12, a first recess structure 305 is formed in the layer stack structure, wherein the first recess structure 305 is opened from the top surface of the second hard mask layer 301d and extends downward into the insulating interlayer dielectric layer 301a, but does not penetrate the insulating interlayer dielectric layer.
As an example, forming the first recess structure 305 includes the steps of:
as shown in fig. 11, a bottom anti-reflective layer 302 and a photoresist layer 303 are sequentially formed on the surface of the layer stack structure 301 from bottom to top. The material of the bottom anti-reflective layer 302 may be SiON. Then, the photoresist layer 303 is patterned by using a photolithography process to obtain an opening 304 in the photoresist layer 303, wherein the opening 304 exposes a portion of the surface of the bottom anti-reflection layer 302.
As shown in fig. 12, the layer stack structure 301 is etched using the photoresist layer 303 as a mask, so as to obtain the first recess structure 305.
As an example, the first recess structure 305 is formed using at least one of dry etching or wet etching. In this embodiment, the sidewall of the first recess structure 305 is inclined to form a tapered hole (taper Via).
Illustratively, when the first recess structure 305 is formed by dry etching, an etching gas containing octafluorocyclobutane (C) is used4F8) To facilitate inAnd defining an initial photoetching critical dimension processing window. In addition, the etching gas may further include hexafluorobutadiene (C)4F6) Carbon tetrafluoride (CF)4) Argon (Ar), oxygen (O)2) And the like.
As an example, the specific depth of the first recess structure 305 may be adjusted according to the thickness of the layer stack structure 301 or the specific thickness of the insulating dielectric interlayer 301a, so as to ensure that the critical dimension process window at the bottom of the subsequent recess structure is sufficiently large, and the protection scope of the present invention should not be limited herein.
Referring to fig. 13, the insulating dielectric interlayer 301a is etched using the first hard mask layer 301c as a mask to obtain a second recess structure 306 in the layer stack structure 301, the second recess structure 306 is continued to the first recess structure 305 and extends downward to the surface of the etch stop layer 301b, and the sidewall of the second recess structure 306 is vertical.
As an example, the second recess structure 306 is formed by dry etching using an etching gas having a high selectivity ratio to the insulating dielectric interlayer/etch stop layer. In this embodiment, the insulating dielectric interlayer 301a is made of silicon oxide, and the etching gas includes hexafluorobutadiene (C)4F6) Argon (Ar) and oxygen (O)2) Wherein the volume ratio range of each gas in the etching gas is C4F6：Ar：O2= 10-30: 100-500: 5-20, and the pressure of the etching gas is 15-80 mTorr. The etching time can be adjusted according to the thickness of the insulating dielectric interlayer 301 a.
Referring to fig. 14, the second hard mask layer 301d is etched using a lateral Trim process (Trim) to enlarge the top opening size of the second hard mask layer 301 d. The specific size of the top opening of the second hard mask layer 301d may be adjusted according to the specific width of the trench, the slit, etc. to be formed, and the scope of the present invention should not be limited herein.
Referring to fig. 15, the insulating dielectric interlayer 301a is etched using the second hard mask layer as a mask to enlarge the size of the opening of the first recess structure 305 in the insulating dielectric interlayer 301 a. During this etching process, the second recess structure 306 is also etched to a certain extent, and its vertical sidewalls may become inclined.
As an example, at least one of dry etching and wet etching is used to enlarge the opening size of the first recess structure 305.
referring to fig. 16, an enlarged view α of a portion α of the structure shown in fig. 15 is shown, wherein the angle α of inclination α of the lower sidewall α of the second recess structure 306 is less than 20 ° in the present embodiment.
As an example, the etch stop layer 301b under the second recess structure 306 is further etched away, exposing a portion of the surface of the contact 301 f.
Thus, a semiconductor structure is obtained. The manufacturing method of the semiconductor structure comprises the steps of firstly preliminarily defining a first concave structure with smaller size, stopping etching in the middle of an insulating medium interlayer, then covering film thickness change of the insulating medium interlayer through an etching body (etch body) with high selection ratio of the insulating medium interlayer/an etching stopping layer to form a second concave structure with vertical side walls, then enlarging an opening of a second hard mask layer by using a transverse trimming etching method, and then further etching to enlarge the opening size of the first concave structure in the insulating medium interlayer, thereby obtaining a dual damascene hole type, slit type or groove type structure suitable for different film thicknesses. The method is beneficial to enlarging the processing window of the chemical mechanical polishing of the insulating layer in the previous process and enlarging the processing window of the critical dimension of the bottom of the dual damascene hole.
Example two
The present invention further provides a semiconductor structure, referring to fig. 17, which is a schematic diagram of the semiconductor structure, including a layer stack structure 401, a first recess structure and a second recess structure, wherein the layer stack structure 401 includes an insulating dielectric interlayer 401a, an etching blocking layer 401b located below the insulating dielectric interlayer 401a, a hard mask layer 401c located above the insulating dielectric interlayer 401a, and an insulating layer 401d located above the hard mask layer 401c, the first recess structure 402 is opened from a top surface of the insulating layer 401d and extends downward into the insulating dielectric interlayer 401a but does not penetrate through the insulating dielectric interlayer 401a, the second recess structure is opened from a bottom surface of the first recess structure 402 and extends downward through the etching blocking layer 401b, an upper opening size of the second recess structure 403 is smaller than a lower opening size of the first recess structure 402, and the lower sidewall of the second recess structure 403 is inclined at an angle less than 20 °.
As an example, a contact portion 401e is further disposed in the layer stack structure 401, the contact portion 401e is located below the etch stop layer 401b, and the second recess structure 403 exposes a portion of the surface of the contact portion 401 e.
As an example, the sidewalls of the first recess structure are sloped.
As an example, the insulating dielectric interlayer 401a may be made of an Oxide (OX) layer including, but not limited to, silicon dioxide (SiO)2) The material of the etch stop layer 401b includes, but is not limited to, silicon nitride (SiN), the hard mask layer 401c includes, but is not limited to, at least one of a nitrogen-doped silicon carbide (NDC) layer, an LDR layer, and a silicon nitride (SiN) layer, and the material of the insulating layer 401d includes, but is not limited to, silicon dioxide.
The semiconductor structure can be prepared by adopting the method in the first embodiment, and has a larger processing window for chemically and mechanically polishing the insulating layer and a processing window for the critical dimension of the bottom of the dual damascene hole.
In summary, the semiconductor structure and the manufacturing method thereof of the present invention initially define a first recess structure with a smaller size, and etch the first recess structure and stop in the middle of the insulating dielectric interlayer, then cover the film thickness variation of the insulating dielectric interlayer by an etching body (etch body) with a high selection ratio of the insulating dielectric interlayer/etch stop layer to form a second recess structure with a vertical sidewall, then enlarge the opening of the second hard mask layer by an etching method of lateral trimming, and then further etch the second recess structure to enlarge the opening size of the first recess structure in the insulating dielectric interlayer, thereby obtaining a dual damascene via, slit or trench structure adapted to different film thicknesses. The method is beneficial to enlarging the processing window of the chemical mechanical polishing of the insulating layer in the previous process and enlarging the processing window of the critical dimension of the bottom of the dual damascene hole. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A method for manufacturing a semiconductor structure is characterized by comprising the following steps:
providing a layer of stacked structure, wherein the layer of stacked structure comprises an insulating medium interlayer, an etching barrier layer positioned below the insulating medium interlayer, a first hard mask layer positioned above the insulating medium interlayer and a second hard mask layer positioned above the first hard mask layer;
forming a first recess structure in the layer stack structure, wherein the first recess structure is open from the top surface of the second hard mask layer and extends downward into the insulating dielectric interlayer, but does not penetrate through the insulating dielectric interlayer;
etching the insulating medium interlayer by taking the first hard mask layer as a mask to obtain a second concave structure in the layer stacking structure, wherein the second concave structure is connected with the first concave structure and extends downwards to the surface of the etching barrier layer, and the side wall of the second concave structure is vertical;
laterally trimming the second hard mask layer to enlarge the size of a top opening of the second hard mask layer;
and etching the insulating medium interlayer by taking the second hard mask layer as a mask so as to enlarge the size of the opening of the first concave structure in the insulating medium interlayer.
2. The method of claim 1, wherein: and forming the second sunken structure by adopting dry etching.
3. The method of claim 1, wherein forming the first recess structure comprises:
sequentially forming a bottom anti-reflection layer and a light resistance layer on the surface of the layer stacking structure from bottom to top;
patterning the light resistance layer to obtain an opening in the light resistance layer, wherein the opening exposes part of the surface of the bottom anti-reflection layer;
and etching the layer stacking structure by using the photoresist layer as a mask to obtain the first concave structure.
4. The method of claim 1, wherein: the method further comprises the step of etching and removing the etching barrier layer below the second concave structure.
5. The method of claim 4, wherein: the layer stack structure is provided with a contact part, the contact part is positioned below the etching barrier layer, and the second concave structure exposes part of the surface of the contact part.
6. The method of claim 1, wherein: and after the insulating medium interlayer is etched by taking the second hard mask layer as a mask, the inclination angle of the lower side wall of the second concave structure is less than 20 degrees.
7. The method of claim 1, wherein: before the second concave structure is formed, at least one of dry etching and wet etching is adopted to form the first concave structure with an inclined side wall.
8. The method of claim 1, wherein: and enlarging the opening size of the first sunken structure by adopting at least one of dry etching and wet etching.
9. The method of claim 1, wherein: an insulating layer is arranged between the first hard mask layer and the second hard mask layer.
10. The method of claim 1, wherein: the insulating medium interlayer is made of silicon dioxide, and the etching barrier layer is made of silicon nitride.
11. A semiconductor structure, comprising:
the layer stack structure comprises an insulating medium interlayer, an etching barrier layer positioned below the insulating medium interlayer, a hard mask layer positioned above the insulating medium interlayer and an insulating layer positioned above the hard mask layer;
the first concave structure is opened from the top surface of the insulating layer, extends downwards into the insulating medium interlayer and does not penetrate through the insulating medium interlayer;
the second concave structure is opened from the bottom surface of the first concave structure and extends downwards to penetrate through the etching barrier layer, the size of an upper opening of the second concave structure is smaller than that of a lower opening of the first concave structure, and the inclination angle of a lower side wall of the second concave structure is smaller than 20 degrees;
the semiconductor structure is manufactured by the method for manufacturing the semiconductor structure according to any one of claims 1 to 10.
12. The semiconductor structure of claim 11, wherein: the layer stack structure is provided with a contact part, the contact part is positioned below the etching barrier layer, and the second concave structure exposes part of the surface of the contact part.
13. The semiconductor structure of claim 11, wherein: the side wall of the first concave structure is inclined.
14. The semiconductor structure of claim 11, wherein: the hard mask layer comprises at least one of a nitrogen-doped silicon carbide layer and a silicon nitride layer, the insulating layer comprises silicon dioxide, the insulating medium interlayer comprises silicon dioxide, and the etching barrier layer comprises silicon nitride.
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| KR20060067393A (en) * | 2004-12-15 | 2006-06-20 | 동부일렉트로닉스 주식회사 | Method for fabricating dual damascene pattern |
| CN106257643A (en) * | 2015-06-17 | 2016-12-28 | 格罗方德半导体公司 | Unique bilayer etch of protection conductive structure stops and using method |
| CN109863587A (en) * | 2019-01-25 | 2019-06-07 | 长江存储科技有限责任公司 | The method of pore structure is formed in the semiconductor device |
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| US9728501B2 (en) * | 2015-12-21 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trenches |
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| KR20060067393A (en) * | 2004-12-15 | 2006-06-20 | 동부일렉트로닉스 주식회사 | Method for fabricating dual damascene pattern |
| CN106257643A (en) * | 2015-06-17 | 2016-12-28 | 格罗方德半导体公司 | Unique bilayer etch of protection conductive structure stops and using method |
| CN109863587A (en) * | 2019-01-25 | 2019-06-07 | 长江存储科技有限责任公司 | The method of pore structure is formed in the semiconductor device |
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