KR100505602B1 - Method for removing anti-reflection film and multi-layer in cluding that used in manufacturing semi-conductor devices - Google Patents
Method for removing anti-reflection film and multi-layer in cluding that used in manufacturing semi-conductor devices Download PDFInfo
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- KR100505602B1 KR100505602B1 KR1019980016992A KR19980016992A KR100505602B1 KR 100505602 B1 KR100505602 B1 KR 100505602B1 KR 1019980016992 A KR1019980016992 A KR 1019980016992A KR 19980016992 A KR19980016992 A KR 19980016992A KR 100505602 B1 KR100505602 B1 KR 100505602B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 장치 제조공정중 식각방법에 관한 것으로, 특히 무기 반사방지막 및 이를 포함하는 다층막의 전면식각방법을 제시한다. 본 발명은 무기 반사방지막을 사용한 사진식각공정에 의해 형성된 컨택 홀 및 무기 반사방지막에 플러그로 사용되는 다결정 실리콘을 증착하고, 사불화탄소(CF4) 및 산소(O2) 가스 조성물을 사용하여 다결정 실리콘층과 반사방지막을 동시에 전면식각하는 것을 특징으로 한다. 이때, 사불화탄소에 대한 산소의 유량비는 20~80%로 함이 바람직하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method during a semiconductor device manufacturing process, and more particularly to an inorganic antireflection film and a front surface etching method of a multilayer film including the same. The present invention is to deposit a polycrystalline silicon used as a plug in the contact hole and the inorganic antireflection film formed by a photolithography process using an inorganic antireflection film, and using a carbon tetrafluoride (CF4) and oxygen (O2) gas composition and a polycrystalline silicon layer It is characterized in that the anti-reflection film at the same time the entire surface. At this time, the flow rate ratio of oxygen to carbon tetrafluoride is preferably 20 to 80%.
본 발명에 의하면, 후속공정에 나쁜 영향을 미치는 무기 반사방지막을 쉽게 제거할 수 있고, 그 하층 절연막까지 동시에 식각할 수 있어 전체 절연막의 두께 감소 및 평탄화에 효과가 있다.According to the present invention, the inorganic antireflection film which adversely affects the subsequent process can be easily removed, and the lower layer insulating film can be etched at the same time, which is effective in reducing the thickness and planarization of the entire insulating film.
Description
본 발명은 반도체 장치의 제조공정중 식각방법에 관한 것으로, 특히 무기 반사방지막 및 이를 포함한 다층막에 대한 전면 식각을 하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method during a manufacturing process of a semiconductor device, and more particularly, to an entire surface etching method for an inorganic antireflection film and a multilayer film including the same.
근래, 반도체 소자의 집적도가 증가함에 따라 선폭(Critical Dimension, CD)이 감소하고 그 균일도(uniformity) 조절이 반도체 소자에 중요한 역할을 하게 되었다. 따라서 거의 모든 공정에서 사진식각작업을 보다 미세하고 균일도가 좋게 하기 위하여 반사방지막(Anti Reflection Film)을 사용하고 있다. 이러한 반사방지막중 무기 반사방지막으로는 주로 SiON을 사용하고 있는데, 이 SiON이 제거되지 않고 남아있을 경우에는 후속공정에서 좋지 않은 영향을 미치게 된다. 즉, 산화막 사이에 SiON막이 남아 있으면 그 남은 두께만큼 층간절연막의 두께가 증가(scale-up)하고, 후속공정에서 SiON막 아래층까지 컨택 홀을 형성할 때 슬로프(slope) 감소에 의해 선폭이 감소하거나 심한 경우 식각이 멈춰(etch stopping) 컨택 홀이 완전히 개구되지 않을 수도 있다.In recent years, as the degree of integration of semiconductor devices increases, the critical dimension (CD) decreases and the uniformity control plays an important role in semiconductor devices. Therefore, anti-reflection film is used to make photo etching work finer and more uniform in almost all processes. Among the anti-reflection films, SiON is mainly used as the inorganic anti-reflection film. If the SiON is left without being removed, it will adversely affect the subsequent process. That is, if the SiON film is left between the oxide films, the thickness of the interlayer insulating film is scaled up by the remaining thickness, and the line width is decreased due to the slope reduction when forming the contact hole to the lower layer of the SiON film in the subsequent process. In extreme cases, the etch stopping may not fully open the contact hole.
따라서, 반사방지막으로 사용되는 SiON막은 반드시 제거되어 하는데, 이 SiON막을 사용하여 컨택 식각 등을 한 후 바로 SiON막을 제거하게 되면, SiON막의 하층 층간절연막의 식각선택비가 커서 과도식각과정에서 컨택 홀의 개구부 선폭(top CD)이 증가하는 문제가 발생하고, 후속공정인 비트라인 식각공정에서 제거하려 하면 비트라인 스택(stack) 증가로 식각에 어려움이 있다.Therefore, the SiON film used as the anti-reflection film must be removed. When the SiON film is removed immediately after contact etching using the SiON film, the etching selectivity of the lower interlayer insulating film of the SiON film is large, and thus the line width of the opening of the contact hole in the transient etching process is large. There is a problem that (top CD) increases, and when it is removed in a subsequent bit line etching process, there is a difficulty in etching due to an increase in the bit line stack.
또한, 반사방지막을 사용하여 사진식각공정을 수행하는 경우에는, 그 하층막인 층간절연막, 반사방지막, 컨택 홀을 채우는 플러그막 등 실리콘 산화물 계열의 다층막이 형성되는데, 이 다층막은 결과적으로 절연막의 두께 증가를 초래한다. 따라서, 반사방지막을 포함한 실리콘 산화물 계열의 다층막은 전면적으로 감소시킬(scale-down) 필요가 있고, 이는 다층막으로 이루어진 반도체 장치의 평탄화(planization)에도 도움이 된다. In addition, in the case of performing a photolithography process using an antireflection film, a silicon oxide-based multilayer film such as an interlayer insulating film, an antireflection film, and a plug film filling contact holes is formed, which is a result of the thickness of the insulating film. Causes an increase. Therefore, the silicon oxide-based multilayer film including the antireflection film needs to be scaled down entirely, which also helps in planarization of the semiconductor device made of the multilayer film.
그러나, 종래는 이 다층막에 대하여, 각각의 층을 적층하고 원하는 패턴으로 식각한 다음 CMP(Chemical Mechanical Polishing) 공정 등을 통해 제거, 평탄화를 수행하고 다시 다음 층을 적층, 식각, 평탄화하는 과정을 반복하였다. 따라서, 공정수가 증가하고 생산성이 저하되는 문제가 있었다.However, conventionally, the multilayer film is laminated with each layer and etched in a desired pattern, and then removed, planarized through a chemical mechanical polishing (CMP) process, etc., and then the process of laminating, etching, and planarizing the next layer is repeated. It was. Therefore, there is a problem that the number of processes increases and productivity decreases.
본 발명의 목적은 사진식각공정에서 사용된 무기 반사방지막을 효율적으로 제거하기 위한 식각방법을 제공함에 있다.An object of the present invention is to provide an etching method for efficiently removing the inorganic anti-reflection film used in the photolithography process.
본 발명의 다른 목적은 반사방지막을 포함한 실리콘 산화물 계열의 다층막을 동시에 전면식각하는 방법을 제공함에 있다.Another object of the present invention is to provide a method for simultaneously etching the entire surface of a silicon oxide-based multilayer film including an antireflection film.
상기의 목적을 달성하기 위한 본 발명의 무기 반사방지막을 제거하는 방법은, 반사방지막을 사용하여 사진식각공정을 수행한 후 형성된 컨택 홀과 반사방지막 위에 다결정 실리콘 플러그를 증착하는 단계 및 사불화탄소(CF4)와 산소(O2) 가스의 조성물을 사용하여 다결정 실리콘층과 무기 반사방지막을 동시에 전면식각하는 단계를 포함하는 것을 특징으로 한다. 이때, 사불화탄소와 산소 가스의 조성물은 다결정 실리콘층과 무기 반사방지막의 식각선택비를 최대한 같게 하기 위한 것으로, 사불화탄소에 대한 산소의 유량비는 20~80%로 하는 것이 바람직하다.Method for removing the inorganic anti-reflection film of the present invention for achieving the above object, the step of depositing a polycrystalline silicon plug on the contact hole and the anti-reflection film formed after performing a photolithography process using the anti-reflection film and carbon tetrafluoride (CF4 And simultaneously etching the polycrystalline silicon layer and the inorganic anti-reflection film by using the composition of oxygen and oxygen (O 2) gas. In this case, the composition of carbon tetrafluoride and oxygen gas is to make the etching selectivity of the polycrystalline silicon layer and the inorganic antireflection film as the same as possible, and the flow rate ratio of oxygen to carbon tetrafluoride is preferably 20 to 80%.
상기의 다른 목적을 달성하기 위한 본 발명의 다층막 전면식각방법은 실리콘 산화물 계열의 절연막 위에 다결정 실리콘층이 적층된 다층막을 전면식각하는 방법으로서, 사불화탄소 및 산소 가스의 조성물을 사용하여 다결정 실리콘층과 그 하층막인 절연막을 동시에 연속적으로 식각하는 것을 특징으로 한다. 이때, 사불화탄소에 대한 산소의 유량비는 상기와 같이 20~80%로 하는 것이 바람직하다.The multi-layered film front etching method of the present invention for achieving the above another object is a method of front-etched a multi-layered film in which a polycrystalline silicon layer is laminated on a silicon oxide-based insulating film, using a composition of carbon tetrafluoride and oxygen gas and The insulating film as the underlayer film is simultaneously etched continuously. At this time, the flow rate ratio of oxygen to carbon tetrafluoride is preferably 20 to 80% as described above.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도1은 반사방지막을 사용하여 사진식각공정을 수행한 후의 상태를 도시한 단면도이다. 도1의 상태는 반도체 기판(100) 상에 소정의 공정을 통하여 트랜지스터 영역을 형성하고 제1절연막(200), 제2절연막(300)을 적층하고, 그 위에 반사방지막(400)을 적층한 다음, 반사방지막(400)의 패턴에 따라 소정 개소에 컨택 홀을 형성한 상태이다. 여기서, 제1절연막(200), 제2절연막(300)은 BPSG(Borophospho Silicate Glass)나 PE-TEOS(Plasma enhanced Tetra-ethyl-orthosilicate) 등의 실리콘 산화물 계열의 절연막이 될 수 있다. 그리고 반사방지막(400)은 무기 반사방지막으로서 주로 SiON으로 이루어진다.1 is a cross-sectional view showing a state after performing a photolithography process using an anti-reflection film. In the state of FIG. 1, a transistor region is formed on a semiconductor substrate 100 through a predetermined process, a first insulating film 200 and a second insulating film 300 are stacked, and an antireflection film 400 is stacked thereon. The contact hole is formed in a predetermined position according to the pattern of the antireflection film 400. The first insulating layer 200 and the second insulating layer 300 may be silicon oxide-based insulating layers such as borophospho silicate glass (BPSG) or plasma enhanced tetra-ethyl-orthosilicate (PE-TEOS). The anti-reflection film 400 is made of SiON mainly as an inorganic anti-reflection film.
이어서, 반사방지막을 곧바로 제거하지 않고, 사진식각공정에 의해 형성된 컨택 홀 및 반사방지막(400) 위에 플러그로 채워질 다결정 실리콘(500)을 증착하여 도2와 같이 만든다.Subsequently, the polycrystalline silicon 500 to be filled with the plug is deposited on the contact hole and the antireflection film 400 formed by the photolithography process without removing the antireflection film immediately, as shown in FIG. 2.
다음, 사불화탄소 및 산소 가스의 조성물을 식각가스로 하여 전면식각을 수행한다. 여기서, 도3에 도시된 바와 같이 다결정 실리콘층(500)과 반사방지막(400)층을 완전히 제거하기 위해서는, 다결정 실리콘층과 SiON으로 이루어진 반사방지막의 식각선택비를 최대한 낮게, 이상적으로는 1:1까지 낮게 하는 것이 중요하다. 이 식각선택비를 낮추는 것은 식각가스로 사용하는 사불화탄소와 산소 가스의 유량비에 의해 조절이 된다. 본 실시예에서는 사불화탄소에 대한 산소의 유량비를 20~80%로 하였다. 예를 들어, 사불화탄소의 유량을 30sccm으로 하면 산소의 유량은 6~24sccm으로 한다. 이렇게 하면 다결정 실리콘과 SiON의 식각선택비를 1:1.3 이하로 낮추는 것이 가능하다. 기타 제반 공정조건은 식각장비나 각 막의 두께에 따라 통상적으로 조절될 수 있다.Next, full etching is performed using the composition of carbon tetrafluoride and oxygen gas as an etching gas. Here, in order to completely remove the polycrystalline silicon layer 500 and the antireflection film 400 as shown in FIG. 3, the etching selectivity of the antireflection film made of the polycrystalline silicon layer and SiON is as low as possible, ideally 1: It is important to lower it to 1. The lowering of the etching selectivity is controlled by the flow rate ratio of carbon tetrafluoride and oxygen gas used as the etching gas. In this example, the flow rate ratio of oxygen to carbon tetrafluoride was 20 to 80%. For example, when the flow rate of carbon tetrafluoride is 30 sccm, the flow rate of oxygen is 6-24 sccm. In this way, it is possible to lower the etching selectivity of polycrystalline silicon and SiON to 1: 1.3 or less. Other process conditions can usually be adjusted according to the etching equipment or the thickness of the cornea.
이렇게 식각선택비가 낮게 되면 도3에 도시된 바와 같이 다결정 실리콘층과 반사방지막이 전부 제거되고, 플러그로서 채워진 다결정 실리콘(510)과 반사방지막의 하층이었던 제2절연막(310) 이하의 층만 남게된다. When the etch selectivity is lowered as shown in FIG. 3, the polycrystalline silicon layer and the antireflection film are all removed, and only the layer below the second insulating layer 310 which is the lower layer of the polycrystalline silicon 510 and the antireflection film filled as a plug remains.
또한, 사불화탄소에 대한 산소의 유량비를 상기와 같이 20~80%로 하면 전술한 바와 같이 다결정 실리콘층과 SiON막의 식각선택비가 1:1.3 이하로 될 뿐만 아니라, 다결정 실리콘층과 PE-TEOS로 이루어진 제2절연막(300)의 식각선택비도 1:1.3 정도로 된다. 즉, 다결정 실리콘층(500):반사방지막(400):제2절연막(300)의 식각선택비가 1:1.3:1.3까지 달성된다. 이는, 식각시간을 더 길게 하면 다결정 실리콘층과 반사방지막 뿐만 아니라 그 하층막인 제2절연막까지 쉽게 식각할 수 있음을 의미한다. 따라서, 전체 절연막의 두께 감소와 평탄화를 위해 같은 조건에서 식각시간을 더 늘려 제2절연막까지 약간 식각을 하는 것이 좋다.In addition, when the flow rate ratio of oxygen to carbon tetrafluoride is 20 to 80% as described above, the etching selectivity ratio of the polycrystalline silicon layer and the SiON film is not less than 1: 1.3 as described above, and the polycrystalline silicon layer and PE-TEOS The etching selectivity of the second insulating layer 300 is also about 1: 1.3. That is, the etching selectivity of the polycrystalline silicon layer 500: antireflection film 400: second insulating film 300 is achieved to 1: 1.3: 1.3. This means that the longer the etching time, the easier it is to etch not only the polycrystalline silicon layer and the anti-reflection film but also the second insulating film, which is the lower layer film. Therefore, in order to reduce the thickness and planarization of the entire insulating film, the etching time may be further extended under the same conditions to slightly etch the second insulating film.
한편, 사불화탄소와 산소 가스 조성물은 다결정 실리콘과 SiON의 식각선택비를 낮추는 데에는 효과가 있지만, 다결정 실리콘 자체의 식각속도는 느린 편이다. 따라서, 특히 다결정 실리콘층이 두꺼운 경우는, 염소(Cl2) 및 브롬화수소(HBr)와 같은 다결정 실리콘 식각용 가스를 사용하여 반사방지막이 드러나기 직전까지 식각을 행하고, 그 후에 사불화탄소와 산소 가스 조성물을 사용하여 다결정 실리콘과 반사방지막을 식각하는 것이 효과적일 수 있다. On the other hand, carbon tetrafluoride and oxygen gas composition is effective in lowering the etching selectivity of the polycrystalline silicon and SiON, but the etching rate of the polycrystalline silicon itself is slow. Therefore, especially when the polycrystalline silicon layer is thick, etching is performed until the antireflective film is exposed using a polycrystalline silicon etching gas such as chlorine (Cl 2) and hydrogen bromide (HBr), and then the carbon tetrafluoride and oxygen gas compositions are It may be effective to etch polycrystalline silicon and antireflective coatings.
무기 반사방지막을 제거하기 위한 본 발명은 실리콘 산화물 계열의 절연막 위에 다결정 실리콘층이 적층된 구조의 다층막을 전면식각하는 데에도 그대로 적용될 수 있다. 즉, SiON이나 PE-TEOS 등의 절연막 위에 다결정 실리콘이 적층된 다층막에 대하여 사불화탄소와 산소 가스 조성물을 상기와 같은 유량비로 사용하면 다결정 실리콘층과 그 하부의 절연막을 전부 제거할 수 있다.The present invention for removing the inorganic antireflection film can also be applied to the entire surface etching of a multilayer film having a structure in which a polycrystalline silicon layer is stacked on a silicon oxide insulating film. That is, when the carbon tetrafluoride and the oxygen gas composition are used in the above-described flow rate ratio with respect to the multilayer film in which polycrystalline silicon is laminated on an insulating film such as SiON or PE-TEOS, all of the polycrystalline silicon layer and the insulating film beneath it can be removed.
또한, 상기와 같은 전면식각은 RIE(Reactive Ion Etching), MERIE(Magnetron Enhanced RIE), ICP(Inductively Coupled Plasma), ECR(Electron Cyclotron Resonance), Helicon, SWP(Surface Wave Plasma) 등의 각종 플라즈마 방식에 의해서도 수행될 수 있다. In addition, the front surface etching may be applied to various plasma methods such as Reactive Ion Etching (RIE), Magnetictron Enhanced RIE (MERIE), Inductively Coupled Plasma (ICP), Electron Cyclotron Resonance (ECR), Helicon, and Surface Wave Plasma (SWP). It can also be performed by.
상술한 바와 같이 본 발명에 따른 식각방법에 의하면, 후속공정에 나쁜 영향을 미치는 무기 반사방지막을 쉽게 제거할 수 있을 뿐만 아니라, 한 번의 공정으로 반사방지막의 하층막인 절연막까지 동시에 식각할 수 있어, 전체 절연막의 두께 감소 및 평탄화에도 효과가 있다.As described above, according to the etching method of the present invention, not only the inorganic antireflection film which adversely affects the subsequent process can be easily removed, but also the insulating film which is the lower layer of the antireflection film can be simultaneously etched in one step. It is also effective in reducing the thickness and planarization of the entire insulating film.
도 1 내지 도 3은 본 발명에 따른 무기 반사방지막 및 이를 포함한 다층막 전면 식각공정을 도시한 도면이다.1 to 3 is a view showing an inorganic anti-reflection film and a multi-layer front surface etching process including the same according to the present invention.
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