CN110365330B - Half digital phase-locked loop based on FIR filter - Google Patents
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The invention discloses a half digital phase-locked loop based on FIR filter, the half digital phase-locked loop includes: an FIR filter, an integration path and a digital/voltage controlled oscillator, the FIR filter comprising: the digital/voltage controlled oscillator comprises a counter, a delay chain, a plurality of frequency dividers, a plurality of phase detectors and a low-pass filter, wherein the frequency dividers are connected with the output end of the digital/voltage controlled oscillator, each frequency divider is connected with one phase detector, the phase detectors are connected with the low-pass filter, and an integration path is respectively connected with one of the frequency dividers in the frequency dividers and the input end of the digital/voltage controlled oscillator. The half-digital phase-locked loop provided by the invention is based on the spurious suppression technology of the FIR filter, effectively realizes the spurious suppression of the half-digital phase-locked loop based on the finite-modulus frequency divider, has the advantage of insensitivity to process, voltage, temperature variation and analog mismatch, and has the advantage of hardware cost and overhead cost.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a half-digital phase-locked loop based on an FIR filter.
Background
In a fractional phase-locked loop based on a finite modulus divider, the finite modulus divider can generate different division ratios for a period of time, so that the phase-locked loop can realize division ratios with the average value being a fraction. The reference frequency of the fractional phase-locked loop is not limited by frequency precision and can be selected randomly, so that the contribution of a reference source and a frequency divider to noise in the phase-locked loop can be reduced by improving the reference frequency and reducing the frequency dividing ratio. The higher reference frequency also allows for the use of greater bandwidth in the loop setup process to increase the speed of lock by dynamically changing the loop bandwidth.
Because the integer frequency dividing ratio sequence generated when the finite modulus frequency divider generates the fractional frequency dividing ratio is not a true random sequence, the fractional spurious problem is also introduced in the fractional phase-locked loop. As a signal generating circuit, a first consideration in the design of a fractional phase-locked loop is the spectral purity of the output signal, including phase noise and spurs, whose performance specifications are required to be given in the form of clock jitter and noise templates in the clock generator and frequency synthesizer, respectively.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a half digital phase-locked loop based on an FIR filter, effectively realizes the spurious suppression of the half digital phase-locked loop based on a finite-modulus frequency divider, has the advantage of insensitivity to process, voltage, temperature change and analog mismatch, and has the advantage of hardware cost and cost.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a half digital phase locked loop based on an FIR filter, the half digital phase locked loop comprising: an FIR filter, an integration path, and a digital/voltage controlled oscillator, the FIR filter comprising: the digital/voltage controlled oscillator comprises a counter, a delay chain, a plurality of frequency dividers, a plurality of phase detectors and a low-pass filter, wherein the frequency dividers are connected with the output end of the digital/voltage controlled oscillator, each frequency divider is connected with one phase detector, the phase detectors are connected with the low-pass filter, and the integration paths are respectively connected with one of the frequency dividers and the input end of the digital/voltage controlled oscillator;
the control signal generated by the counter generates a plurality of delay units after being delayed by the delay chain, each delay unit controls one frequency divider to generate a path of clock signal, the plurality of frequency dividers input the generated clock signal into corresponding phase detectors, the phase detectors acquire first phase error signals between an externally input reference clock signal and a received clock signal, the first phase error signals acquired by the plurality of phase detectors are input into the low-pass filter to be synthesized into voltage control signals of an analog domain, and the output frequency of the digital/voltage control oscillator is controlled according to the voltage control signals, wherein the delay chain is a register chain which comprises a plurality of stages of registers;
the integration path obtains a second phase error signal between the externally input reference clock signal and the clock signal input by the corresponding frequency divider, generates a digital control signal according to the second phase error signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
Further, in the half-digital phase-locked loop based on the FIR filter, the plurality of phase detectors are a plurality of analog phase detectors, and the low-pass filter is a passive low-pass filter; each analog phase discriminator is provided with a reference clock signal input end and a clock signal input end, the reference clock signal input end is used for receiving an externally input reference clock signal, and the clock signal input end is used for receiving a clock signal input by a corresponding frequency divider;
the analog phase discriminator acquires a first phase error signal between the reference clock signal and a clock signal input by a corresponding frequency divider, inputs a plurality of first phase error signals acquired by the plurality of analog phase discriminators into the passive low-pass filter to synthesize a voltage control signal in an analog domain, and controls the output frequency of the digital/voltage control oscillator according to the voltage control signal.
Further, a half digital phase locked loop based on FIR filter as described above, the integration path comprising: the digital/voltage control oscillator comprises a binary phase detector and a finite-state machine, wherein the binary phase detector is connected with one of the frequency dividers, the output end of the binary phase detector is connected with the input end of the finite-state machine, and the output end of the finite-state machine is connected with the input end of the digital/voltage control oscillator;
the binary phase discriminator is provided with a reference clock signal input end and a clock signal input end, the reference clock signal input end is used for receiving the reference clock signal input by the outside, and the clock signal input end is used for receiving the clock signal input by the corresponding frequency divider;
and the binary phase discriminator acquires a second phase error signal between the reference clock signal and a clock signal input by a corresponding frequency divider, controls the finite-state machine to work according to the second phase error signal, generates a digital control signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
Further, a half digital phase locked loop based on an FIR filter as described above, said register chain comprising three stages of registers, each stage delayed by a single clock cycle;
the control signal generated by the counter generates four delay units after being delayed by the register chain, each delay unit controls one frequency divider to generate a path of clock signal, the four frequency dividers input the generated clock signal into corresponding analog phase detectors, the analog phase detectors acquire first phase error signals between an externally input reference clock signal and a received clock signal, the four first phase error signals acquired by the four analog phase detectors are input into the passive low-pass filter to be synthesized into a voltage control signal of an analog domain, and the output frequency of the digital/voltage control oscillator is controlled according to the voltage control signal;
and the binary phase discriminator acquires a second phase error signal between the reference clock signal and a clock signal input by a corresponding frequency divider, controls the finite-state machine to work according to the second phase error signal, generates a digital control signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
Further, a half digital phase locked loop based on FIR filter as described above, said digital/voltage controlled oscillator comprising: the ring oscillator comprises a PMOS array, a varactor and an automatic frequency control module, wherein the PMOS array, the varactor and the automatic frequency control module are connected with the ring oscillator;
the PMOS array is used for controlling the output frequency of the ring oscillator according to a first digital control signal input by the integral path;
the varactor is used for controlling the output frequency of the ring oscillator according to a voltage control signal input by the FIR filter;
the automatic frequency control module is used for comparing a frequency difference between an externally input reference oscillation frequency signal and an output frequency signal of the ring oscillator, generating a second digital control signal according to the frequency difference, and controlling the PMOS array to carry out initial frequency calibration on the digital/voltage control oscillator according to the second digital control signal.
Furthermore, as described above, the ring oscillator is formed by cascading multiple stages of differential inverters into a ring, each differential inverter in the ring oscillator is provided with a positive input end, a negative input end, a positive output end and a negative output end, in a multi-stage differential inverter loop, the positive output end and the negative output end of a previous stage of differential inverter are respectively connected with the positive input end and the negative input end of a next stage of differential inverter, and the positive output end and the negative output end of a last stage of differential inverter are respectively connected with the negative input end and the positive input end of a first stage of differential inverter.
Further, according to the half digital phase-locked loop based on the FIR filter, the PMOS array is formed by connecting a plurality of PMOS tubes in parallel, and the source electrode of the PMOS array is connected with a power supply; the drain electrode of the PMOS array is connected with the ring oscillator and used for generating bias voltage to supply power to the ring oscillator; the grid of the PMOS array is used for receiving a first digital control signal input by the integral path and a second digital control signal input by the automatic frequency control module, controlling the conduction and the cut-off of a corresponding PMOS tube according to the first digital control signal after a half-digital phase-locked loop works, controlling the bias voltage of the drain electrode of the PMOS array, controlling the output frequency of the ring oscillator, controlling the conduction and the cut-off of the corresponding PMOS tube according to the second digital control signal before the half-digital phase-locked loop works, and performing initial frequency calibration on the digital/voltage control oscillator.
Further, as described above, the varactor is bridged between the positive output terminal and the negative output terminal of each differential inverter in the ring oscillator, and is configured to receive a voltage control signal input by the FIR filter, change a capacitance value of the varactor according to the voltage control signal, that is, change a load capacitance at the output terminal of the ring oscillator, and control an output frequency of the ring oscillator.
Further, as to the half digital phase-locked loop based on the FIR filter, the automatic frequency control module is provided with a reference oscillation frequency signal input end and a ring oscillator output frequency signal input end, the reference oscillation frequency signal input end is used for receiving an externally input reference oscillation frequency signal, and the ring oscillator output frequency signal input end is connected to the output end of the ring oscillator and is used for receiving an output frequency signal of the ring oscillator;
the automatic frequency control module is used for comparing the frequency difference between the reference oscillation frequency signal and the output frequency signal of the ring oscillator, generating a second digital control signal according to the frequency difference, controlling the conduction and the cut of a corresponding PMOS tube in the PMOS array according to the second digital control signal before the semi-digital phase-locked loop works, changing the output frequency of the ring oscillator, and carrying out initial frequency calibration on the digital/voltage control oscillator.
Further, as mentioned above, the automatic frequency control module is formed by a frequency-locked loop.
The invention has the beneficial effects that: the half-digital phase-locked loop provided by the invention is based on the spurious suppression technology of the FIR filter, effectively realizes the spurious suppression of the half-digital phase-locked loop based on the finite-modulus frequency divider, has the advantage of insensitivity to process, voltage, temperature variation and analog mismatch, and has the advantage of hardware cost and overhead cost.
Drawings
Fig. 1 is a schematic structural diagram of an FIR filter provided in an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a half-digital phase-locked loop based on an FIR filter according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a digital/voltage controlled oscillator provided in an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
As shown in fig. 1-2, a half digital phase-locked loop based on an FIR filter, the half digital phase-locked loop comprising: an FIR filter, an integration path and a digital/voltage controlled oscillator, the FIR filter comprising: the digital/voltage controlled oscillator comprises a counter, a delay chain, a plurality of frequency dividers, a plurality of phase detectors and a low-pass filter, wherein the frequency dividers are connected with the output end of the digital/voltage controlled oscillator, each frequency divider is connected with one phase detector, the phase detectors are connected with the low-pass filter, and an integration path is respectively connected with one of the frequency dividers and the input end of the digital/voltage controlled oscillator;
the control signal generated by the counter generates a plurality of delay units after being delayed by a delay chain, each delay unit controls one frequency divider to generate one path of clock signal, the plurality of frequency dividers input the generated clock signal into corresponding phase detectors, the phase detectors acquire first phase error signals between an externally input reference clock signal and a received clock signal, the plurality of first phase error signals acquired by the plurality of phase detectors are input into a low-pass filter to be synthesized into a voltage control signal of an analog domain, and the output frequency of a digital/voltage control oscillator is controlled according to the voltage control signal, wherein the delay chain is a register chain which comprises a plurality of stages of registers;
specifically, the plurality of phase detectors are a plurality of analog phase detectors, and the low-pass filter is a passive low-pass filter; each analog phase discriminator is provided with a reference clock signal input end and a clock signal input end, the reference clock signal input end is used for receiving an externally input reference clock signal, and the clock signal input end is used for receiving a clock signal input by a corresponding frequency divider;
the analog phase discriminator acquires a first phase error signal between a reference clock signal and a clock signal input by a corresponding frequency divider, inputs a plurality of first phase error signals acquired by the analog phase discriminators into the passive low-pass filter to synthesize a voltage control signal of an analog domain, and controls the output frequency of the digital/voltage control oscillator according to the voltage control signal.
The integration path obtains a second phase error signal between an externally input reference clock signal and a clock signal input by a corresponding frequency divider, generates a digital control signal according to the second phase error signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
Specifically, the integration path includes: the system comprises a binary phase discriminator and a finite-state machine, wherein the binary phase discriminator is connected with one of a plurality of frequency dividers, the output end of the binary phase discriminator is connected with the input end of the finite-state machine, and the output end of the finite-state machine is connected with the input end of a digital/voltage control oscillator;
the binary phase discriminator is provided with a reference clock signal input end and a clock signal input end, the reference clock signal input end is used for receiving an externally input reference clock signal, and the clock signal input end is used for receiving a clock signal input by a corresponding frequency divider;
the binary phase discriminator obtains a second phase error signal between the reference clock signal and the clock signal input by the corresponding frequency divider, controls the finite-state machine to work according to the second phase error signal, generates a digital control signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
The register chain comprises three stages of registers, each stage delaying a single clock cycle;
the control signal generated by the counter generates four delay units after being delayed by a register chain, each delay unit controls one frequency divider to generate a path of clock signal, the four frequency dividers input the generated clock signal into corresponding analog phase detectors, the analog phase detectors acquire first phase error signals between an externally input reference clock signal and a received clock signal, the four first phase error signals acquired by the four analog phase detectors are input into a passive low-pass filter to be synthesized into a voltage control signal of an analog domain, and the output frequency of the digital/voltage control oscillator is controlled according to the voltage control signal;
the binary phase discriminator obtains a second phase error signal between the reference clock signal and the clock signal input by the corresponding frequency divider, controls the finite-state machine to work according to the second phase error signal, generates a digital control signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
The invention provides a half digital phase-locked loop, which is based on a spurious suppression technology of an FIR (finite impulse response) filter, wherein in the half digital phase-locked loop based on a finite-mode frequency divider, an instantaneous phase error caused by different frequency dividing ratios exists between two signals at the input end of a phase discriminator, and a low-pass filter converts the phase error into an error voltage of an analog domain. In order to realize the FIR filtering function of fractional spur, the invention adopts a form of connecting a plurality of phase detectors in parallel. The control signal of the finite-mode frequency divider realizes the time delay of one or a plurality of clock periods through a register chain, a plurality of taps are selected from the control signal to respectively control the corresponding multi-mode frequency dividers, and the instantaneous phase errors generated during the switching of different frequency dividing ratios pass through the branch phase detectors and are combined into analog domain error voltage in a multi-input low-pass filter.
The specific structure of the above-described digital/voltage controlled oscillator is as follows.
The digital/voltage controlled oscillator includes: the ring oscillator comprises a PMOS array, a varactor and an automatic frequency control module, wherein the PMOS array, the varactor and the automatic frequency control module are connected with the ring oscillator;
the ring oscillator is formed by cascading multistage differential phase inverters into a ring, each differential phase inverter in the ring oscillator is provided with a positive input end, a negative input end, a positive output end and a negative output end, in a multistage differential phase inverter loop, the positive output end and the negative output end of a previous stage of differential phase inverter are respectively connected with the positive input end and the negative input end of a next stage of differential phase inverter, and the positive output end and the negative output end of a last stage of differential phase inverter are respectively connected with the negative input end and the positive input end of a first stage of differential phase inverter.
The PMOS array is used for controlling the output frequency of the ring oscillator according to a first digital control signal input by the integral path;
the PMOS array is formed by connecting a plurality of PMOS tubes in parallel, and a source electrode of the PMOS array is connected with a power supply; the drain electrode of the PMOS array is connected with the ring oscillator and used for generating bias voltage to supply power to the ring oscillator; the grid of the PMOS array is used for receiving a first digital control signal input by an integral path and a second digital control signal input by an automatic frequency control module, controlling the conduction and the cut-off of a corresponding PMOS tube according to the first digital control signal after the half-digital phase-locked loop works, controlling the bias voltage of the drain electrode of the PMOS array, controlling the output frequency of the ring oscillator, controlling the conduction and the cut-off of the corresponding PMOS tube according to the second digital control signal before the half-digital phase-locked loop works, and performing initial frequency calibration on the digital/voltage control oscillator.
The varactor is used for controlling the output frequency of the ring oscillator according to a voltage control signal input by the FIR filter;
the varactor is bridged between the positive output end and the negative output end of each differential phase inverter in the ring oscillator, and is used for receiving a voltage control signal input by the FIR filter, changing the capacitance value of the varactor according to the voltage control signal, namely changing the load capacitance of the output end of the ring oscillator, and controlling the output frequency of the ring oscillator.
The automatic frequency control module is used for comparing the frequency difference between an externally input reference oscillation frequency signal and an output frequency signal of the ring oscillator, generating a second digital control signal according to the frequency difference, and controlling the PMOS array to carry out initial frequency calibration on the digital/voltage control oscillator according to the second digital control signal.
The automatic frequency control module is provided with a reference oscillation frequency signal input end and a ring oscillator output frequency signal input end, the reference oscillation frequency signal input end is used for receiving an externally input reference oscillation frequency signal, and the ring oscillator output frequency signal input end is connected with the output end of the ring oscillator and used for receiving the output frequency signal of the ring oscillator;
the automatic frequency control module is used for comparing the frequency difference between the reference oscillation frequency signal and the output frequency signal of the ring oscillator, generating a second digital control signal according to the frequency difference, controlling the conduction and the cut of a corresponding PMOS tube in the PMOS array according to the second digital control signal after the half-digital phase-locked loop works, changing the output frequency of the ring oscillator and carrying out initial frequency calibration on the digital/voltage control oscillator.
The automatic frequency control module is composed of a frequency locking ring.
Example one
As shown in fig. 1, the basic circuit structure for FIR noise filtering in a half-digital phase-locked loop is realized. In order to realize the FIR filtering function, the invention adopts a form that a plurality of phase detectors are connected in parallel. The counter does not directly control the frequency dividing ratio of the frequency divider in the traditional structure, but realizes the time delay of one or a plurality of clock periods through a register chain, a control signal generated by the counter extracts a plurality of taps from the register chain after the time delay of the register chain to respectively control the corresponding frequency dividers, and the generated instantaneous phase error is synthesized into the error voltage of an analog domain in a multi-input low-pass filter after passing through each branch phase discriminator. In this embodiment, a three-stage register is included in the register chain to implement four stages of delay, each stage of delay being a single clock cycle, a parallel 4-branch phase detector and a 4-input low-pass filter.
As shown in fig. 2, the circuit structure of a half digital phase-locked loop based on FIR filter spur suppression technology is applied. Different delay units control different frequency dividers respectively by passing the output of the counter through a series of register chains, wherein the input clock of the frequency dividers is the output clock signal (output frequency) of the digital/voltage controlled oscillator. In the present embodiment, a 4-tap delay requires 4 dividers (multi-modulus dividers) correspondingly. And 4 paths of clock signals output by the frequency divider are respectively compared with the phase of a reference clock, and phase errors are superposed after passing through a 4-input low-pass filter, so that a 4-order FIR hybrid filter structure is realized. Because the digital integration branch is only used for frequency tracking, the digital phase detector only needs to detect the frequency division output of a reference clock and a certain branch.
It should be noted that the frequency divider described herein is a finite modulus frequency divider, i.e., a multi-modulus frequency divider. The passive low pass filter described herein is a multiple input low pass filter. The reference frequency in the figures is the reference clock signal described herein.
The half-digital phase-locked loop provided by the invention is based on the spurious suppression technology of the FIR filter, effectively realizes spurious suppression of the half-digital phase-locked loop based on the finite-modulus frequency divider, has the advantage of insensitivity to process, voltage, temperature (PVT) variation and analog mismatch, and has the advantage of hardware cost and overhead cost.
Example two
As shown in fig. 3, the digital/voltage controlled oscillator includes: the device comprises a ring oscillator, a PMOS array, a varactor and an automatic frequency control module.
The ring oscillator is formed by cascading any multiple stages of differential inverters into a ring, the smaller the number of stages of the differential inverters is, the higher the oscillation frequency of the ring oscillator is, and in the embodiment, the ring oscillator is formed by three stages of differential inverters, so that the oscillator can achieve a higher output frequency under the application of a low power supply voltage. The differential inverter is provided with a positive and negative input single end IP, IN and a positive and negative output end OP, ON, and the attention is paid that IN a loop of the differential inverter, the positive output end and the negative output end of one stage of differential inverter are respectively connected to the negative input end and the positive input end of the next set of differential inverter, otherwise the ring oscillator cannot oscillate.
The PMOS array is formed by connecting a plurality of PMOS transistors in parallel, the number of the PMOS transistors can be set according to the requirement, and in this embodiment, 5 PMOS transistors are selected to form the array. The source of the PMOS array is connected to the power supply VDD of the low supply voltage digital/voltage oscillator, the drain of the PMOS array generates a bias voltage to power the ring oscillator, and the gates of the PMOS array are connected to different digital control signals CW [0], CW [1], CW [2], respectively. The PMOS tubes in the PMOS array all work in a linear region, and each PMOS tube can be equivalent to a resistor. The digital signal of each PMOS tube gate controls the conduction and the cut-off of the PMOS tube, and represents the connection or the disconnection of the equivalent resistor in the array, thereby controlling the voltage of the PMOS array drain electrode, further controlling the output frequency of the ring oscillator and realizing the digital signal control of the oscillator output frequency.
The varactor is bridged between the positive and negative output terminals of a differential inverter in the ring oscillator. The external input voltage signal Vc controls the capacitance value of the varactor to change, which is equivalent to the change of the load capacitance of the output end of the ring oscillator, so that the output frequency of the ring oscillator is controlled, and the voltage signal control of the oscillator is realized.
The automatic frequency control module is provided with a reference oscillation frequency signal F0 input end and a feedback ring oscillator output frequency signal input end, compares the frequency difference of the two signals, outputs a digital control signal AFC [1] 0 to control part of PMOS tubes in the PMOS array, changes the output frequency of the ring oscillator and realizes the initial frequency calibration of the low power supply voltage digital/analog control oscillator. The automatic frequency control module may be implemented by a frequency locked loop. The oscillator realizes three-input control of a digital signal, a voltage signal and an initial reference frequency signal, does not need bias current during working, and can realize automatic calibration of the initial oscillation frequency of the oscillator.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (10)
1. A half digital phase locked loop based on an FIR filter, the half digital phase locked loop comprising: an FIR filter, an integration path, and a digital/voltage controlled oscillator, the FIR filter comprising: the digital/voltage controlled oscillator comprises a counter, a delay chain, a plurality of frequency dividers, a plurality of phase detectors and a low-pass filter, wherein the frequency dividers are connected with the output end of the digital/voltage controlled oscillator, each frequency divider is connected with one phase detector, the phase detectors are connected with the low-pass filter, and the integration paths are respectively connected with one of the frequency dividers and the input end of the digital/voltage controlled oscillator;
the control signal generated by the counter generates a plurality of delay units after being delayed by the delay chain, each delay unit controls one frequency divider to generate a path of clock signal, the plurality of frequency dividers input the generated clock signal into corresponding phase detectors, the phase detectors acquire first phase error signals between an externally input reference clock signal and a received clock signal, the first phase error signals acquired by the plurality of phase detectors are input into the low-pass filter to be synthesized into voltage control signals of an analog domain, and the output frequency of the digital/voltage control oscillator is controlled according to the voltage control signals, wherein the delay chain is a register chain which comprises a plurality of stages of registers;
the integration path obtains a second phase error signal between the externally input reference clock signal and the clock signal input by the corresponding frequency divider, generates a digital control signal according to the second phase error signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
2. The FIR filter-based half-digital phase-locked loop of claim 1, wherein the plurality of phase detectors are a plurality of analog phase detectors, and the low-pass filter is a passive low-pass filter; each analog phase discriminator is provided with a reference clock signal input end and a clock signal input end, the reference clock signal input end is used for receiving an externally input reference clock signal, and the clock signal input end is used for receiving a clock signal input by a corresponding frequency divider;
the analog phase discriminator acquires a first phase error signal between the reference clock signal and a clock signal input by a corresponding frequency divider, inputs a plurality of first phase error signals acquired by the plurality of analog phase discriminators into the passive low-pass filter to synthesize a voltage control signal in an analog domain, and controls the output frequency of the digital/voltage control oscillator according to the voltage control signal.
3. A FIR filter based half digital phase locked loop as claimed in claim 2, wherein said integration path comprises: the digital/voltage control oscillator comprises a binary phase detector and a finite-state machine, wherein the binary phase detector is connected with one of the frequency dividers, the output end of the binary phase detector is connected with the input end of the finite-state machine, and the output end of the finite-state machine is connected with the input end of the digital/voltage control oscillator;
the binary phase discriminator is provided with a reference clock signal input end and a clock signal input end, the reference clock signal input end is used for receiving the reference clock signal input by the outside, and the clock signal input end is used for receiving the clock signal input by the corresponding frequency divider;
the binary phase detector obtains a second phase error signal between the reference clock signal and the clock signal input by the corresponding frequency divider, controls the finite-state machine to work according to the second phase error signal, generates a digital control signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
4. A FIR filter based half digital phase locked loop as claimed in claim 3, wherein said register chain comprises three stages of registers, each stage delayed by a single clock cycle;
the control signal generated by the counter generates four delay units after being delayed by the register chain, each delay unit controls one frequency divider to generate a path of clock signal, the four frequency dividers input the generated clock signal into corresponding analog phase detectors, the analog phase detectors acquire first phase error signals between an externally input reference clock signal and a received clock signal, the four first phase error signals acquired by the four analog phase detectors are input into the passive low-pass filter to be synthesized into a voltage control signal of an analog domain, and the output frequency of the digital/voltage control oscillator is controlled according to the voltage control signal;
and the binary phase discriminator acquires a second phase error signal between the reference clock signal and a clock signal input by a corresponding frequency divider, controls the finite-state machine to work according to the second phase error signal, generates a digital control signal, and controls the output frequency of the digital/voltage control oscillator according to the digital control signal.
5. A half digital phase locked loop based on FIR filter according to any of claims 1 to 4 characterized in that the digital/voltage controlled oscillator comprises: the ring oscillator comprises a PMOS array, a varactor and an automatic frequency control module, wherein the PMOS array, the varactor and the automatic frequency control module are connected with the ring oscillator;
the PMOS array is used for controlling the output frequency of the ring oscillator according to a first digital control signal input by the integral path;
the varactor is used for controlling the output frequency of the ring oscillator according to a voltage control signal input by the FIR filter;
the automatic frequency control module is used for comparing a frequency difference between an externally input reference oscillation frequency signal and an output frequency signal of the ring oscillator, generating a second digital control signal according to the frequency difference, and controlling the PMOS array to carry out initial frequency calibration on the digital/voltage control oscillator according to the second digital control signal.
6. The half-digital phase-locked loop based on FIR filter of claim 5, characterized in that the ring oscillator is composed of multiple stages of differential inverters cascaded into a ring, each differential inverter in the ring oscillator has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, in the loop of multiple stages of differential inverters, the positive output terminal and the negative output terminal of the previous stage of differential inverter are connected with the positive input terminal and the negative input terminal of the next stage of differential inverter respectively, and the positive output terminal and the negative output terminal of the last stage of differential inverter are connected with the negative input terminal and the positive input terminal of the first stage of differential inverter respectively.
7. The half-digital phase-locked loop based on the FIR filter of claim 6, wherein the PMOS array is composed of a plurality of PMOS tubes connected in parallel, and the source of the PMOS array is connected with a power supply; the drain electrode of the PMOS array is connected with the ring oscillator and used for generating bias voltage to supply power to the ring oscillator; the grid of the PMOS array is used for receiving a first digital control signal input by the integral path and a second digital control signal input by the automatic frequency control module, controlling the conduction and the cut-off of a corresponding PMOS tube according to the first digital control signal after a half-digital phase-locked loop works, controlling the bias voltage of the drain electrode of the PMOS array, controlling the output frequency of the ring oscillator, controlling the conduction and the cut-off of the corresponding PMOS tube according to the second digital control signal before the half-digital phase-locked loop works, and performing initial frequency calibration on the digital/voltage control oscillator.
8. The half digital phase-locked loop based on the FIR filter of claim 7, wherein the varactor is connected across the positive output terminal and the negative output terminal of each differential inverter in the ring oscillator, and is used for receiving a voltage control signal input by the FIR filter, and changing its capacitance value according to the voltage control signal, that is, changing the magnitude of the load capacitance at the output terminal of the ring oscillator, and controlling the output frequency of the ring oscillator.
9. The half-digital phase-locked loop based on the FIR filter of claim 8, wherein the automatic frequency control module is provided with a reference oscillation frequency signal input terminal and a ring oscillator output frequency signal input terminal, the reference oscillation frequency signal input terminal is used for receiving an externally input reference oscillation frequency signal, the ring oscillator output frequency signal input terminal is connected with the output terminal of the ring oscillator and is used for receiving the output frequency signal of the ring oscillator;
the automatic frequency control module is used for comparing the frequency difference between the reference oscillation frequency signal and the output frequency signal of the ring oscillator, generating a second digital control signal according to the frequency difference, controlling the conduction and the cut-off of a corresponding PMOS tube in the PMOS array according to the second digital control signal before the semi-digital phase-locked loop works, changing the output frequency of the ring oscillator, and carrying out initial frequency calibration on the digital/voltage control oscillator.
10. A half digital phase locked loop based on FIR filter according to claim 5 characterized in that the automatic frequency control block is constituted by a frequency locked loop.
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