CN110351961A - The patch processing method of FPC plate - Google Patents
The patch processing method of FPC plate Download PDFInfo
- Publication number
- CN110351961A CN110351961A CN201810305364.9A CN201810305364A CN110351961A CN 110351961 A CN110351961 A CN 110351961A CN 201810305364 A CN201810305364 A CN 201810305364A CN 110351961 A CN110351961 A CN 110351961A
- Authority
- CN
- China
- Prior art keywords
- plate
- patch
- fpc
- processing method
- cog region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention discloses a kind of patch processing methods of FPC plate, include the following steps: S1: detecting the half of FPC plate at plate before patch, half is equipped with Chip Area and cog region at plate；S2: will be partly the removal of underproof cog region at testing result on plate；S3: will partly be installed on patch jig at plate, and patch jig is equipped with the identification mouth for exposing the patch mouth of Chip Area and for exposing cog region, and what identification mouth exposed after the removal of underproof cog region is patch jig itself；S4: patch jig selects qualified half into plate and underproof half into plate according to the difference at identification mouth, and only the half of agproximation plate at the Chip Area of plate carries out patch.The patch processing method of FPC plate according to an embodiment of the present invention, by cutting away half before patch into the cog region on plate, convenient and efficient to make patch jig identify plate and bad plate, practical, accuracy is high.
Description
Technical field
The present invention relates to electronic equipment manufacturing manufacture field more particularly to a kind of patch processing methods of FPC plate.
Background technique
SMT sections, in patch electronics element, mainly mount after element coordinate on mark point location FPC.Because plate factory supplies
When having bad plate when answering quotient's supplied materials, therefore judging whether plank needs to mount, chip mounter will be determined by identification bad mark, when
When machine recognition comes out threshold value greater than a certain standard, machine judgement has been plate, normal to mount；, whereas if identifying threshold value
When lower than this standard value, machine judgement is bad plate, will not be mounted.But these recognition methods in the prior art, some presence
The problem of accuracy deficiency is some to there are problems that influencing subsequent technique.
Summary of the invention
The present invention is directed at least solve one of the technical problems existing in the prior art.For this purpose, the present invention proposes a kind of FPC
The patch processing method of plate can efficiently and accurately identify underproof partly at plate in patch.
A kind of patch processing method of FPC plate according to the present invention, includes the following steps:
S1: detecting the half of FPC plate at plate before patch, and described half is equipped with Chip Area and cog region at plate；
S2: described half is removed at testing result on plate for the underproof cog region；
S3: described half is installed on patch jig at plate, the patch jig is equipped with for exposing the Chip Area
Patch mouth and identification mouth for exposing the cog region, the identification mouth after removal of the underproof cog region
What is exposed is described patch jig itself；
S4: the patch jig selects qualified described half into plate and underproof according to the difference at the identification mouth
Described half at plate, and only described the half of agproximation plate carries out patch at the Chip Area of plate.
The patch processing method of FPC plate according to an embodiment of the present invention, by cutting away half before patch into the identification on plate
Area, convenient and efficient to make patch jig identify plate and bad plate, practical, accuracy is high.
In some embodiments, described half at plate is multiple and connection forms whole join plate, the whole spelling on the same plate
Connecting plate patch after processing is completed, then carries cutting and is cut into multiple mutually independent FPC plates.
In some embodiments, in step s 4, the patch jig is according to the brightness and/or coloration at the identification mouth
Difference selects qualified described half into plate and underproof described half into plate.
Specifically, in step s 4, by making the Chip Area of the patch outlet for lantern slide exposing to the patch mouth polishing
It is obvious with the luminance difference of the patch jig itself.
In some embodiments, described half is a part of the Chip Area at the cog region on plate.
Specifically, the cog region is bad mark cog region.
In some embodiments, the patch jig includes: bottom plate and cover board, and the cover plate lid is on the bottom plate, institute
It states half to be folded between the bottom plate and the cover board at plate, the patch mouth and the identification mouth are located on the cover board.
Specifically, the gray value of the side surface towards the cover board of the bottom plate is consistent, the separate institute of the cover board
The gray value for stating a side surface of bottom plate is consistent, and the side surface towards the cover board of the bottom plate is remote with the cover board
The gray value of a side surface from the bottom plate is different.
More specifically, described half is located at the whole of rectangle at plate and joins on plate, the bottom plate and the cover board are rectangle.
Further, in step s 4, before carrying out patch at the Chip Area of plate to described half, first to the patch
Area's print solder paste.
Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 is the partial process view of the patch of FPC plate according to an embodiment of the present invention；
Fig. 2 is the integrated artistic flow chart of FPC plate patch；
Fig. 3 is according to an embodiment of the present invention partly at the structural schematic diagram of plate；
Fig. 4 is shown in Fig. 3 half to remove area schematic at plate；
Fig. 5 is the whole schematic diagram for joining plate according to an embodiment of the present invention；
Fig. 6 is the schematic diagram of patch jig according to an embodiment of the present invention.
Appended drawing reference:
It is whole join plate 100,
Half at plate 10, Chip Area 11, cog region 12, Wiring area 1313,
Patch jig 20, cover board 21, bottom plate 22, patch mouth 211, identification mouth 212.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not considered as limiting the invention.
The patch processing method of FPC plate according to an embodiment of the present invention is described below with reference to Fig. 1-Fig. 6.Here, it is processed into
FPC plate can be used for mobile phone, can be used for other electronic products such as computer.
The patch processing method of a kind of FPC plate according to the present invention, as shown in Figure 1, including the following steps:
S1: detecting the half of FPC plate at plate 10 before patch, and half is equipped with Chip Area 11 and cog region at plate 10
12；
S2: will be partly that underproof cog region 12 removes at testing result on plate 10；
S3: it will be partly installed on patch jig 20 at plate 10, patch jig 20 is equipped with the patch for exposing Chip Area 11
Piece mouth 211 and identification mouth 212 for exposing cog region 12, identification mouth 212 exposes after the removal of underproof cog region 12
Be patch jig 20 itself；
S4: patch jig 20 according to the difference at identification mouth 212 select qualified half at plate 10 and underproof half at
Plate 10, and only the half of agproximation plate at the Chip Area 11 of plate 10 carries out patch.
It is understood that the half of FPC plate has plywood at plate 10, also have underproof.Industrial commonly referred to as qualification
Preferably plate, underproof is bad plate.If good plate and bad plate carry out patch operation, it will cause unnecessary waste.Therefore
By before patch, finding bad plate in the application, then the cog region on bad plate is removed.Later in patch, patch jig
20 can identify that there are the half of cog region 12 into the preferably plate of plate 10, and eliminating the half of cog region 12 into plate 10 is bad plate, thus
The identification for being able to carry out plate and bad plate operates.
On patch jig 20, if partly at plate 10, preferably plate, cog region 12 are not removed, then the identification of patch jig 20
What is exposed at mouth 212 is exactly cog region 12.If cog region 12 is removed, expose at the identification mouth 212 of patch jig 20
It is exactly patch jig 20 itself.And Chip Area 11 belong to the half of FPC plate at plate 10 a part, it and patch jig 20 itself exist
Difference is very big on material, and difficulty will be greatly reduced when patch jig 20 is screened before patch.
It should be noted that the paster technique of FPC plate, is usually automatically performed by assembly line, flow production line treating capacity is big,
But it is higher to the accuracy requirement of detection.The resolution work of good plate and bad plate, is generally also automatically performed by machine before patch.Such as
Fruit is still identified bad plate before patch by human eye, and is arranged that machine which bad plate is unable to patch, then will be greatly reduced efficiency.
In the prior art, also have through color pencil marking, to help machine recognition bad plate, but color pencil can be because using
The differences such as type cause accuracy to decline.In some embodiments, labeling is proposed on cog region 12 to distinguish bad plate, but is pasted
On label will affect subsequent process.And by way of removing cog region 12, accuracy is higher, will not be to later period process
Have an adverse effect.
The patch processing method of FPC plate according to an embodiment of the present invention, it is convenient and efficient, it is practical, before SMT patch is online
It does not need to carry out resetting chip mounter threshold value according to the plate of different manufacturers or the region bad mark coating situation；For bad
Plate, Direct Recognition patch jig, threshold uniformity is good, and it is abnormal not will cause chip mounter identification；It is small after monomer for striking out
Plate, it is very clear to scrap plate (fork plate) situation, will not mix plate.
As shown in Fig. 2, FPC plate in SMT patch section, has following several processes: baking sheet → online loading board → print solder paste →
Patch → Reflow Soldering.Certainly, the technique during each of above-mentioned operation can be replaced by same process, for example, Reflow Soldering
It can be substituted by immersed solder.Wherein, wherein the identification of bad plate is in " patch " Duan Jinhang, by patch jig 20 when carrying out paster technique
Bad plate is skipped, patch only is carried out to good plate.
Specifically, in step s 4, before half-and-half carrying out patch at the Chip Area 11 of plate 10, tin first is printed to Chip Area 11
Cream.If labelled on cog region 12, the label of protrusion be will affect in print solder paste process on the Chip Area 11 on side
Tin amount causes quality bad.In addition, labeling will lead to cog region 12 than other FPC plate thickness, jigsaw will cause plate when being vacuum-packed
Material deformation.
In some embodiments, as shown in Figure 5 and Figure 6, half whole spelling is formed on the same plate for multiple and connection at plate 10
Connecting plate 100, it is whole to join 100 patch of plate after processing is completed, then carry cutting and be cut into multiple mutually independent FPC plates.
Specifically, the half of FPC plate at plate 10, first it is processed on plate 100 in whole joins, it is whole to join plate 100
Area is big, is easy aid and fixes, shifts.
When each section completes the process on FPC plate, or after being nearly completed, it is whole join plate 100 and carry again cut, be divided into multiple phases
Mutual independent FPC plate.
Specifically, as shown in figure 5, processing when supplied materials be it is whole join plate 100, whole join is provided with multiple rows of multiple row on plate 100
Multiple half at plate 10.This whole setting for joining plate 100, integrated level is high, is conducive to be mass produced.
The whole plate 100 that joins judges whether to need patch by machine recognition before patch.It is (right by dismissing cog region 12
Identification region carries out physical damage), Direct Recognition jig when 20 patch of patch jig, because the gray value consistency of jig is preferable,
Therefore it is abnormal not will cause identification when machine recognition.
In some embodiments, in step s 4, patch jig 20 is according to the brightness and/or colour difference at identification mouth 212
It is different, qualified half is selected into plate 10 and underproof half into plate 10.That is, patch jig 20 is distinguishing plate and bad plate
When, it is identified by the otherness to exposed portion at identification mouth 212.It can be identified by brightness, color can be passed through
Degree is identified, can also be identified by other parameters.
Specifically, in step s 4, by 211 polishing of patch mouth, making the Chip Area 11 exposed at patch mouth 211 and patch
The luminance difference of piece jig 20 itself is obvious.In this way, being conducive to increase difference degree, the differentiation precision of patch jig 20 is improved.
In some embodiments, half is a part of Chip Area 11 at the cog region 12 on plate 10.That is, cog region
12 be also Chip Area 11.
Specifically, cog region 12 is bad mark cog region.Wherein, mark point is alternatively referred to as optical locating point or reflective
Point is the vital signs of SMT patch contraposition.Bad mark cog region is then the cog region 12 to the contraposition of mark point, if passed through
Mark point contraposition inaccuracy is found to the detection of mark point, then will lead to the failure of SMT patch.Therefore, cog region 12 is removed,
It is avoided that the FPC plate for producing failure.
In some embodiments, as shown in fig. 6, patch jig 20 includes: bottom plate 22 and cover board 21, cover board 21 is covered in bottom plate
On 22, half is folded between bottom plate 22 and cover board 21 at plate 10, and patch mouth 211 and identification mouth 212 are located on cover board 21.Pass through bottom
On the one hand plate 22 and cover board 21 will play the role of fixed half into plate 10 half at 10 sandwiched of plate, on the other hand it is convenient subsequently through
The patch mouth 211 that cover board 21 exposes carries out the processes such as print solder paste.
Specifically, the gray value of the side surface towards cover board 21 of bottom plate 22 is consistent, the separate bottom plate 22 of cover board 21
The gray value of one side surface is consistent, and the side of the separate bottom plate 22 of the side surface and cover board 21 towards cover board 21 of bottom plate 22
The gray value on surface is different.In this way, patch jig 20 can identify identification mouth 212 by apparent gray scale difference, and to identification
The FPC plate exposed at mouth 212 is identified.
It is joined on plate 100 more specifically, being partly located at the whole of rectangle at plate 10, bottom plate 22 and cover board 21 are rectangle.In this way
It is easily worked, and processing quantity is big, it is high-efficient.
In some embodiments, as shown in figure 3, half is equipped with multiple Chip Areas 11 at plate 10, between different Chip Areas 11
It is connected by Wiring area 13.
Further, cog region 12 is used for patch, and cog region 12 is a part of Chip Area 11.
Optionally, Wiring area 13 forms " Z " font, and Chip Area 11 is two and is respectively provided at the both ends of Wiring area 13.
Certainly, for FPC plate partly at plate 10, structure can specifically be arranged according to specific needs, be not construed as limiting here.
In some embodiments, as shown in Figure 3 and Figure 4, it when half detects unqualified at the cog region 12 on plate 10, needs
Fig. 4 center area is entirely removed.Cog region 12 can be cut off by way of punching.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
In the description of this specification, the description of reference term " embodiment ", " example " etc. mean combine the embodiment or
Example particular features, structures, materials, or characteristics described are included at least one embodiment or example of the invention.At this
In specification, schematic expression of the above terms be may not refer to the same embodiment or example.Moreover, description is specific
Feature, structure, material or feature can be combined in any suitable manner in any one or more of the embodiments or examples.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that: not
A variety of change, modification, replacement and modification can be carried out to these embodiments in the case where being detached from the principle of the present invention and objective, this
The range of invention is defined by the claims and their equivalents.
Claims (10)
1. a kind of patch processing method of FPC plate, which comprises the steps of:
S1: detecting the half of FPC plate at plate before patch, and described half is equipped with Chip Area and cog region at plate；
S2: described half is removed at testing result on plate for the underproof cog region；
S3: described half is installed on patch jig at plate, the patch jig is equipped with the patch for exposing the Chip Area
Piece mouth and identification mouth for exposing the cog region, the identification mouth exposing after removal of the underproof cog region
Be described patch jig itself；
S4: the patch jig selects qualified described half into plate and underproof described according to the difference at the identification mouth
Half at plate, and only described the half of agproximation plate carries out patch at the Chip Area of plate.
2. the patch processing method of FPC plate according to claim 1, which is characterized in that described half is multiple at plate and connects
Connect formed on the same plate it is whole join plate, it is described it is whole join plate patch after processing is completed, then carry cutting be cut into it is multiple mutually indepedent
The FPC plate.
3. the patch processing method of FPC plate according to claim 1, which is characterized in that in step s 4, the patch is controlled
Tool selects qualified described half into plate and underproof described half according to the brightness and/or coloration difference at the identification mouth
At plate.
4. the patch processing method of FPC plate according to claim 3, which is characterized in that in step s 4, by described
The luminance difference of patch mouth polishing, the Chip Area and the patch jig itself that expose the patch outlet for lantern slide is obvious.
5. the patch processing method of FPC plate according to claim 1, which is characterized in that described half at the knowledge on plate
Other area is a part of the Chip Area.
6. the patch processing method of FPC plate according to claim 1, which is characterized in that the cog region is badmark knowledge
Other area.
7. the patch processing method of FPC plate according to claim 1, which is characterized in that the patch jig includes: bottom plate
And cover board, the cover plate lid is on the bottom plate, and described half is folded between the bottom plate and the cover board at plate, the patch
Mouth and the identification mouth are located on the cover board.
8. the patch processing method of FPC plate according to claim 7, which is characterized in that the bottom plate towards the lid
The gray value of one side surface of plate is consistent, and the gray value of the side surface far from the bottom plate of the cover board is consistent and described
The side surface towards the cover board of bottom plate is different far from the gray value of a side surface of the bottom plate from the cover board.
9. the patch processing method of FPC plate according to claim 7, which is characterized in that described half is located at rectangle at plate
Whole to join on plate, the bottom plate and the cover board are rectangle.
10. the patch processing method of FPC plate according to claim 2, which is characterized in that in step s 4, to described
Before half carries out patch at the Chip Area of plate, first to the Chip Area print solder paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810305364.9A CN110351961B (en) | 2018-04-08 | 2018-04-08 | Paster processing method of FPC board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810305364.9A CN110351961B (en) | 2018-04-08 | 2018-04-08 | Paster processing method of FPC board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110351961A true CN110351961A (en) | 2019-10-18 |
| CN110351961B CN110351961B (en) | 2021-03-05 |
Family
ID=68173170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810305364.9A Expired - Fee Related CN110351961B (en) | 2018-04-08 | 2018-04-08 | Paster processing method of FPC board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110351961B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101009971A (en) * | 2006-01-25 | 2007-08-01 | 日东电工株式会社 | Wired-circuit-board assembly sheet |
| CN201523480U (en) * | 2009-11-17 | 2010-07-07 | 英华达（南京）科技有限公司 | Circuit board with recognizing marks |
| CN205017686U (en) * | 2015-08-31 | 2016-02-03 | 昆山龙朋精密电子有限公司 | A inclined to one side golden finger of scour protection for flexible line way board |
| CN206260135U (en) * | 2016-12-13 | 2017-06-16 | 上海斐讯数据通信技术有限公司 | A kind of pcb board with bad panel sign |
-
2018
- 2018-04-08 CN CN201810305364.9A patent/CN110351961B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101009971A (en) * | 2006-01-25 | 2007-08-01 | 日东电工株式会社 | Wired-circuit-board assembly sheet |
| CN201523480U (en) * | 2009-11-17 | 2010-07-07 | 英华达（南京）科技有限公司 | Circuit board with recognizing marks |
| CN205017686U (en) * | 2015-08-31 | 2016-02-03 | 昆山龙朋精密电子有限公司 | A inclined to one side golden finger of scour protection for flexible line way board |
| CN206260135U (en) * | 2016-12-13 | 2017-06-16 | 上海斐讯数据通信技术有限公司 | A kind of pcb board with bad panel sign |
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| Publication number | Publication date |
|---|---|
| CN110351961B (en) | 2021-03-05 |
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