CN110299376B - 显示设备 - Google Patents
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- CN110299376B CN110299376B CN201910146574.2A CN201910146574A CN110299376B CN 110299376 B CN110299376 B CN 110299376B CN 201910146574 A CN201910146574 A CN 201910146574A CN 110299376 B CN110299376 B CN 110299376B
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 204
- 239000002184 metal Substances 0.000 claims abstract description 204
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 150000004645 aluminates Chemical class 0.000 description 2
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- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 2
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- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
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- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- LCKIEQZJEYYRIY-UHFFFAOYSA-N Titanium ion Chemical compound [Ti+4] LCKIEQZJEYYRIY-UHFFFAOYSA-N 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- OWOMRZKBDFBMHP-UHFFFAOYSA-N zinc antimony(3+) oxygen(2-) Chemical compound [O--].[Zn++].[Sb+3] OWOMRZKBDFBMHP-UHFFFAOYSA-N 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
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- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/262—Sn as the principal constituent
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
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- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
一种显示设备,包括:一基板;一第一金属线及一第二金属线,设置于所述基板上;一第一接垫及一第二接垫,设置于所述基板上且分别与所述第一金属线及所述第二金属线电性连接;以及一电子装置,设置于所述第一接垫及所述第二接垫上,且所述电子装置包括一第一连接柱及一第二连接柱;其中所述第一连接柱与所述第二连接柱之间的距离介于1μm至200μm的范围内,以及其中所述第一连接柱的一部分埋置于所述第一接垫中,所述第二连接柱的一部分埋置于所述第二接垫中。
Description
技术领域
本发明是关于显示设备,且特别是关于显示设备中的电子组件的相互连接(interconnection)。
背景技术
智能型手机、平板计算机、笔记本计算机、显示器及电视等具有显示面板的电子装置已成为现代社会不可或缺的必需品。随着这类可携式电子产品的蓬勃发展,消费者对于这类产品的质量、功能及价格等有更高的期望,下一代显示设备的发展专注于节能及环保的技术。
微型发光二极管(micro LED)技术为新兴的平板显示技术。微型LED显示设备可驱动寻址的(addressed)微型LED的阵列。微型LED显示器可以产生具有宽视角、高亮度及高对比度的无缝影像。然而,由于微型LED的尺寸小,集成化及封装问题为此类产品商业化的主要障碍之一。
于目前的制造方法中,通常形成微型LED且将其分为芯片基底上的多个微型LED管芯(例如,微型发光管芯),接着转移至另一目标基板。举例而言,驱动电路及相关电路形成于目标基板上,以提供阵列基板(例如,TFT阵列基板),然后将微型LED管芯装载于阵列基板上。由于微型LED管芯的尺寸小,将微型LED管芯转移至目标基板是一项繁重的作业。此外,微型LED(包含形成这些管芯的集成电子组件)与目标基板之间的电性连接也是需要注意的问题。
因此,发展出可有效地维持或改善小型电子组件(例如,微型LED)转移的效率,或是改善其与目标基板的电性相互连接的结构及方法,为目前业界所致力的课题之一。
发明内容
根据一些实施例,本发明提供一种显示设备,包括:一基板;一第一金属线及一第二金属线,设置于所述基板上;一第一接垫及一第二接垫,设置于所述基板上且分别与所述第一金属线及所述第二金属线电性连接;以及一电子装置,设置于所述第一接垫及所述第二接垫上,且所述电子装置包括一第一连接柱及一第二连接柱;其中所述第一连接柱与所述第二连接柱之间的距离介于1μm至200μm的范围内,以及其中所述第一连接柱的一部分埋置于所述第一接垫中,所述第二连接柱的一部分埋置于所述第二接垫中。
根据一些实施例,本发明提供一种显示设备,包括:一集成电子组件,包括:一第一基板;一第一金属线及一第二金属线,设置于所述第一基板上;一第一接垫及一第二接垫,设置于所述第一基板上且分别与所述第一金属线及所述第二金属线电性连接;以及一电子装置,设置于所述第一接垫及所述第二接垫上,且所述电子装置包括一第一连接柱及一第二连接柱,其中所述第一连接柱的一部分埋置于所述第一接垫中,且所述第二连接柱的一部分埋置于所述第二接垫中。所述显示设备更包括:一第二基板,设置于所述集成电子组件下方;以及一第三接垫及一第四接垫,设置于所述第二基板上且分别与所述第一金属线及所述第二金属线电性连接;其中所述第一金属线包括一第三连接柱且所述第二金属线包括一第四连接柱,以及其中所述第三连接柱与所述第四连接柱分别与所述第三接垫与所述第四接垫电性连接。
附图说明
为让本发明的上述目的、特征和优点能更明显易懂,以下结合附图对本发明的具体实施方式作详细说明,其中:
图1显示根据本发明一些实施例中,显示设备的剖面示意图;
图2A~2D显示根据本发明一些实施例中,图1的区域M中的金属线及接垫的剖面示意图;
图2E及图2F显示根据本发明一些实施例中,图1的区域M中的金属线及接垫的俯视示意图;
图3~7显示根据本发明一些实施例中,显示设备的剖面示意图;
图8A~8E显示根据本发明一些实施例中,图1的区域M的剖面示意图;
图9显示根据本发明一些实施例中,显示设备的剖面示意图;
图10显示根据本发明一些实施例中,显示设备的剖面示意图;
图11A~11C显示根据本发明一些实施例中,电子装置转移至目标基板的步骤的示意图。
符号说明
10、20、30、40、50、60、70、80 显示设备;
100、100’、100” 第一基板;
102a 第一金属线;
102b 第二金属线;
102e 末端;
102f 外层;
102g 内层;
102s 侧壁;
104a 第一接垫;
104b 第二接垫;
104p 凸起部分;
104s 侧壁;
200、200’、200” 电子装置;
200A 集成电子组件;
200b 底部侧;
202 半导体管芯;
204a 第一电极;
204b 第二电极;
206 第一介电层;
206b 底表面;
208 导电层;
210a 第一连接柱;
210a’ 第一层;
210a” 第二层;
210b 第二连接柱;
210b’ 第一层;
210b” 第二层;
212 第二介电层;
214 粘着层;
214p ***部分;
300 第二基板;
302a 第三金属线;
302b 第四金属线;
304a 第三接垫;
304b 第四接垫;
310a 第三连接柱;
310b 第四连接柱;
314 粘着层;
400 集成电路;
B-B’ 线段;
D1、D2 距离;
H1、H2、H3、H3”、H4、H5 高度;
H3’ 总高度;
M 区域;
T1、T2、T3、T4、T5、T6、T7、T8 厚度;
W1、W2 宽度。
具体实施方式
以下针对本发明的显示设备的结构及其制造方法作详细说明。应了解的是,以下的叙述提供许多不同的实施例,用以实施本发明一些实施例的不同样态。以下所述特定的组件及排列方式仅为简单清楚描述本发明一些实施例。当然,这些仅用以举例而非本发明的限定。此外,在不同实施例中可能使用类似及/或对应的标号标示类似及/或对应的组件,以清楚描述本发明。然而,这些类似及/或对应的标号的使用仅为了简单清楚地叙述本发明一些实施例,不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者,当叙述“一第一材料层”设置于“一第二材料层”上或之上时,包括第一材料层与第二材料层直接接触的情形。或者,亦可能间隔有一或更多其它材料层的情形,在此情形中,第一材料层与第二材料层之间可能不直接接触。
应理解的是,附图的组件或装置可以所属技术领域的技术人员所熟知的各种形式存在。此外,实施例中可能使用相对性用语,例如“较低”或“底部”或“较高”或“顶部”,以描述附图的一个组件对于另一组件的相对关系。可理解的是,如果将附图的装置翻转使其上下颠倒,则所叙述在“较低”侧的组件将会成为在“较高”侧的组件。
应理解的是,虽然在此可使用用语“第一”、“第二”、“第三”等来叙述各种组件、组件、区域、层、部分及/或截面,这些组件、组件、区域、层、部分或截面不应被这些用语限定。这些用语仅是用来区别不同的组件、组件、区域、层、部分或截面。因此,以下讨论的一第一组件、组件、区域、层、部分或截面可在不偏离本发明的教示的情况下被称为一第二组件、组件、区域、层、部分或截面。
本发明实施例可配合附图一并理解,本发明的附图亦被视为揭露说明的一部分。应理解的是,本发明的附图并未按照比例绘制,事实上,可能任意的放大或缩小组件的尺寸以便清楚表现出本发明的特征,而在说明书及附图中,同样或类似的组件将以类似的符号表示。
在此,“约”、“大约”、“实质上”的用语通常表示在一给定值或范围的20%内,较佳是10%内,更佳是5%内,或3%之内,或2%之内,或1%之内,或0.5%之内。在此给定的数量为大约的数量,亦即在没有特定说明“约”、“大约”、“实质上”的情况下,仍可隐含“约”、“大约”、“实质上”的含义。
除非另外定义,在此使用的全部用语(包含技术及科学用语)具有与本发明所属技术领域的技术人员通常理解的相同涵义。能理解的是,这些用语例如在通常使用的字典中定义用语,应被解读成具有与相关技术及本发明的背景或上下文一致的意思,而不应以一理想化或过度正式的方式解读,除非在本发明实施例有特别定义。
此外,在本发明一些实施例中,关于接合、连接的用语例如“连接”、“互连”等,除非特别定义,否则可指两个结构是直接接触,或者亦可指两个结构并非直接接触,其中有其它结构设于此两个结构之间。且此关于接合、连接的用语亦可包括两个结构都可移动,或者两个结构都固定的情况。
根据本发明的一些实施例,提供一种用于改善尺寸较小的电子装置(例如,次毫米LED、微型LED、有机LED、非有机LED(例如:量子点LED)或集成电子组件等)与尺寸较大的目标基板(例如,阵列基板)之间的电性连接效率的结构。本发明提供的显示设备包含可稳固地埋置于目标基板的导电组件(例如,用于相互连接的接垫)中的连接柱。因此,可维持电子装置对目标基板上的电路***的有效电性连接。此外,根据本发明的一些实施例,显示设备中的中间基板的设置可减少将小型电子装置转移至目标基板所需的时间。
图1显示根据本发明一些实施例中,显示设备10的剖面示意图。应理解的是,根据一些实施例中,可添加额外特征于显示设备。根据一些实施例中,以下所述的部分特征可以被取代或删除。
请参照图1,显示设备10包含第一基板100以及设置于第一基板100上的电子装置200。第一基板100可为显示设备10的中间基板或目标基板(例如,阵列基板)。在一些实施例中,第一基板100可包含玻璃、石英、蓝宝石(sapphire)、聚碳酸酯(polycarbonate,PC)、聚酰亚胺(polyimide,PI)、聚对苯二甲酸乙二酯(polyethylene terephthalate,PET)、橡胶、玻璃纤维、其它高分子材料、其它合适的基板材料或前述的组合,但不限于此。在一些实施例中,第一基板100可由金属-玻璃纤维复合板材、金属-陶瓷复合板材或印刷电路板等制成。
显示设备10亦包含设置于第一基板100上的第一金属线102a及第二金属线102b。第一金属线102a及第二金属线102b可为第一基板100上的任意导电材料。例如,第一金属线102a及第二金属线102b可各自为阵列基板上的电路的导电材料。在一些实施例中,第一金属线102a及第二金属线102b可为阵列基板上的数据线或扫描线。第一金属线102a及第二金属线102b于第一基板100的法线方向上(例如,如图1所示的X方向上)分别具有厚度T1及厚度T2。在一些实施例中,第一金属线102a的厚度T1可在约0.1μm至约1μm的范围内,或约0.2μm至约0.6μm的范围内。在一些实施例中,第二金属线102b的厚度T2可在约0.1μm至约1μm的范围内,或约0.2μm至约0.6μm的范围内。第一金属线102a的厚度T1可与第二金属线102b的厚度T2相同或不同。
在一些实施例中,第一金属线102a及第二金属线102b可各自由相同或不同的导电材料形成。用于形成第一金属线102a及第二金属线102b的材料可包含铜、铝、钨、钛、金、银、钼、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、其它合适的导电材料或前述的组合,但不限于此。在一些实施例中,第一金属线102a及第二金属线102b可各自由具有较高熔化温度(melting temperature)的导电材料形成。在一些实施例中,第一金属线102a及第二金属线102b可各自由熔化温度在约660℃至约3410℃范围内的导电材料形成。
此外,在一些实施例中,第一金属线102a及/或第二金属线102b可包含多层结构。举例而言,图2A显示根据本发明一些实施例中,图1的区域M中的第二金属线102b及第二接垫104b的剖面示意图。如图2A所示,根据一些实施例,第二金属线102b可至少为双层结构。具体而言,第二金属线102b可为同轴的双层结构,其包含内层102g及外层102f。在一些特定的实施例中,内层102g可由铝形成,外层102f可由钼形成。此外,应理解的是,图2A~2F仅以第二金属线102b及第二接垫104b为例进行说明,未绘示的第一金属线102a及第一接垫104a亦可具有相同或类似的特征。
接着,请再次参照图1,显示设备10亦包含设置于第一基板100上的第一接垫104a及第二接垫104b。第一接垫104a及第二接垫104b分别与第一金属线102a及第二金属线102b电性连接。换言之,第一接垫104提供电子装置200与第一基板100上的第一金属线102a之间的电性连接。第二接垫104b提供电子装置200与第一基板100上的第二金属线102b之间的电性连接。如图1所示,第一接垫104a及第二接垫104b分别与第一金属线102a及第二金属线102b至少部分地重叠,使得第一接垫104a与第一金属线102a以及第二接垫104b与第二金属线102b之间可维持良好的电性连接。具体而言,第一接垫104a与第一金属线102a以及第二接垫104b与第二金属线102b之间的重叠可分别有助于第一金属线102a及第二金属线102b中的电信号传输或减少漏电的可能性。
图2B~2D详细描述根据本发明的一些实施例中,第二金属线102b与第二接垫104b的配置。图2B~2D显示根据本发明一些实施例中,图1的区域M中的第二金属线102b及第二接垫104b的剖面示意图。应理解的是,图中省略了除金属线及接垫之外的组件,以便清楚说明。
如图2B所示,根据一些实施例,第二接垫104b的一部分与第二金属线102b重叠。详细而言,第二接垫104b可覆盖第二金属线102b的侧壁及顶表面的一部分。如图2C及图2D所示,在一些实施例中,整个第二接垫104b设置于第二金属线102b上。根据一些实施例,第二接垫104b的侧壁104s可与第二金属线102b的侧壁102s对齐(如图2C所示)。根据一些实施例,第二金属线102b可以进一步向电子装置200的中心延伸,且第二金属线102b的侧壁102s可突出于第二接垫104b的侧壁104s(如图2D所示)。
另一方面,图2E及图2F显示根据本发明一些实施例中,图1的区域M中的第二金属线102b与第二接垫104b的俯视示意图。此外,沿着图2E中的线段B-B’的剖面图可对应于图2B及图2C所示的剖面图。沿着图2F中的线段B-B’的剖面图可对应于图2D所示的剖面图。请参照图2B、2C及2E,在一些实施例中,第二接垫104b可与第二金属线102b的端部102e完全地重叠,亦即,第二接垫104b可完全地覆盖第二金属线102b的端部102e。请参照图2D及图2F,在一些实施例中,第二接垫104b可与第二金属线102b的端部102e部分地重叠,亦即,第二接垫104b可部分地覆盖第二金属线102b的端部102e。根据本发明一些实施例,所述“第二金属线102b的端部102e”指的是从第二金属线102b的侧壁102s且沿着Y方向,往内延伸约100μm范围内的部分。
接着,请再次参照图1,第一接垫104a及第二接垫104b在第一基板100的法线方向(亦即X方向)上可分别具有厚度T3及厚度T4。在一些实施例中,第一接垫104a的厚度T3可在约0.2μm至约50μm的范围内,或约5μm至约15μm的范围内。在一些实施例中,第二接垫104b的厚度T4可在约0.2μm至约50μm的范围内,或约5μm至约15μm的范围内。第一接垫104a的厚度T3可与第二接垫104b的厚度T4相同或不同。在一些实施例中,第一接垫104a的厚度T3大于第一金属线102a的厚度T1。在一些实施例中,第二接垫104b的厚度T4大于第二金属线102b的厚度T2。
在一些实施例中,第一接垫104a及第二接垫104b可各自由导电材料形成。用于形成第一接垫104a及第二接垫104b的导电材料可包含焊料(solder material)、锡、铟、镓、锡合金、铟合金、镓合金、镓-铟合金或前述的组合,但不限于此。在一些实施例中,第一接垫104a及第二接垫104b可各自由具有较低熔化温度的导电材料形成。具体而言,第一接垫104a及第二接垫104b可分别由与第一金属线102a及第二金属线102b的熔化温度相比具有较低熔化温度的导电材料形成。在一些实施例中,第一接垫104a及第二接垫104b可各自由熔化温度在约100℃至约400℃范围内的导电材料形成。
在一些实施例中,可使用化学气相沉积制程、物理气相沉积制程、电镀制程、无电电镀制程、其它合适的制程或前述的组合形成第一金属线102a、第二金属线102b、第一接垫104a及第二接垫104b。所述化学气相沉积制程例如可包含低压化学气相沉积(lowpressure chemical vapor deposition,LPCVD)制程、低温化学气相沉积(lowtemperature chemical vapor deposition,LTCVD)制程、快速升温化学气相沉积(rapidthermal chemical vapor deposition,RTCVD)制程、等离子辅助化学气相沉积(plasmaenhanced chemical vapor deposition,PECVD)制程或原子层沉积(atomic layerdeposition,ALD)制程等。所述物理气相沉积制程例如可包含溅镀制程、蒸镀制程或脉冲激光沉积(pulsed laser deposition,PLD)制程等。
请继续参照图1,电子装置200包含半导体管芯202、第一电极204a、第二电极204b、第一介电层206、导电层208、第一连接柱210a、第二连接柱210b及第二介电层212。电子装置200可包含集成电路。举例而言,电子装置200可包含数字电路、LED、光电二极管、晶体管或其它合适的电子装置,但不限于此。在一些实施例中,电子装置200可为微型LED。应理解的是,虽然图1仅绘示一个电子装置200,但实际上第一基板100上可设置有多于一个的电子装置200。
如图1所示,电子装置200设置于第一接垫104a及第二接垫104b上。电子装置200的半导体管芯202可包含不同材料形成的多层。在一些实施例中,半导体管芯202可包含半导体层或量子阱层,但不限于此。在一些实施例中,半导体层可由III-V族化合物形成。III-V族化合物可包含氮化镓(GaN)、氮化铟(InN)、氮化铝(AlN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)、氮化铝镓铟(AlGaInN)或前述的组合,但不限于此。在一些实施例中,量子阱层的材料可包含氮化铟镓、氮化镓或前述的组合,但不限于此。
根据一些实施例,半导体管芯202可为有机微型LED管芯。根据一些实施例,半导体管芯202可为无机微型LED管芯。在一些实施例中,半导体管芯202于Y-Z平面的剖面的面积可具有在约1μm至约175μm的范围内的长度(于Y方向),以及可具有在约1μm至约175μm的范围内的宽度(于Z方向)。在一些实施例中,半导体管芯202的尺寸可为约1μm×1μm×1μm至约175μm×175μm×175μm。在一些实施例中,可使用磊晶成长制程形成半导体管芯202。例如,可使用金属有机化学气相沉积(metal organic chemical vapor deposition,MOCVD)制程、分子束磊晶(molecular beam epitaxy,MBE)制程、氢化物气相磊晶法(hydride vaporphase epitaxy,HVPE)、液相磊晶(liquid phase epitaxy,LPE)制程或前述的组合形成半导体管芯202。
第一电极204a及第二电极204b可设置于半导体管芯202上。在电子装置200为微型LED的一些实施例中,第一电极204a及第二电极204b可分别作为微型LED的n电极及p电极。在一些实施例中,第一电极204a及第二电极204b可由金属导电材料形成。金属导电材料可包含铜、铝、钨、钛、金、银、钼、铂、镍、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、铂合金、镍合金、其它合适的金属导电材料或前述的组合,但不限于此。在一些实施例中,第一电极204a及第二电极204b可由透明导电材料(TCO)形成。例如,透明导电材料可包含铟锡氧化物(ITO)、氧化锡(SnO)、氧化锌(ZnO)、氧化铟锌(IZO)、氧化铟镓锌(IGZO)、氧化铟锡锌(ITZO)、氧化锑锡(ATO)、氧化锑锌(AZO)、其它适合的透明导电材料或前述的组合,但不限于此。应注意的是,相较于电子装置200的导电层208,第一电极204a及第二电极204b可由具有较高熔化温度的材料形成。在一些实施例中,可使用化学气相沉积制程、物理气相沉积制程、电镀制程、无电镀制程、其它合适的制程或前述的组合形成第一电极204a及第二电极204b。
请继续参照图1,第一介电层206设置于半导体管芯202上。在一些实施例中,第一电介质层206可覆盖第一电极204a的一部分及第二电极204b的一部分。换言之,第一介电层206可部分地暴露第一电极204a及第二电极204b,使得第一电极204a及第二电极204b可以电性连接至导电层208。在一些实施例中,第一介电层206可包含氧化硅、氮化硅、氮氧化硅、高介电常数(high-k)介电材料、其它合适的介电材料或前述的组合,但不限于此。高介电常数介电材料可包含金属氧化物、金属氮化物、金属硅化物、过渡金属氧化物、过渡金属氮化物、过渡金属硅化物、金属氮氧化物、金属铝酸盐、锆硅酸盐或锆铝酸盐,但不限于此。在一些实施例中,可借由化学气相沉积制程、旋转涂布(spin coating)制程、其它合适的制程或前述的组合形成第一介电层206。
此外,电子装置200包含设置于第一介电层206上方的导电层208。承前述,导电层208与第一电极204a及第二电极204b的一部分接触。导电层208分别与第一电极204a及第二电极204b电性连接。此外,如图1所示,导电层208包含第一连接柱210a及第二连接柱210b。第一连接柱210a及第二连接柱210b各自定义为实质上位于电子装置200的底部侧200b下方的部分。在一些实施例中,第一连接柱210a及第二连接柱210b可从第一介电层206的底表面206b突出。在一些实施例中,第一连接柱210a及第二连接柱210b亦可从半导体管芯202的底表面202b突出。换言之,第一连接柱210a及第二连接柱210b朝向第一基板100延伸。第一连接柱210a及第二连接柱210b分别朝向第一接垫104a及第二接垫104b延伸。此外,至少一部分的第一连接柱210a埋置(embed)于第一接垫104a中,且至少一部分的第二连接柱210b埋置于第二接垫104b中。因此,第一连接柱210a电性连接至第一接垫104a,第二连接柱210b电性连接至第二接垫104b。应理解的是,虽然于图1所示的实施例中设置了两个连接柱,但在另一些实施例中可根据需要调整连接柱的数量。
如图1所示,第一连接柱210a与第二连接柱210b彼此分离距离D1。在一些实施例中,第一连接柱210a与第二连接柱210b之间的距离D1在约1μm至约200μm的范围内,或约2μm至约50μm的范围内。在一些实施例中,第一连接柱210a与第二连接柱210b之间的距离D1定义为第一连接柱210a中的任一位置与第二连接柱210b中的任一位置之间的距离。在另一些实施例中,第一连接柱210a与第二连接柱210b之间的距离D1定义为第一连接柱210a于第一基板100的法线方向(X方向)上的最低点与第二连接柱210a于第一基板100的法线方向上的最低点之间的距离。
再者,第一连接柱210a及第二连接柱210b在第一基板100的法线方向上(例如,X方向)分别具有高度H1及高度H2。在一些实施例中,第一连接柱210a的高度H1可在约0.05μm至约10μm的范围内,或约1μm至约5μm的范围内。在一些实施例中,第二连接柱210b的高度H2可在约0.05μm至约10μm的范围内,或约1μm至约5μm的范围内。
在一些实施例中,第一连接柱210a、第二连接柱210b及导电层208为一体形成的。第一连接柱210a、第二连接柱210b及导电层208可为连续结构。在另一些实施例中,第一连接柱210a、第二连接柱210b及导电层208为分开形成的。第一连接柱210a、第二连接柱210b及导电层208可为独立的组件。此外,第一连接柱210a及导电层208可由相同或不同的材料形成。相似地,第二连接柱210b及导电层208可由相同或不同的材料形成。
在一些实施例中,第一连接柱210a及第二连接柱210b可各自由导电材料形成。用于形成第一连接柱210a及第二连接柱210b的材料可包含铜、铝、钨、钛、金、银、钼、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、其它合适的导电材料或前述的组合,但不限于此。在一些实施例中,第一连接柱210a及第二连接柱210b可各自由具有较高熔化温度的导电材料形成。在一些实施例中,第一连接柱210a及第二连接柱210b可各自由熔化温度在约660℃至约3410℃范围内的导电材料形成。
第二介电层212形成于导电层208上,第二介电层212亦覆盖第一连接柱210a及第二连接柱210b。在一些实施例中,第二介电层212可包含氧化硅、氮化硅、氮氧化硅、高介电常数(high-k)介电材料、其它合适的介电材料或前述的组合,但不限于此。高介电常数介电材料可包含金属氧化物、金属氮化物、金属硅化物、过渡金属氧化物、过渡金属氮化物、过渡金属硅化物、金属氮氧化物、金属铝酸盐、锆硅酸盐或锆铝酸盐,但不限于此。在一些实施例中,可借由化学气相沉积制程、旋转涂布制程、其它合适的制程或前述的组合形成第二介电层212。
此外,显示设备10亦包含设置于电子装置200及第一基板100之间的粘着层214。粘着层214将电子装置200与第一基板100粘合在一起,并使第一连接柱210a及第二连接柱210b分别与第一基板100上的第一接垫104a及第二接垫104b保持实体接触。粘着层214可由粘着材料形成。在一些实施例中,粘着层214可为绝缘体。在一些实施例中,粘着层214的材料可包含热固化粘着剂、光固化粘着剂或前述的组合,但不限于此。光固化粘着剂可包含UV光固化粘着剂或可见光固化粘着剂。
在一些实施例中,可使用涂布、喷涂、喷墨印刷、其它合适的方法或前述的组合形成粘着层214。如图1所示,根据一些实施例,粘着层214可具有液滴形状。
应注意的是,在一些实施例中,在电子装置200固定至第一基板100之前,第一基板100及设置于其上形成的组件会先被加热。详细而言,第一接垫104a及第二接垫104b被加热至熔化状态(melted state),使得第一连接柱210a及第二连接柱210b可分别埋置于第一接垫104a及第二接垫104b中。在一些实施例中,第一连接柱210a及第二连接柱210b的熔化温度分别高于第一接垫104a及第二接垫104b的熔化温度。在此种情况下,可在接垫实质上熔化且连接柱不熔化的范围内,调整加热步骤的温度。在另一些实施例中,连接柱的硬度大于接垫的硬度,使得连接柱可埋置于接垫中。
此外,由于设置于第一基板100上的第一金属线102a及第二金属线102b在加热过程中亦会被加热,因此,根据一些实施例,第一金属线102a及第二金属线102b的熔化温度分别高于第一接垫104a及第二接垫104b的熔化温度。具体而言,在一些实施例中,金属线的熔化温度与接垫的熔化温度的比值在约1.5至约35的范围内,或约1.5至约17的范围内。应注意的是,金属线的熔化温度与接垫的熔化温度的比值不应过小,否则金属线可能会在加热过程中熔化或变形,而造成金属线损坏的风险。此外,金属线的熔化温度与接垫的熔化温度的比值不应过大,否则金属线的膨胀系数与接垫的膨胀系数的差异可能过大,而使得金属线与接垫彼此剥离。
如同前述,第一接垫104a及第二接垫104b分别可由与第一金属线102a及第二金属线102b的材料相比具有较低的熔化温度的导电材料形成。用于形成第一接垫104a及第二接垫104b的具有较低熔化温度的导电材料可包含焊料、锡、铟、镓、锡合金、铟合金、镓合金、镓-铟合金或前述的组合,但不限于此。第一连接柱210a及第二连接柱210b分别可由与第一接垫104a及第二接垫104b的材料相比具有较高的熔化温度的导电材料形成。用于形成第一连接柱210a及第二连接柱210b的具有较高熔化温度的导电材料可包含铜、铝、钨、钛、金、银、钼、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、其它合适的导电材料或前述的组合,但不限于此。此外,第一金属线102a及第二金属线102b分别亦可由与第一接垫104a及第二接垫104b的材料相比具有较高的熔化温度的导电材料形成。用于形成第一金属线102a及第二金属线102b的具有较高熔化温度的导电材料可包含铜、铝、钨、钛、金、银、钼、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、其它合适的导电材料或前述的组合,但不限于此。
前述材料的熔化温度如下表所列示:
材料 | 熔化温度(℃) |
焊料 | 400 |
锡 | 232 |
铟 | 157 |
镓-铟合金 | 100 |
镓 | 30 |
钼 | 2623 |
金 | 1065 |
铜 | 1085 |
钛 | 1660 |
钨 | 3407 |
银 | 961 |
铝 | 660 |
接着,请参照图3,图3显示根据本发明一些实施例中,显示设备20的剖面示意图。应理解的是,后文中与前文相同或相似的组件或组件将以相同或相似的标号表示,其材料、制造方法与功能与前文所述相同或相似,故此部分在后文中将不再赘述。图3所示的显示设备20与图1所示的显示设备10之间的差异在于,显示设备20具有不同轮廓(profile)的第一连接柱210a及第二连接柱210b。如图3所示,显示设备20具有钟形的(bell-shaped)第一连接柱210a及钟形的第二连接柱210b。在此实施例中,第一连接柱210a及第二连接柱210b具有钝端(blunt end)。相较于具有尖端的连接柱,具有钝端的连接柱可进一步减少静电的累积,可提高连接柱与接垫之间的电连接效率。因为具有钝端的连接柱较不易产生尖端放电(corona discharge)损坏接垫,且使得接垫的表面较不易氧化。在此种情况下,连接柱与接垫之间的电连接效率可进一步提升。实际上,第一连接柱210a及第二连接柱210b可具有其它合适的任意形状,只要第一连接柱210a及第二连接柱210b从电子装置200的底部侧200b突出并可埋置于第一接垫104a及第二接垫104b中。例如,第一连接柱210a及第二连接柱210b可具有锥体形状或柱体形状,但不限于此。
接着,请参照图4,图4显示根据本发明一些实施例中,显示设备30的剖面示意图。图4所示的显示设备30与图1所示的显示设备10之间的差异在于,在图4所示实施例中,第一连接柱210a及第二连接柱210b的材料及导电层208的材料不同。在一些实施例中,连接柱(第一连接柱210a及第二连接柱210b)及导电层208可分开形成。如上所述,第一连接柱210a及第二连接柱210b可分别由与第一接垫104a及第二接垫104b的材料相比具有较高的熔化温度的导电材料形成。此外,第一连接柱210a及第二连接柱210b可由与导电层208的材料相比具有较低的熔化温度的导电材料形成,使得导电层208可不受加热期间的高温影响。因此,可不影响导电层208的功能(例如,导电性),以维持电子装置的效能。
接着,请参照图5,图5显示根据本发明一些实施例中,显示设备40的剖面示意图。图5所示的显示设备40与图4所示的显示设备30之间的差异在于,在图5所示的实施例中,第一连接柱210a及第二连接柱210b具有多层结构。如图5所示,第一连接柱210a包含第一层210a’及第二层210a”,第二连接柱210b包含第一层210b’及第二层210b”。具体而言,在一些实施例中,第一连接柱210a的第一层210a’及第二连接柱210b的第一层210b’可由与导电层208相同的材料形成。换言之,第一层210a’及第一层210b’可由具有相对高的熔化温度的导电材料形成。在一些实施例中,第一连接柱210a的第二层210a”及第二连接柱210b的第二层210b”可由与第一层210a’及第一层210b’的材料相比分别具有较低熔化温度的导电材料形成。此外,第二层210a”及第二层210b”可分别由与第一接垫104a及第二接垫104b相比具有较高熔化温度的导电材料形成。
接着,请参照图6,图6显示根据本发明一些实施例中,显示设备50的剖面示意图。图6所示的显示设备50与图1所示的显示设备10之间的差异在于,在图6所示的实施例中,粘着层214填充于电子装置200与第一基板100之间的空间中。具体而言,粘着层214实质上填充于由半导体管芯202、第一介电层206、第一连接柱210a、第二连接柱210b、第一接垫104a、第二接垫104b及第一基板100所界定的空间中。在此实施例中,粘着层214与第一接垫104a及第二接垫104b实体接触。在一些实施例中,粘着层214亦与第一连接柱210a及第二连接柱210b实体接触。
接着,请参照图7,图7显示根据本发明一些实施例中,显示设备60的剖面示意图。图7所示的显示设备60与图6所示的显示设备50之间的差异在于,在图7所示的实施例中,粘着层214进一步延伸于位于第一连接柱210a及第二连接柱210b之外的第一接垫104a及第二接垫104b上。如图7所示,粘着层214实质上覆盖整个第一接垫104a及第二接垫104b。在一些实施例中,粘着层214的边缘实质上可与第一接垫104a及/或第二接垫104b的边缘对齐。
接着,请参照图8A至8E,图8A~8E显示根据本发明一些实施例中,图1的区域M的剖面示意图。应理解的是,附图中省略了一些组件以清楚说明。此外,应理解的是,图8A至8E仅以第二连接柱210b及第二接垫104b为例进行说明,未绘示的第一连接柱210a及第一接垫104a亦可具有相同或类似的特征。如上所述,第一连接柱210a及第二连接柱210b的至少一部分分别埋置于第一接垫104a及第二接垫104b中。因此,接垫的一部分将被挤压,且在连接柱埋置于接垫的位置周围形成凸起部分(bulging portion)。如图8A所示,在一些实施例中,第二接垫104b包含位于埋置于第二接垫104b中的第二连接柱210b的周围的凸起部分104p。换言之,凸起部分104p围绕埋置于第二接垫104b中的第二连接柱210b的部分。如图8B所示,在一些实施例中,在粘着层214填充于电子装置200与第一基板100之间的空间中的一些实施例中(例如,如图6所示),接垫包含凸起部分104p,且粘着层214亦包含位于埋置于接垫中的连接柱的周围的***部分(swelling portion)214p,亦即,接垫包含***部分214p,其围绕埋置于接垫中的连接柱的部分。如图8C所示,在粘着层214填充于电子装置200与第一基板100之间的空间中的一些实施例中(例如,如图6所示),粘着层214包含围绕第二连接柱210b的***部分214p,而第二接垫104b未被挤压。此外,如图8D所示,在粘着层214实质上覆盖整个第二接垫104b的另一些实施例中(例如,如图7所示),第二接垫104b包含凸起部分104p,且粘着层214亦包含位于埋置于第二接垫104b中的第二连接柱210b的周围的***部分214p。如图8E所示,在粘着层214实质上覆盖整个第二接垫104b的另一些实施例中(例如,如图7所示),粘着层214包含围绕第二连接柱210b的***部分214p,而第二接垫104b未被挤压。
在一些实施例中,第二接垫104b的凸起部分104p具有高度H3(如图8A所示)。高度H3可定义为于第一基板100的法线方向(X方向)上,凸起部分104p的最高点与凸起部分104p的最低点之间的距离。在一些实施例中,凸起部分104p的高度H3可为在约0.1μm至约5μm的范围内,或约1μm至约3μm的范围内。在第二接垫104b及粘着层214包含凸起部分104p及***部分214p的一些实施例中,凸起部分104p及***部分214p具有总高度H3’(如图8D所示)。总高度H3’可定义为于第一基板100的法线方向(X方向)上,***部分214p的最高点与凸起部分104p的最低点之间的距离。在一些实施例中,凸起部分104p及***部分214p的总高度H3’可在约0.1μm至约5μm的范围内,或约1μm至约3μm的范围内。此外,在粘着层214包含***部分214p的一些实施例中,粘着层214的***部分214p具有高度H3”(如图8E所示)。高度H3”可定义于第一基板100的法线方向(X方向)上,***部分214p的最高点与***部分214p的最低点之间的距离。在一些实施例中,***部分214p的高度H3”可在约0.1μm至约5μm的范围内,或约1μm至约3μm的范围内。
在一些实施例中,埋置于第二接垫104b中的第二连接柱210b的部分具有高度H4(如图8A所示)。在一些实施例中,埋置于第二接垫104b中的第二连接柱210b的部分及粘着层214具有高度H4(如图8D所示)。在一些实施例中,埋置于粘着层214中的第二连接柱210b的部分具有高度H4(如图8E所示)。如上所述,第二连接柱210b在第一基板100的法线方向(X方向)上具有高度H2。在一些实施例中,埋置于第二接垫104b及/或粘着层214中的第二连接柱210b的部分的高度H4与第二连接柱210b的高度H2的比值在0.1至1的范围内(即,0.1≤H4/H2≤1)。在一些实施例中,埋置于粘着层214中的第一连接柱210a的部分具有高度H5(未绘示)。相似地,在一些实施例中,埋置于第一接垫104a及/或粘着层214中的第一连接柱210a的部分的高度H5与第一连接柱210a的高度H1的比值在0.1至1的范围内(即,0.1≤H5/H1≤1)。
接着,请参照图9,图9显示根据本发明一些实施例中,显示设备70的剖面示意图。图9所示的显示设备70与图1所示的显示设备10之间的差异在于,在图9所示的实施例中,电子装置200是以覆晶形式(flip chip type)设置。在此实施例中,导电层208可直接作为埋置于接垫104a/104b中的连接柱。电子装置200可借由埋置于接垫中的导电层208的一部分电性连接至接垫104a/104b。
接着,请参照图10,图10显示根据本发明一些实施例中,显示设备80的剖面示意图。显示设备80包含集成电子组件200A及设置于集成电子组件200A下方的第二基板300。集成电子组件200A与图1中描述的显示设备10大致上相同。具体而言,集成电子组件200A包含第一基板100、设置于第一基板100上的第一金属线102a及第二金属线102b、以及设置于第一基板100上的第一接垫104a及第二接垫104b。第一接垫104a及第二接垫104b分别与第一金属线102a及第二金属线102b电性连接。集成电子组件200A亦包含设于第一接垫104a及第二接垫104b上的电子装置200。电子装置200包含第一连接柱210a及第二连接柱210b,且第一连接柱210a的一部分埋置于第一接垫104a中,第二连接柱210b的一部分埋置于第二接垫104b中。这些组件的材料、制造方法及功能与前述相同或相似,故于此不再赘述。
在一些实施例中,第二基板300可作为显示设备80的目标基板(例如,阵列基板)。第一基板100可作为中间基板,中间基板可将形成于其上的组件承载至目标基板(例如,第二基板300)。在一些实施例中,多个电子装置200设置于第一基板100上。如上所述,电子装置200可包含数字电路、LED、光电二极管、晶体管或其它合适的电子装置,但不限于此。在一些实施例中,电子装置200可为微型LED。在一些实施例中,电子装置200更包含设置于第一基板100上的至少一集成电路400。在另一些实施例中,电子装置200包含多个集成电路、其它电子组件或其它光电组件,以及将多个电子组件互相连接以于第一基板100上形成电路的导电线。第一基板100可承载有多个组件形成于其上的集成电子组件200A,将其设置于第二基板300上,借此可以减少组件转移所需的时间。
在一些实施例中,第二基板300可包含玻璃、石英、蓝宝石(sapphire)、聚碳酸酯(polycarbonate,PC)、聚酰亚胺(polyimide,PI)、聚对苯二甲酸乙二酯(polyethyleneterephthalate,PET)、橡胶、玻璃纤维、其它高分子材料、其它合适的基板材料或前述的组合,但不限于此。在一些实施例中,第一基板100可由金属-玻璃纤维复合板材、金属-陶瓷复合板材或印刷电路板等制成。第二基板300的材料可与第一基板100的材料相同或不同。
此外,显示设备80亦包括设置于第二基板300上的第三金属线302a及第四金属线302b。第三金属线302a及第四金属线302b可为第二基板上的任意导电材料。例如,第三金属线302a及第四金属线302b可各自为阵列基板上的电路的导电材料。在一些实施例中,第三金属线302a及第四金属线302b可为阵列基板上的数据线或扫描线。第三金属线302a及第四金属线302b于第一基板100的法线方向(X方向)上分别具有厚度T5及厚度T6。在一些实施例中,第三金属线302a的厚度T5可在约0.1μm至约1μm,或约0.2μm至约0.6μm的范围内。在一些实施例中,第四金属线302b的厚度T6可在约0.1μm至约1μm的范围内,或约0.2μm至约0.6μm的范围内。此外,第三金属线302a的厚度T5可与第四金属线302b的厚度T6相同或不同。
在一些实施例中,第三金属线302a及第四金属线302b可各自由导电材料形成。用于形成第三金属线302a及第四金属线302b的材料可包含铜、铝、钨、钛、金、银、钼、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、其它合适的导电材料或前述的组合,但不限于此。在一些实施例中,第三金属线302a及第四金属线302b可各自由具有较高熔化温度(melting temperature)的导电材料形成。在一些实施例中,第三金属线302a及第四金属线302b可各自由熔化温度在约660℃至约3410℃范围内的导电材料形成。此外,在一些实施例中,第三金属线302a及/或第四金属线302b可具有多层结构。
如图10所示,显示设备80亦包含设置于第二基板300上的第三接垫304a及第四接垫304b。第三接垫304a及第四接垫304b分别与第三金属线302a及第四金属线302b电性连接。第三接垫304a提供集成电子组件200A与第二基板300上的第三金属线302a之间的电性连接。第四接垫304b提供集成电子组件200A与第二基板300上的第四金属线302b之间的电性连接。如图10所示,第三接垫304a及第四接垫304b分别与第三金属线302a及第四金属线302b至少部分地重叠,使得第三接垫304a与第三金属线302a以及第四接垫304b与第四金属线302b之间可维持良好的电性连接。具体而言,接垫与金属线之间的重叠有助于金属线中的电信号传输或减少漏电的可能性。
在一些实施例中,第三接垫304a及第四接垫304b在第一基板100的法线方向(X方向)上分别具有厚度T7及厚度T8。在一些实施例中,第三接垫304a的厚度T7可在约0.2μm至约50μm,或约5μm至约15μm的范围内。在一些实施例中,第四接垫304b的厚度T8可在约0.2μm至约50μm的范围内,或约5μm至约15μm的范围内。第三接垫304a的厚度T7可与第四接垫304b的厚度T8相同或不同。在一些实施例中,第三接垫304a的厚度T7大于第三金属线302a的厚度T5。在一些实施例中,第四接垫304b的厚度T8大于第四金属线302b的厚度T6。此外,由于相较于第一接垫104a,第三接垫304a需要传输更多的电流,因此第三接垫304a的面积(或尺寸)大于第一接垫104a的面积(或尺寸)。相似地,在一些实施例中,由于相较于第二接垫104b,第四接垫304b需要传输更多电流,因此第四接垫304b的面积(或尺寸)大于第二接垫104b的面积(或尺寸)
在一些实施例中,第三接垫304a及第四接垫304b可各自由相同或不同导电材料形成。用于形成第三接垫304a及第四接垫304b的导电材料可包含焊料、锡、铟、镓、锡合金、铟合金、镓合金、镓-铟合金或前述的组合,但不限于此。在一些实施例中,第三接垫304a及第四接垫304b可各自由具有较低熔化温度的导电材料形成。具体而言,第三接垫304a及第四接垫304b可分别由与第三金属线302a及第四金属线302b的熔化温度相比具有较低熔化温度的导电材料形成。在一些实施例中,第三接垫304a及第四接垫304b可各自由熔化温度在约100℃至约400℃范围内的导电材料形成。
另一方面,应注意的是,集成电子组件200A的第一金属线102a更包含第三连接柱310a,且集成电子组件200A的第二金属线102b更包含第四连接柱310b。第三连接柱310a及第四连接柱310b分别与第一金属线102a及第二金属线102b电性连接。如图10所示,第一金属线102a及第二金属线102b从第一基板100朝向第二基板300延伸,以提供集成电子组件200A与第二基板300之间的电性连接。第三连接柱310a及第四连接柱310b亦朝向第二基板300延伸。第三连接柱310a及第四连接柱310b分别朝向第三接垫304a及第四接垫304b延伸。此外,第三连接柱310a及第四连接柱310b分别与第三接垫304a及第四接垫304b接触。在一些实施例中,第三连接柱310a的至少一部分埋置于第三接垫304a中,第四连接柱310b的至少一部分埋置于第四接垫304b中。因此,第三连接柱310a电性连接至第三接垫304a,第四连接柱310b电性连接至第四接垫304b。
在一些实施例中,连接柱(第三连接柱310a及第四连接柱310b)与金属线(第一金属线102a及第二金属线102b)为一体成形的。连接柱及金属线可为连续结构。在另一些实施例中,连接柱及金属线为分开形成的。连接柱及第金属线可为独立的组件。此外,连接柱(第三连接柱310a及第四连接柱310b)及导电层208可由相同或不同的材料形成。相似地,第二连接柱210b及金属线(第一金属线102a及第二金属线102b)可由相同或不同的材料形成。第三连接柱310a及第四连接柱310b可由相同或不同的材料形成。
在一些实施例中,第三连接柱310a及第四连接柱310b可各自由相同或不同导电材料形成。用于形成第三连接柱310a及第四连接柱310b的材料可包含铜、铝、钨、钛、金、银、钼、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、其它合适的导电材料或前述的组合,但不限于此。在一些实施例中,第三连接柱310a及第四连接柱310b可各自由具有较高熔化温度的导电材料形成。在一些实施例中,第三连接柱310a及第四连接柱310b可各自由熔化温度在约660℃至约3410℃范围内的导电材料形成。在一些实施例中,第三连接柱310a及第四连接柱310b可分别由与第三接垫304a及第四接垫304b的材料相比具有相对高的熔化温度的导电材料形成。在一些实施例中,第一金属线102a和第二金属线102b可分别由与第三接垫304a及第四接垫304b的材料相比具有相对高的熔化温度的导电材料形成。
此外,如同前述,第一连接柱210a与第二连接柱210b彼此分离距离D1。在一些实施例中,第一连接柱210a与第二连接柱210b之间的距离D1在约1μm至约200μm的范围内,或约2μm至约50μm的范围内。如图10所示,第三连接柱310a与第四连接柱310b彼此分开距离D2。在一些实施例中,第三连接柱310a与第四连接柱310b之间的距离D2在约3μm至约600μm的范围内,或约6μm至约150μm的范围内。在一些实施例中,第三连接柱310a与第四连接柱310b之间的距离D2大于第一连接柱210a与第二连接柱210b之间的距离D1。此外,在一些实施例中,第三连接柱310a在垂直于第二基板300的法线方向(例如,Y方向)上的宽度W2可大于第一连接柱210a在Y方向上的宽度W1。在一些实施例中,第四连接柱310b的宽度或尺寸可大于第二连接柱210b的宽度或尺寸。
此外,在一些实施例中,第三连接柱310a及第四连接柱310b的熔化温度分别高于第三接垫304a及第四接垫304b的熔化温度。在一些实施例中,第一金属线102a、第二金属线102b、第三金属线302a及第四金属线302b的熔化温度高于第一接垫104a及第二接垫104b的熔化温度。具体而言,在一些实施例中,金属线的熔化温度与接垫的熔融温度的比值在约1.5至约35的范围内,或约1.5至约17的范围内。应注意的是,金属线的熔化温度与接垫的熔化温度的比值不应过小,否则金属线可能会在加热过程中熔化或变形,而造成金属线损坏的风险。此外,金属线的熔化温度与接垫的熔化温度的比值不应过大,否则金属线的膨胀系数与接垫的膨胀系数的差异可能过大,而使得金属线与接垫彼此剥离。
如同前述,第三接垫304a及第四接垫304b可由与金属线的材料相比具有较低的熔化温度的导电材料形成。用于形成接垫的具有较低熔化温度的导电材料可包含焊料、锡、铟、镓、锡合金、铟合金、镓合金、镓-铟合金或前述的组合,但不限于此。第三连接柱310a及第四连接柱310b可由与接垫的材料相比具有较高的熔化温度的导电材料形成。用于形成连接柱的具有较高熔化温度的导电材料可包含铜、铝、钨、钛、金、银、钼、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、其它合适的导电材料或前述的组合,但不限于此。此外,第三金属线302a及第四金属线302b亦可由与接垫的材料相比具有较高的熔化温度的导电材料形成。用于形成,第三金属线302a及第四金属线302b的具有较高熔化温度的导电材料可包含铜、铝、钨、钛、金、银、钼、铜合金、铝合金、钨合金、钛合金、金合金、银合金、钼合金、其它合适的导电材料或前述的组合,但不限于此。
显示设备80更包含设置于第一基板100及第二基板300之间的粘着层314。粘着层314将第一基板100与第二基板300粘合在一起,并使第三连接柱310a及第四连接柱310b分别与第二基板300上的第三接垫304a及第四接垫304b保持实体接触。粘着层314可由粘着材料形成。在一些实施例中,粘着层314可为绝缘体。在一些实施例中,粘着层314的材料可包含热固化粘着剂、光固化粘着剂或前述的组合,但不限于此。光固化粘着剂可包含UV光固化粘着剂或可见光固化粘着剂。此外,粘着层314的材料可与粘着层214的材料相同或不同。
接着,请参照图11A~11C,图11A~11C显示根据本发明一些实施例中,电子装置转移至目标基板的步骤的示意图。如图11A所示,第一基板100可包含形成于其上的多个电子装置200。应理解的是,虽然图11A仅绘示电子装置200,但实际上第一基板100可包含形成于其上的各种组件(例如,如图10所示)。在此实施例中,第一基板100作为中间基板,以先聚集如电子装置200等的各种组件,然后将这些组件转移至第二基板300(例如,目标基板)。在一些实施例中,电子装置200可为发射红光、绿光、蓝光或前述的组合的微型LED。
在另一些实施例中,可将一个以上的中间基板转移至第二基板300,且中间基板可承载不同的电子装置。例如,如图11A~11C所示,第一基板100、100’及100”可分别承载不同的电子装置200、200’及200”,且电子装置200、200’及200”可先整合于第二基板300上,形成集成电子组件。接着,可将包含集成电子组件的第二基板300转移至另一个目标基板。在一些实施例中,电子装置200、200’及200”可分别为发射红光、绿光及蓝光的微型LED。如同前述,小型电子装置可先集成于中间基板上,然后承载集成小型电子装置的中间基板可被转移至目标基板(例如,显示设备的阵列基板)。因此,相较于逐一转移小型电子装置的方式,借由中间基板进行小型电子装置的转移可大幅减少所需的时间。
综上所述,本发明提供一种用于改善尺寸较小的电子装置(例如,次毫米LED、微型LED、有机LED、非有机LED(例如:量子点LED)或集成电子组件等)与尺寸较大的目标基板(例如,阵列基板)之间的电性连接效率的结构。本发明提供的显示设备包含连接柱,其可稳固地埋置于目标基板的导电组件(例如,用于相互连接的接垫)中。因此,可维持电子装置对目标基板上的电路***的有效电性连接。此外,根据本发明的一些实施例,显示设备中的中间基板的设置可减少将小型电子装置转移至目标基板所需的时间。
虽然本发明的实施例及其优点已揭露如上,但应该了解的是,任何所属技术领域中的技术人员,在不脱离本发明的精神和范围内,当可作更动、替代与润饰。此外,本发明的保护范围并未局限于说明书内所述特定实施例中的制程、机器、制造、物质组成、装置、方法及步骤,任何所属技术领域中的技术人员可从本发明揭示内容中理解现行或未来所发展出的制程、机器、制造、物质组成、装置、方法及步骤,只要可以在此处所述实施例中实施大抵相同功能或获得大抵相同结果皆可根据本发明使用。因此,本发明的保护范围包括上述制程、机器、制造、物质组成、装置、方法及步骤。另外,每一权利要求构成个别的实施例,且本发明的保护范围也包括各个权利要求及实施例的组合。本发明的保护范围当以权利要求所界定者为准。
Claims (19)
1.一种显示设备,其特征在于,包括:
一基板,具有一法线方向(X);
一第一金属线及一第二金属线,设置于所述基板上;
一第一接垫及一第二接垫,设置于所述基板上且分别与所述第一金属线及所述第二金属线电性连接,其中在该法线方向上,所述第一接垫仅与所述第一金属线的一端重叠,且所述第二接垫仅与所述第二金属线的一端重叠;以及
一电子装置,设置于所述第一接垫及所述第二接垫上,且所述电子装置包括一第一连接柱及一第二连接柱;
其中所述第一连接柱与所述第二连接柱之间的距离介于1μm至200μm的范围内,以及其中所述第一连接柱的一部分埋置于所述第一接垫中,所述第二连接柱的一部分埋置于所述第二接垫中。
2.如权利要求1所述的显示设备,其特征在于,所述第一金属线的熔化温度高于所述第一接垫的熔化温度。
3.如权利要求2所述的显示设备,其特征在于,所述第一金属线的熔化温度与所述第一接垫的熔化温度的一比值介于1.5至35的范围内。
4.如权利要求3所述的显示设备,其特征在于,所述比值介于1.5至17的范围内。
5.如权利要求1所述的显示设备,其特征在于,埋置于所述第一接垫中的所述第一连接柱的所述部分的高度与所述第一连接柱的高度的比值介于0.1至1的范围内。
6.如权利要求1所述的显示设备,其特征在于,所述第一连接柱与所述第二连接柱之间的距离介于2μm至50μm的范围内。
7.如权利要求1所述的显示设备,其特征在于,所述第一连接柱的熔化温度高于所述第一接垫的熔化温度。
8.如权利要求1所述的显示设备,其特征在于,所述第一接垫包括一凸起部分(bulgingportion),其位于埋置于所述第一接垫中的所述第一连接柱的周围。
9.如权利要求1所述的显示设备,其特征在于,更包括一粘着层,其设置于所述电子装置与所述基板之间。
10.如权利要求9所述的显示设备,其特征在于,所述粘着层包括一***部分(swellingportion),其位于埋置于所述第一接垫中的所述第一连接柱的周围。
11.如权利要求9所述的显示设备,其特征在于,所述粘着层覆盖所述第一接垫。
12.如权利要求9所述的显示设备,其特征在于,所述粘着层为一绝缘体。
13.一种显示设备,其特征在于,包括:
一集成电子组件,包括:
一第一基板,具有一法线方向(X);
一第一金属线及一第二金属线,设置于所述第一基板上;
一第一接垫及一第二接垫,设置于所述第一基板上且分别与所述第一金属线及所述第二金属线电性连接,其中在该法线方向上,所述第一接垫仅与所述第一金属线的一端重叠,且所述第二接垫仅与所述第二金属线的一端重叠;以及
一电子装置,设置于所述第一接垫及所述第二接垫上,且所述电子装置包括一第一连接柱及一第二连接柱,其中所述第一连接柱的一部分埋置于所述第一接垫中,所述第二连接柱的一部分埋置于所述第二接垫中;
一第二基板,设置于所述集成电子组件下方;以及
一第三接垫及一第四接垫,设置于所述第二基板上且分别与所述第一金属线及所述第二金属线电性连接;
其中所述第一金属线包括一第三连接柱且所述第二金属线包括一第四连接柱,以及其中所述第三连接柱与所述第四连接柱分别与所述第三接垫与所述第四接垫电性连接。
14.如权利要求13所述的显示设备,其特征在于,所述第三连接柱与所述第四连接柱之间的距离大于所述第一连接柱与所述第二连接柱之间的距离。
15.如权利要求13所述的显示设备,其特征在于,所述第三接垫的面积大于所述第一接垫的面积。
16.如权利要求13所述的显示设备,其特征在于,所述第一金属线的熔化温度高于所述第三接垫的熔化温度。
17.如权利要求13所述的显示设备,其特征在于,所述第三连接柱的熔化温度高于所述第三接垫的熔化温度。
18.如权利要求13所述的显示设备,其特征在于,所述第一接垫的厚度大于所述第一金属线的厚度。
19.如权利要求13所述的显示设备,其特征在于,所述第三连接柱的一部分埋置于所述第三接垫中,且所述第四连接柱的一部分埋置于所述第四接垫中。
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US6172422B1 (en) * | 1996-07-11 | 2001-01-09 | Pfu Limited | Semiconductor device and a manufacturing method thereof |
TW201735320A (zh) * | 2016-03-03 | 2017-10-01 | 艾克斯瑟樂普林特有限公司 | 微轉移可印刷電子元件 |
TW201735482A (zh) * | 2016-03-30 | 2017-10-01 | 英特爾公司 | 可表面安裝之電力輸送匯電板 |
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US10446729B1 (en) | 2019-10-15 |
EP3542948A1 (en) | 2019-09-25 |
KR102608656B1 (ko) | 2023-11-30 |
CN110299376A (zh) | 2019-10-01 |
US20190296202A1 (en) | 2019-09-26 |
CN115332286A (zh) | 2022-11-11 |
KR20230163999A (ko) | 2023-12-01 |
KR20190111703A (ko) | 2019-10-02 |
US20190386193A1 (en) | 2019-12-19 |
US11114597B2 (en) | 2021-09-07 |
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