CN110223648B - Driving circuit for display screen - Google Patents
Driving circuit for display screen Download PDFInfo
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- CN110223648B CN110223648B CN201910382521.0A CN201910382521A CN110223648B CN 110223648 B CN110223648 B CN 110223648B CN 201910382521 A CN201910382521 A CN 201910382521A CN 110223648 B CN110223648 B CN 110223648B
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- film transistor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a driving circuit for a display screen, which includes: the pull-up unit is used for converting a clock signal into a stage transmission signal and converting a direct current voltage signal into an output signal; a pull-up control unit for controlling an opening time of the pull-up unit; the bootstrap capacitor is used for lifting the stage transfer signal and outputting a signal voltage; the pull-down unit is used for pulling down the output voltage of the bootstrap capacitor to a low potential; a pull-down maintaining unit for maintaining an output voltage of the bootstrap capacitor at a low potential; the inverter is used for enabling the output voltage of the bootstrap capacitor and the output voltage potential of the pull-down maintaining unit to be opposite; and the feedback unit is used for improving the output voltage of the pull-down unit.
Description
Technical Field
The invention relates to the field of electronic display, in particular to a driving circuit for a display screen.
Background
The response time of the blue phase liquid crystal is in the sub-millimeter level. Compared with other types of displays, the display applying the blue phase liquid crystal has the advantages of simple preparation process, wide viewing angle and quick response time. However, the driving voltage of the blue phase liquid crystal is relatively high (greater than 30V), and the driving voltage output by the driving circuit matched with the driving voltage is relatively high. The potential of the output signal of the driving circuit is determined by the potentials of the clock signal and the trigger signal, and the increase of the potential of the clock signal can greatly increase the power consumption of the driving circuit and the crosstalk between signals.
Disclosure of Invention
The invention provides a driving circuit for a display screen, which can greatly reduce the power consumption of the driving circuit and reduce the crosstalk between signals.
To solve the above problems, the present invention provides a driving circuit for a display panel, comprising:
the pull-up unit is used for converting a clock signal into a stage transmission signal and converting a direct current voltage signal into an output signal;
a pull-up control unit for controlling an opening time of the pull-up unit;
the bootstrap capacitor is used for lifting the stage transfer signal and outputting a signal voltage;
the pull-down unit is used for pulling down the output voltage of the bootstrap capacitor to a low potential;
a pull-down maintaining unit for maintaining an output voltage of the bootstrap capacitor at a low potential;
the inverter is used for enabling the output voltage of the bootstrap capacitor and the output voltage potential of the pull-down maintaining unit to be opposite; and
and the feedback unit is used for improving the output voltage of the pull-down unit.
According to one aspect of the present invention, the pull-up unit includes a first pull-up unit and a second pull-up unit;
the first pull-up unit comprises a first pull-up thin film transistor, a second pull-up thin film transistor and a third pull-up thin film transistor; wherein the content of the first and second substances,
the source electrode of the first pull-up thin film transistor is connected with a first direct-current voltage, the drain electrode of the first pull-up thin film transistor is connected with the pull-down unit, and the grid electrode of the first pull-up thin film transistor is connected with the grid electrode of the second pull-up thin film transistor and the drain electrode of the third pull-up thin film transistor;
the source electrode of the second pull-up thin film transistor is connected with a first direct current voltage, and the drain electrode of the second pull-up thin film transistor is connected with one polar plate of the bootstrap capacitor;
the source electrode of the third pull-up thin film transistor is connected with a second direct current voltage, the grid electrode of the third pull-up thin film transistor is connected with a primary level transmission signal, and the drain electrode of the third pull-up thin film transistor is connected with the other electrode plate of the bootstrap capacitor;
the second pull-up unit comprises a fourth pull-up thin film transistor, a source electrode of the fourth pull-up thin film transistor is connected with a second clock signal, a grid electrode of the fourth pull-up thin film transistor is connected with the bootstrap capacitor, and a drain electrode of the fourth pull-up thin film transistor is connected with a third direct current voltage.
According to one aspect of the present invention, the first pull-up thin film transistor and the third pull-up thin film transistor are N-type thin film transistors, and the second pull-up thin film transistor and the fourth pull-up thin film transistor are P-type thin film transistors.
According to one aspect of the present invention, the pull-up control unit includes a first control thin film transistor and a second control thin film transistor; wherein the content of the first and second substances,
the source electrode of the first control thin film transistor is connected with a first-stage transmission signal, the grid electrode of the first control thin film transistor is connected with a first clock signal, and the drain electrode of the first control thin film transistor is connected with the source electrode of the second control thin film transistor;
and the grid electrode of the second control thin film transistor is connected with the first clock signal, and the drain electrode of the second control thin film transistor is connected with the pull-down maintaining unit.
According to one aspect of the present invention, the first control thin film transistor and the second control thin film transistor are N-type thin film transistors.
According to one aspect of the present invention, the pull-down unit includes a first pull-down unit and a second pull-down unit; wherein the content of the first and second substances,
the first pull-down unit comprises a first pull-down thin film transistor, the source electrode of the first pull-down thin film transistor is connected with the first pull-up unit, the grid electrode of the first pull-down thin film transistor is connected with a next-stage level transmission signal, and the drain electrode of the first pull-down thin film transistor is connected with the third direct-current voltage;
the second pull-down unit comprises a second pull-down thin film transistor and a third pull-down thin film transistor;
the source electrode of the second pull-down thin film transistor is connected with the bootstrap capacitor, the grid electrode of the second pull-down thin film transistor is connected with a next-stage level transmission signal, and the drain electrode of the second pull-down thin film transistor is connected with the source electrode of the third pull-down thin film transistor;
and the grid electrode of the third pull-down thin film transistor is connected with a next-stage transmission signal, and the drain electrode of the third pull-down thin film transistor is connected with the third direct current voltage.
According to one aspect of the present invention, the first pull-down thin film transistor and the third pull-down thin film transistor are N-type thin film transistors, and the second pull-down thin film transistor is a P-type thin film transistor.
According to one aspect of the present invention, the pull-down maintaining unit includes a first pull-down maintaining unit and a second pull-down maintaining unit; wherein the content of the first and second substances,
the first pull-down maintaining unit comprises a first maintaining thin film transistor, a second maintaining thin film transistor and a third maintaining thin film transistor;
the source electrode of the first maintaining thin film transistor is connected with the first pull-up unit, the grid electrode of the first maintaining thin film transistor is connected with the grid electrode of the second maintaining thin film transistor, and the drain electrode of the first maintaining thin film transistor is connected with the third direct current voltage;
the source electrode of the second maintaining thin film transistor is connected with the second pull-up unit, and the drain electrode of the second maintaining thin film transistor is connected with the third direct current voltage;
the source electrode of the third holding thin film transistor is connected with the bootstrap capacitor, and the drain electrode of the third holding thin film transistor is connected with the third direct current voltage;
the second pull-down maintaining unit comprises a fifth maintaining thin film transistor and a sixth maintaining thin film transistor;
the source electrode of the fifth maintaining thin film transistor is connected with the pull-up control unit, the grid electrode of the fifth maintaining thin film transistor is connected with the phase inverter, and the drain electrode of the fifth maintaining thin film transistor is connected with the source electrode of the sixth maintaining thin film transistor;
and the grid electrode of the sixth maintaining thin film transistor is connected with the phase inverter, and the drain electrode of the sixth maintaining thin film transistor is connected with the third direct current voltage.
According to one aspect of the present invention, the first and third, fifth and sixth sustain thin film transistors are N-type thin film transistors, and the second sustain thin film transistor is a P-type thin film transistor.
According to one aspect of the present invention, the inverter includes a first inverter and a second inverter; wherein the content of the first and second substances,
the first inverter comprises a first reverse thin film transistor, a second reverse thin film transistor, a third reverse thin film transistor and a fourth reverse thin film transistor;
the source electrode and the grid electrode of the first reverse thin film transistor are connected with the second pull-down unit, and the drain electrode of the first reverse thin film transistor is connected with the source electrode of the second reverse thin film transistor;
the grid electrode of the second reverse thin film transistor is connected with the second pull-down unit, and the drain electrode of the second reverse thin film transistor is connected with the third direct current voltage;
the source electrode of the third reverse thin film transistor is connected with the second pull-down unit, the grid electrode of the third reverse thin film transistor is connected with the drain electrode of the first reverse thin film transistor, and the drain electrode of the third reverse thin film transistor is connected with the source electrode of the fourth reverse thin film transistor;
the grid electrode of the fourth reverse thin film transistor is connected with the grid electrode of the second reverse thin film transistor, and the drain electrode of the fourth reverse thin film transistor is connected with the third direct-current voltage;
the second inverter comprises a fifth reverse thin film transistor, a sixth reverse thin film transistor, a seventh reverse thin film transistor and an eighth reverse thin film transistor;
the grid electrode and the source electrode of the fifth reverse thin film transistor are connected with the feedback unit, and the drain electrode of the fifth reverse thin film transistor is connected with the source electrode of the sixth reverse thin film transistor;
the grid electrode of the sixth reverse thin film transistor is connected with the second pull-up unit, and the drain electrode of the sixth reverse thin film transistor is connected with the third direct current voltage;
the source electrode of the seventh reverse thin film transistor is connected with the feedback unit, the grid electrode of the seventh reverse thin film transistor is connected with the drain electrode of the fifth reverse thin film transistor, and the drain electrode of the seventh reverse thin film transistor is connected with the source electrode of the eighth reverse thin film transistor;
and the grid electrode of the eighth reverse thin film transistor is connected with the grid electrode of the sixth reverse thin film transistor, and the drain electrode of the eighth reverse thin film transistor is connected with the third direct current voltage.
According to one aspect of the present invention, the first, third, fourth, fifth, seventh and eighth inversion thin film transistors are N-type thin film transistors; the second reverse thin film transistor and the sixth reverse thin film transistor are P-type thin film transistors.
According to one aspect of the present invention, the feedback unit includes a feedback thin film transistor, a source of the feedback thin film transistor is connected to the first pull-up unit, a drain of the feedback thin film transistor is connected to the pull-up control unit, and a gate of the feedback thin film transistor is connected to the stage signal of the present stage.
According to one aspect of the invention, the feedback thin film transistor is an N-type thin film transistor.
According to one aspect of the present invention, the bootstrap capacitor includes a first storage capacitor and a second storage capacitor; wherein the content of the first and second substances,
one polar plate of the first storage capacitor is connected with the first pull-up unit, and the other polar plate of the first storage capacitor is connected with the pull-down maintaining unit;
one polar plate of the second storage capacitor is connected with the second pull-up unit, and the other polar plate of the second storage capacitor is connected with the second pull-down unit.
The driving circuit provided by the invention can raise the voltage of the clock signal, so that the driving circuit outputs high voltage for driving the blue phase liquid crystal while keeping the voltage signal of the internal node at a lower voltage value, the power consumption of the driving circuit can be greatly reduced, and the crosstalk between signals is reduced.
Drawings
FIG. 1 is a circuit diagram of a driver circuit in an embodiment of the invention;
FIG. 2 is a timing diagram of driving signals in the driving circuit of FIG. 1;
fig. 3 is a diagram illustrating simulation results of a driving circuit according to an embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The present invention provides a driving circuit for a display screen, as shown in fig. 1, which includes: the pull-up unit M2, the pull-up unit M2 is used for converting the clock signal into a stage transmission signal and converting the direct current voltage signal into an output signal; a pull-up control unit M1, the pull-up control unit M1 is used for controlling the opening time of the pull-up unit M2; the bootstrap capacitor is used for lifting the stage transfer signal and outputting a signal voltage; a pull-down unit M3, the pull-down unit M3 is used for pulling down the output voltage of the bootstrap capacitor to a low potential; a pull-down maintaining unit M4, the pull-down maintaining unit M4 is used for pulling the output voltage of the bootstrap capacitor to low level; an inverter M5, the inverter M5 is used for making the output voltage of the bootstrap capacitor and the output voltage potential of the pull-down maintaining unit M4 opposite; and a feedback unit M6 for increasing the output voltage of the pull-down unit M3 by the feedback unit M6.
The pull-up unit M2 includes a first pull-up unit M21 and a second pull-up unit M22. the first pull-up unit M21 includes a first pull-up thin film transistor T21, a second pull-up thin film transistor T22 and a third pull-up thin film transistor T23. the first pull-up thin film transistor T21 has a source connected to a first dc voltage VDD, a drain connected to the pull-down unit M3, a gate connected to a gate of the second pull-up thin film transistor T22 and a drain of the third pull-up thin film transistor T23. the second pull-up thin film transistor T22 has a source connected to the first dc voltage VDD and a drain connected to one plate of the bootstrap capacitor.
Preferably, the first pull-up thin film transistor T21 and the third pull-up thin film transistor T23 are N-type thin film transistors, and the second pull-up thin film transistor T22 and the fourth pull-up thin film transistor T24 are P-type thin film transistors.
The pull-up control unit M1 includes a first control thin film transistor T11 and a second control thin film transistor T12. The source of the first control thin film transistor T11 is connected to a first-level pass signal, the gate is connected to a first clock signal, and the drain is connected to the source of the second control thin film transistor T12; the gate of the second control thin film transistor T12 is connected to the first clock signal, and the drain is connected to the pull-down sustain unit M4.
The first and second control thin film transistors T11 and T12 are N-type thin film transistors.
The pull-down unit M3 includes a first pull-down unit M31 and a second pull-down unit M32, wherein the first pull-down unit M31 includes a first pull-down thin film transistor T31, a source of the first pull-down thin film transistor T31 is connected to the first pull-up unit M21, a gate is connected to a stage signal of a next stage, and a drain is connected to the third dc voltage VG L, the second pull-down unit M32 includes a second pull-down thin film transistor T32 and a third pull-down thin film transistor T33, a source of the second pull-down thin film transistor T32 is connected to the bootstrap capacitor, a gate is connected to a stage signal of a next stage, a drain is connected to a source of the third pull-down thin film transistor T33, a gate of the third pull-down thin film transistor T33 is connected to a stage signal of a next stage, and a drain is connected to the third dc voltage VG L.
Preferably, the first pull-down thin film transistor T31 and the third pull-down thin film transistor T33 are N-type thin film transistors, and the second pull-down thin film transistor T32 is a P-type thin film transistor.
The pull-down maintaining unit M4 includes a first pull-down maintaining unit M41 and a second pull-down maintaining unit M42. the first pull-down maintaining unit M41 includes a first maintaining thin film transistor T41, a second maintaining thin film transistor T42 and a third maintaining thin film transistor T43. the first maintaining thin film transistor T41 has a source connected to the first pull-up unit M21, a gate connected to the gate of the second maintaining thin film transistor T42, and a drain connected to the third direct current voltage VG L. the second maintaining thin film transistor T42 has a source connected to the second pull-up unit M22, a drain connected to the third direct current voltage VG L. the third maintaining thin film transistor T43 has a source connected to the bootstrap capacitor, a drain connected to the third direct current voltage VG L. the second pull-down maintaining unit M42 includes a fifth maintaining thin film transistor T45 and a sixth maintaining thin film transistor T46. the fifth maintaining thin film transistor T5 has a source connected to the pull-up controlling thin film transistor M1, a drain connected to the gate of the sixth maintaining thin film transistor T46. the drain of the maintaining thin film transistor T599 is connected to the gate of the sixth maintaining thin film transistor T599.
Preferably, the first and third sustain thin film transistors T41 and T43, the fifth and sixth sustain thin film transistors T45 and T46 are N-type thin film transistors, and the second sustain thin film transistor T42 is a P-type thin film transistor.
The inverter M5 includes a first inverter M51 and a second inverter M52.
The first inverter M51 includes a first reverse thin film transistor T51, a second reverse thin film transistor T52, a third reverse thin film transistor T53 and a fourth reverse thin film transistor T54. the source and the gate of the first reverse thin film transistor T51 are connected to the second pull-down unit M32, and the drain is connected to the source of the second reverse thin film transistor T52. the gate of the second reverse thin film transistor T52 is connected to the second pull-down unit M32, and the drain is connected to the third direct current voltage VG L. the source of the third reverse thin film transistor T53 is connected to the second pull-down unit M32, the gate is connected to the drain of the first reverse thin film transistor T51, the drain is connected to the source of the fourth reverse thin film transistor T54. the gate of the fourth reverse thin film transistor T54 is connected to the gate of the second reverse thin film transistor T52, and the drain is connected to the third direct current voltage VG L.
The second inverter M52 includes a fifth reverse thin film transistor T55, a sixth reverse thin film transistor T56, a seventh reverse thin film transistor T57 and an eighth reverse thin film transistor T58. the gate and the source of the fifth reverse thin film transistor T55 are connected to the feedback unit M6, the drain is connected to the source of the sixth reverse thin film transistor T56. the gate of the sixth reverse thin film transistor T56 is connected to the second pull-up unit M22, the drain is connected to the third direct current voltage VG L. the source of the seventh reverse thin film transistor T57 is connected to the feedback unit M6, the gate is connected to the drain of the fifth reverse thin film transistor T55, the drain is connected to the source of the eighth reverse thin film transistor T58. the gate of the eighth reverse thin film transistor T58 is connected to the gate of the sixth reverse thin film transistor T56, and the drain is connected to the third direct current voltage VG L.
Preferably, the first, third, fourth, fifth, seventh and eighth reverse thin film transistors T51, T53, T54, T55, T57 and T58 are N-type thin film transistors; the second and sixth reverse thin film transistors T52 and T56 are P-type thin film transistors.
The feedback unit M6 includes a feedback thin film transistor T6, the source of the feedback thin film transistor T6 is connected to the first pull-up unit M21, the drain is connected to the pull-up control unit M1, and the gate is connected to the stage signal of the present stage. Preferably, the feedback thin film transistor T6 is an N-type thin film transistor.
The bootstrap capacitor includes a first storage capacitor Cbt1 and a second storage capacitor Cbt 2. One plate of the first storage capacitor Cbt1 is connected to the first pull-up unit M21, and the other plate is connected to the pull-down maintaining unit M4. One plate of the second storage capacitor Cbt2 is connected to the second pull-up unit M22, and the other plate is connected to the second pull-down unit M32.
The operation of the driving circuit of the present invention will be described in detail with reference to specific embodiments. Referring to fig. 2 and 3, fig. 2 is a timing diagram of driving signals in the driving circuit of fig. 1; fig. 3 is a diagram illustrating simulation results of a driving circuit according to an embodiment of the present invention.
Wherein CK1 is a first clock signal, CK2 is a second clock signal, and the waveforms of the first clock signal CK1 and the second clock signal CK2 are opposite. Cout (n) is the stage transmission signal of the present stage; COUT (n-1) is a stage transmission signal of the previous stage; cout (n +1) is a stage transmission signal of the next stage.
Referring to fig. 3, the duty cycle of the driving circuit in the present embodiment includes a first phase T1, a second phase T2, and a third phase T3.
In the first stage: when the first clock signal CK1 is at a high potential, the first control tft T11 and the second control tft T12 are turned on, COUT (n-1) is at a high potential, the potential of the Q point is raised to a high potential, the fourth pull-up tft T24, the second inversion tft T52 and the fourth inversion tft T54 are turned on, QB is pulled down to a low potential, the third sustain tft T43, the fourth sustain tft T44, the fifth sustain tft T45 and the sixth sustain tft T46 are turned off, since the second clock signal CK2 is at a low potential, the stage transmission signal COUT (n) of the present stage is at a low potential, the sixth inversion tft T56 and the eighth inversion tft T58 are turned off, the P point is pulled up to a high potential, the first sustain tft T41 and the second sustain tft T42 are turned on, the stage transmission signal COUT (n-1) of the upper stage is at a high potential, the third pull-up TFT T23 is turned on, the potential at M point is pulled to high potential, the first pull-up TFT T21 and the second pull-up TFT T22 are turned on, and the N point and the output signal G (N) are still maintained at low potential because the second sustain TFT T42 and the first sustain TFT T41 are turned on.
In the second stage: when the first clock signal CK1 is at a low potential, the first control tft T11 and the second control tft T12 are turned off, the fourth pull-up tft T24 is turned on, CK2 is turned to a high potential, and the stage signal cout (n) is turned to a high potential, so that the potential at the Q point is pulled up to a higher potential, which is favorable for turning on the fourth pull-up tft T24. Meanwhile, the feedback thin film transistor T6, the sixth reverse thin film transistor T56 and the eighth reverse thin film transistor T58 are turned on, and the point F is raised to a high potential, so that the leakage of the second control thin film transistor T12, the fifth maintaining thin film transistor T45 and the T32 is reduced, and the potential of a point Q is maintained. The point P drops to a low potential. The first sustain thin film transistor T41 and the second sustain thin film transistor T42 are turned off, and the N point is raised to a high potential. Due to the presence of the second storage capacitance Cbt2, the M-point potential is pulled up to a higher potential. The first pull-up TFT T21 and the second pull-up TFT T22 are turned on, and the potential at the N point and the output signal are gradually raised to the high potential.
In the third stage: the first clock signal CK1 rises to a high level, the first control tft T11 and the second control tft T12 are turned on, and the level of the Q point is pulled down to a low level because the level signal COUT (n-1) of the previous stage is at a low level. The fourth pull-up thin film transistor T24, the second reverse thin film transistor T52, and the fourth reverse thin film transistor T54 are turned off, and the QB point rises to a high potential. The third sustain thin film transistor T43, the fourth sustain thin film transistor T44, the fifth sustain thin film transistor T45, and the sixth sustain thin film transistor T46 are turned on, and the stage signal cout (n) is lowered to a low potential. The sixth and eighth inversion TFTs T56 and T58 and the feedback TFT T6 are turned off, and the point P is raised to a high potential. The first and second sustain tfts T41 and T42 are turned on, and the stage signal COUT (n +1) of the next stage is raised to a high potential. T31 turns on and the stage signaling goes low.
The driving circuit provided by the invention can raise the voltage of the clock signal, so that the driving circuit outputs high voltage for driving the blue phase liquid crystal while keeping the voltage signal of the internal node at a lower voltage value, the power consumption of the driving circuit can be greatly reduced, and the crosstalk between signals is reduced.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (13)
1. A driving circuit for a display screen, the driving circuit comprising:
the pull-up unit is used for converting a clock signal into a stage transmission signal and converting a direct current voltage signal into an output signal;
a pull-up control unit for controlling an opening time of the pull-up unit;
the bootstrap capacitor is used for lifting the stage transfer signal and outputting a signal voltage;
the pull-down unit is used for pulling down the output voltage of the bootstrap capacitor to a low potential;
a pull-down maintaining unit for maintaining an output voltage of the bootstrap capacitor at a low potential;
the inverter is used for enabling the output voltage of the bootstrap capacitor and the output voltage potential of the pull-down maintaining unit to be opposite; and
the feedback unit is used for increasing the output voltage of the pull-down unit;
the pull-up unit comprises a first pull-up unit and a second pull-up unit;
the first pull-up unit comprises a first pull-up thin film transistor, a second pull-up thin film transistor and a third pull-up thin film transistor; wherein the content of the first and second substances,
the source electrode of the first pull-up thin film transistor is connected with a first direct-current voltage, the drain electrode of the first pull-up thin film transistor is connected with the pull-down unit, and the grid electrode of the first pull-up thin film transistor is connected with the grid electrode of the second pull-up thin film transistor and the drain electrode of the third pull-up thin film transistor;
the source electrode of the second pull-up thin film transistor is connected with a first direct current voltage, and the drain electrode of the second pull-up thin film transistor is connected with one polar plate of the bootstrap capacitor;
the source electrode of the third pull-up thin film transistor is connected with a second direct current voltage, the grid electrode of the third pull-up thin film transistor is connected with a primary level transmission signal, and the drain electrode of the third pull-up thin film transistor is connected with the other electrode plate of the bootstrap capacitor;
the second pull-up unit comprises a fourth pull-up thin film transistor, a source electrode of the fourth pull-up thin film transistor is connected with a second clock signal, a grid electrode of the fourth pull-up thin film transistor is connected with the bootstrap capacitor, and a drain electrode of the fourth pull-up thin film transistor is connected with a third direct current voltage.
2. The driving circuit according to claim 1, wherein the first pull-up thin film transistor and the third pull-up thin film transistor are N-type thin film transistors, and the second pull-up thin film transistor and the fourth pull-up thin film transistor are P-type thin film transistors.
3. The driving circuit according to claim 1, wherein the pull-up control unit includes a first control thin film transistor and a second control thin film transistor; wherein the content of the first and second substances,
the source electrode of the first control thin film transistor is connected with a first-stage transmission signal, the grid electrode of the first control thin film transistor is connected with a first clock signal, and the drain electrode of the first control thin film transistor is connected with the source electrode of the second control thin film transistor;
and the grid electrode of the second control thin film transistor is connected with the first clock signal, and the drain electrode of the second control thin film transistor is connected with the pull-down maintaining unit.
4. The driving circuit according to claim 3, wherein the first and second control thin film transistors are N-type thin film transistors.
5. The driving circuit according to claim 3, wherein the pull-down unit comprises a first pull-down unit and a second pull-down unit; wherein the content of the first and second substances,
the first pull-down unit comprises a first pull-down thin film transistor, the source electrode of the first pull-down thin film transistor is connected with the first pull-up unit, the grid electrode of the first pull-down thin film transistor is connected with a next-stage level transmission signal, and the drain electrode of the first pull-down thin film transistor is connected with the third direct-current voltage;
the second pull-down unit comprises a second pull-down thin film transistor and a third pull-down thin film transistor;
the source electrode of the second pull-down thin film transistor is connected with the bootstrap capacitor, the grid electrode of the second pull-down thin film transistor is connected with a next-stage level transmission signal, and the drain electrode of the second pull-down thin film transistor is connected with the source electrode of the third pull-down thin film transistor;
and the grid electrode of the third pull-down thin film transistor is connected with a next-stage transmission signal, and the drain electrode of the third pull-down thin film transistor is connected with the third direct current voltage.
6. The driving circuit according to claim 5, wherein the first pull-down thin film transistor and the third pull-down thin film transistor are N-type thin film transistors, and the second pull-down thin film transistor is a P-type thin film transistor.
7. The driving circuit according to claim 5, wherein the pull-down sustain unit comprises a first pull-down sustain unit and a second pull-down sustain unit; wherein the content of the first and second substances,
the first pull-down maintaining unit comprises a first maintaining thin film transistor, a second maintaining thin film transistor and a third maintaining thin film transistor;
the source electrode of the first maintaining thin film transistor is connected with the first pull-up unit, the grid electrode of the first maintaining thin film transistor is connected with the grid electrode of the second maintaining thin film transistor, and the drain electrode of the first maintaining thin film transistor is connected with the third direct current voltage;
the source electrode of the second maintaining thin film transistor is connected with the second pull-up unit, and the drain electrode of the second maintaining thin film transistor is connected with the third direct current voltage;
the source electrode of the third holding thin film transistor is connected with the bootstrap capacitor, and the drain electrode of the third holding thin film transistor is connected with the third direct current voltage;
the second pull-down maintaining unit comprises a fifth maintaining thin film transistor and a sixth maintaining thin film transistor;
the source electrode of the fifth maintaining thin film transistor is connected with the pull-up control unit, the grid electrode of the fifth maintaining thin film transistor is connected with the phase inverter, and the drain electrode of the fifth maintaining thin film transistor is connected with the source electrode of the sixth maintaining thin film transistor;
and the grid electrode of the sixth maintaining thin film transistor is connected with the phase inverter, and the drain electrode of the sixth maintaining thin film transistor is connected with the third direct current voltage.
8. The driving circuit according to claim 7, wherein the first and third sustain thin film transistors, the fifth sustain thin film transistor, and the sixth sustain thin film transistor are N-type thin film transistors, and the second sustain thin film transistor is a P-type thin film transistor.
9. The driving circuit according to claim 7, wherein the inverter includes a first inverter and a second inverter; wherein the content of the first and second substances,
the first inverter comprises a first reverse thin film transistor, a second reverse thin film transistor, a third reverse thin film transistor and a fourth reverse thin film transistor;
the source electrode and the grid electrode of the first reverse thin film transistor are connected with the second pull-down unit, and the drain electrode of the first reverse thin film transistor is connected with the source electrode of the second reverse thin film transistor;
the grid electrode of the second reverse thin film transistor is connected with the second pull-down unit, and the drain electrode of the second reverse thin film transistor is connected with the third direct current voltage;
the source electrode of the third reverse thin film transistor is connected with the second pull-down unit, the grid electrode of the third reverse thin film transistor is connected with the drain electrode of the first reverse thin film transistor, and the drain electrode of the third reverse thin film transistor is connected with the source electrode of the fourth reverse thin film transistor;
the grid electrode of the fourth reverse thin film transistor is connected with the grid electrode of the second reverse thin film transistor, and the drain electrode of the fourth reverse thin film transistor is connected with the third direct-current voltage;
the second inverter comprises a fifth reverse thin film transistor, a sixth reverse thin film transistor, a seventh reverse thin film transistor and an eighth reverse thin film transistor;
the grid electrode and the source electrode of the fifth reverse thin film transistor are connected with the feedback unit, and the drain electrode of the fifth reverse thin film transistor is connected with the source electrode of the sixth reverse thin film transistor;
the grid electrode of the sixth reverse thin film transistor is connected with the second pull-up unit, and the drain electrode of the sixth reverse thin film transistor is connected with the third direct current voltage;
the source electrode of the seventh reverse thin film transistor is connected with the feedback unit, the grid electrode of the seventh reverse thin film transistor is connected with the drain electrode of the fifth reverse thin film transistor, and the drain electrode of the seventh reverse thin film transistor is connected with the source electrode of the eighth reverse thin film transistor;
and the grid electrode of the eighth reverse thin film transistor is connected with the grid electrode of the sixth reverse thin film transistor, and the drain electrode of the eighth reverse thin film transistor is connected with the third direct current voltage.
10. The driving circuit according to claim 9, wherein the first, third, fourth, fifth, seventh and eighth inversion thin film transistors are N-type thin film transistors; the second reverse thin film transistor and the sixth reverse thin film transistor are P-type thin film transistors.
11. The driving circuit according to claim 9, wherein the feedback unit comprises a feedback thin film transistor, a source of the feedback thin film transistor is connected to the first pull-up unit, a drain of the feedback thin film transistor is connected to the pull-up control unit, and a gate of the feedback thin film transistor is connected to the stage signal of the current stage.
12. The driving circuit of claim 9, wherein the feedback thin film transistor is an N-type thin film transistor.
13. The driver circuit according to claim 11, wherein the bootstrap capacitor includes a first storage capacitor and a second storage capacitor; wherein the content of the first and second substances,
one polar plate of the first storage capacitor is connected with the first pull-up unit, and the other polar plate of the first storage capacitor is connected with the pull-down maintaining unit;
one polar plate of the second storage capacitor is connected with the second pull-up unit, and the other polar plate of the second storage capacitor is connected with the second pull-down unit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910382521.0A CN110223648B (en) | 2019-05-09 | 2019-05-09 | Driving circuit for display screen |
| PCT/CN2019/102963 WO2020224110A1 (en) | 2019-05-09 | 2019-08-28 | Driving circuit for display screen |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910382521.0A CN110223648B (en) | 2019-05-09 | 2019-05-09 | Driving circuit for display screen |
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| CN110223648B true CN110223648B (en) | 2020-07-10 |
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| CN111192550B (en) * | 2020-02-26 | 2021-05-07 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105528983A (en) * | 2016-01-25 | 2016-04-27 | 武汉华星光电技术有限公司 | Scanning drive circuit and plane display device having the same |
| CN107393473A (en) * | 2017-08-25 | 2017-11-24 | 深圳市华星光电半导体显示技术有限公司 | GOA circuits |
| KR20180057975A (en) * | 2016-11-23 | 2018-05-31 | 엘지디스플레이 주식회사 | Shift resister, image display device containing the same and method of driving the same |
| CN108932933A (en) * | 2017-05-27 | 2018-12-04 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display device |
| CN208433206U (en) * | 2018-07-27 | 2019-01-25 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| CN109712552A (en) * | 2019-02-12 | 2019-05-03 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9934749B2 (en) * | 2014-07-18 | 2018-04-03 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Complementary gate driver on array circuit employed for panel display |
| CN104409057B (en) * | 2014-11-14 | 2017-09-29 | 深圳市华星光电技术有限公司 | A kind of scan drive circuit |
| US9490780B2 (en) * | 2014-12-18 | 2016-11-08 | Intel Corporation | Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors |
| CN105139816B (en) * | 2015-09-24 | 2017-12-19 | 深圳市华星光电技术有限公司 | Gate driving circuit |
| CN107978290A (en) * | 2017-12-26 | 2018-05-01 | 深圳市华星光电技术有限公司 | A kind of gate drivers and drive circuit |
| CN108962166A (en) * | 2018-07-23 | 2018-12-07 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display device with the GOA circuit |
| CN109637423A (en) * | 2019-01-21 | 2019-04-16 | 深圳市华星光电半导体显示技术有限公司 | GOA device and gate driving circuit |
-
2019
- 2019-05-09 CN CN201910382521.0A patent/CN110223648B/en active Active
- 2019-08-28 WO PCT/CN2019/102963 patent/WO2020224110A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105528983A (en) * | 2016-01-25 | 2016-04-27 | 武汉华星光电技术有限公司 | Scanning drive circuit and plane display device having the same |
| KR20180057975A (en) * | 2016-11-23 | 2018-05-31 | 엘지디스플레이 주식회사 | Shift resister, image display device containing the same and method of driving the same |
| CN108932933A (en) * | 2017-05-27 | 2018-12-04 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display device |
| CN107393473A (en) * | 2017-08-25 | 2017-11-24 | 深圳市华星光电半导体显示技术有限公司 | GOA circuits |
| CN208433206U (en) * | 2018-07-27 | 2019-01-25 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| CN109712552A (en) * | 2019-02-12 | 2019-05-03 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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| Publication number | Publication date |
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| CN110223648A (en) | 2019-09-10 |
| WO2020224110A1 (en) | 2020-11-12 |
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