CN110222001B - Feedback control system and feedback control method based on PXIe chassis - Google Patents

Feedback control system and feedback control method based on PXIe chassis Download PDF

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CN110222001B
CN110222001B CN201910421531.0A CN201910421531A CN110222001B CN 110222001 B CN110222001 B CN 110222001B CN 201910421531 A CN201910421531 A CN 201910421531A CN 110222001 B CN110222001 B CN 110222001B
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chassis
feedback control
control module
pxie
sub
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CN110222001A (en
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郭成
梁福田
邓辉
龚明
吴玉林
彭承志
朱晓波
潘建伟
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University of Science and Technology of China USTC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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Abstract

The invention discloses a feedback control system and a feedback control method based on a PXIe chassis, wherein the system comprises: a main control case, wherein the main control case is a PXIe case; the plurality of PXIe sub-chassis are cascaded with the main control chassis in one stage and/or cascaded in multiple stages; the reading control module is inserted into a common PXIe slot of the chassis and used for completing signal acquisition or signal generation; the feedback control module is inserted into the timing slot of the chassis and used for collecting/fanning out data and executing a feedback algorithm; and the fan-out module is arranged between the main control machine case and each sub machine case, so that the synchronization between the main control machine case and each sub machine case is realized. The PXIe read control modules in the case realize feedback information exchange through the feedback control modules; the main control case and each sub case are connected through a data cascade interface on the feedback control module. The feedback control system and the feedback control method based on the PXIe case can realize sub microsecond feedback time and flexible expansion of the sub case.

Description

Feedback control system and feedback control method based on PXIe chassis
Technical Field
The invention belongs to the field of automatic control and quantum information regulation and control, and particularly relates to a feedback control system and a feedback control method based on a PXIe chassis.
Background
In the field of superconducting quantum computing, the coherence time of a quantum bit is very short, only tens of microseconds, and the decoherence of the quantum bit can cause the damage of a quantum state. To eliminate the effects of decoherence, we need to encode one logical bit with multiple physical bits for error detection and error correction by fast feedback control. Since decoherence of qubits exists at all times, the longer the feedback time, the greater the probability of error occurrence and the smaller the probability of correction, which requires the delay of the feedback control system to be as low as possible. Since the decoherence and time of the qubit are closely related, this requires that the regulation and reading of the quantum information be performed at a timing with an accuracy of the order of one picosecond. Since the number of physical encodings of logical bits is positively correlated with the success rate of error correction, this requires that the system have channels capable of reading and controlling multiple physical bits. In a standard PXIe chassis, a PXIe protocol is needed for data feedback, and as the PXIe protocol is asynchronous, the feedback has long delay and uncertain delay, and is difficult to be qualified for the task of quantum error correction. Typically PXIe chassis use a 10 mhz reference clock, a lower clock frequency can limit control time accuracy, resulting in poor synchronization of the individual control and read channels. The limited number of slots of a single PXIe chassis results in limited number of control and read channels, limiting the scalability of the system, and the use of a backplane trigger bus on the PXIe chassis panel may enable synchronization of multiple chassis, but the number of its synchronized chassis is limited by the electronic transmission distance of 100 nanoseconds.
Disclosure of Invention
The invention aims to provide a feedback control system and a feedback control method based on a PXIe chassis, so as to at least partially solve the problems.
In view of the above, the present invention provides a feedback control system and a feedback control method based on a PXIe chassis, where the feedback control system based on the PXIe chassis includes:
the main control machine box is a PXIe machine box;
the plurality of PXIe sub-chassis and the main control chassis are in one-stage cascade connection and/or multi-stage cascade connection;
the read control module is inserted into the PXIe slots of the main control chassis and each sub chassis;
the feedback control module is inserted into the timing slots of the main control chassis and each sub chassis;
and the fan-out module is arranged between the main control chassis and each sub chassis to realize the synchronization between the main control chassis and each sub chassis.
Furthermore, information communication is realized between the main control machine case and each sub machine case, and between the main control machine case and the read control modules and between the read control modules in each sub machine case through the feedback control modules.
Furthermore, the fan-out module provides a synchronizing signal to realize signal synchronization between the main control chassis and each sub chassis.
Still further, the main control chassis and each sub chassis are interconnected through a data cascade interface on the feedback control module, and the main control chassis and each sub chassis are interconnected with an external fan-out module through a synchronous interface on the feedback control module.
The data cascade interface and the synchronous interface are both arranged on a front panel of the feedback control module, wherein the data cascade interface comprises:
the reference clock interface realizes clock beat synchronization among the PXIe chassis;
the synchronous cascade interface realizes the time starting point synchronization among the PXIe machine boxes;
and the feedback cascade interface is used for realizing data communication among the PXIe machine boxes.
Based on the system, the feedback control method based on the PXIe chassis provided by the invention comprises the following steps:
the feedback control module of the main control chassis sends out a synchronous signal;
the fan-out system controls the synchronous signals to fan out to the feedback control modules of the main control chassis and each sub chassis, and further diffuses out to each reading control module in each chassis, so as to realize the system start synchronization;
the feedback control module obtains clock signals and transmits the clock signals to the feedback control module and the read control module in the main control cabinet and each sub cabinet to realize time sequence control, and the method further comprises the following steps:
when the system is in multi-cabinet cascade connection, clock signals are obtained from the outside, and the fan-out system controls the clock signals to fan out to a feedback control module and a reading control module of the main control cabinet and each sub cabinet; or (b)
When the system is a single machine box, the feedback control module in the machine box generates a clock signal and transmits the clock signal to the feedback control module and the reading control module of the machine box;
the method comprises the steps that data information is acquired by a main control chassis and/or a reading control module and a feedback control module in each sub chassis, and is converged to the feedback control module of the main control chassis for real-time calculation;
the calculation result is sent from the feedback control module of the main control chassis to the feedback control modules of other sub chassis through the data cascade interface, and then is forwarded to the main control chassis and the read control modules of all the sub chassis, so that the feedback transmission of data between the main control chassis and all the sub chassis is realized.
The feedback control system and the feedback control method based on the PXIe chassis have the following beneficial effects:
(1) The compact structure of the PXIe case is utilized to ensure that the transmission delay and the determined transmission time of a link are as little as possible, and the high-quality differential interface is utilized to transmit feedback data, so that the faster data transmission speed is ensured, the delay time from the control and reading module to the feedback control module is further reduced, and the feedback time determined in sub microsecond level can be realized;
(2) The high-frequency clock is provided through the timing slot, so that the phase noise of the reading and control channel is reduced, and the time control precision of the system is improved;
(3) The synchronous signals fanned by the fanning module and the feedback control module can uniformly control each module on the chassis to realize cooperative work, so that the system synchronization is realized in principle without the limitation of the chassis scale, and the expansibility of the system is improved;
(4) In addition, the feedback control panel reserves enough data cascading interfaces, and flexible expansion can be realized by programming the FPGA in the feedback control module.
Drawings
FIG. 1 is a schematic diagram of an internal star signal link of a PXIe chassis provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of a front panel of a feedback control module of a PXIe chassis provided by embodiments of the present invention;
fig. 3 is a schematic diagram of connection of a multi-chassis system according to an embodiment of the present invention.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
In order to achieve the purpose of high-precision and fast feedback control of multi-channel quantum information, a first embodiment of the present invention provides a feedback control system based on a PXIe chassis, referring to fig. 3, a basic framework of the system includes:
master chassis 0_1, which is a PXIe chassis and is used for outputting a synchronization signal;
a plurality of PXIe sub chassis, comprising: chassis 1_1, & gt, chassis 1_m are in primary cascade with the master chassis 0_1, chassis 2_1, chassis 2_2, & gt, chassis 2_N are in secondary cascade with the master chassis 0_1, & gt, and the like, so that data information is read and converged to the master chassis;
the reading control module is inserted into the common PXIe slots of the main control chassis and each sub chassis and is used for realizing signal acquisition and generation;
the feedback control module is inserted into the timing slots of the main control chassis and each sub chassis and is used for realizing the collection/fan-out of data and executing a feedback algorithm;
and the fan-out module is arranged between the main control chassis and each sub chassis to realize the synchronization between the main control chassis and each sub chassis.
As is apparent from fig. 3, in the feedback control system based on the PXIe chassis provided in this embodiment, the chassis 0_1 is used as a master chassis, the cascaded chassis 1_1, & gt, the chassis 1_m, and the like are used as first cascaded sub-chassis, and each chassis of the first cascaded sub-chassis is further cascaded with a second cascaded sub-chassis (the chassis 1_1 is cascaded with the chassis 2_1 and the chassis 2_2, & gt, the chassis 1_m is cascaded with the chassis 2_N, and the like). Similarly, each second cascade sub-chassis may also cascade a plurality of third cascade sub-chassis, and so on.
In some embodiments, information exchange is realized between the main control chassis and each sub chassis, and between the main control chassis and the read control modules inside each sub chassis through the feedback control modules.
In the embodiment of the invention, the main control chassis and each sub chassis are provided with feedback control modules and are arranged in timing slots of the main control chassis and each sub chassis.
In some embodiments, the fan-out module provides a synchronization signal to achieve signal synchronization between the main chassis and each sub chassis.
In some embodiments, the main control chassis and each sub chassis are interconnected through a data cascade interface on the feedback control module, and the main control chassis and each sub chassis are interconnected with an external fan-out module through a synchronous interface on the feedback control module.
Preferably, the data cascade interface and the synchronization interface are both disposed on a front panel of the feedback control module, where the data cascade interface includes:
the reference clock interface realizes clock beat synchronization among the PXIe chassis;
the synchronous cascade interface realizes the time starting point synchronization among the PXIe machine boxes;
and the feedback cascade interface is used for realizing data communication among the PXIe machine boxes.
Based on the above embodiments, the embodiment of the present invention designs the feedback control module for the timing slot of the PXIe chassis, and uses the 3 pairs of differential star-shaped fan-out interfaces and one single-ended star-shaped fan-out interface provided by the timing slot in the clock synchronization and the data feedback transmission of the system, and further description thereof is presented in detail in the following content, and will not be described herein.
In the feedback control system based on the PXIe chassis, for synchronization among the chassis, the embodiment of the invention additionally designs a fan-out module for fan-out synchronization signals and clock signals, and for feedback number transmission among the chassis, the embodiment of the invention designs a data cascade interface between the chassis and the chassis on a front panel of the feedback control module so as to realize better system expansibility.
The following is a second embodiment of the feedback control system according to the foregoing embodiment, and the feedback control method based on the PXIe chassis is further described with reference to fig. 3, where the method includes:
the feedback control module of the main control chassis sends out a synchronous signal;
in this embodiment, a chassis (i.e., chassis 0_1) controlling the synchronization cascade output signal is used as a master chassis, and outputs the synchronization signal through the synchronization cascade output interface.
The fan-out system controls the synchronous signals to fan out to the feedback control modules of the main control chassis and each sub chassis and further to be dispersed to each read control module in each chassis, so that the cooperative work between the main control chassis and each sub chassis and between the main control chassis and the feedback control modules and each access control module in each sub chassis is realized;
in this embodiment, the fan-out system receives the synchronization signal and controls the synchronization signal to be distributed to the main control chassis and each sub chassis through the synchronization cascade input interface at equal transmission distances, and the feedback control modules in the main control chassis and each sub chassis receive the synchronization signal through the synchronization cascade input interface and fan-out the synchronization signal to the read control module and the feedback control module of the chassis through the single-ended star-shaped fan-out interface, so as to realize the system start synchronization.
The feedback control module obtains a clock signal and transmits the clock signal to the feedback control module and the read control module in the main control chassis and each sub chassis to realize time sequence control, and in some embodiments, the steps include:
when the system is in multi-cabinet cascade connection, clock signals are obtained from the outside, and the fan-out system controls the clock signals to fan out to a feedback control module and a reading control module of the main control cabinet and each sub cabinet; or (b)
When the system is a single machine box, the feedback control module in the machine box generates a clock signal and transmits the clock signal to the feedback control module and the reading control module of the machine box;
in this embodiment, as apparent from fig. 3, the system is a multi-chassis cascade system, the clock signal is a reference clock acquired from the outside, the fan-out system controls the slave reference clock signal to be distributed to the main chassis and each sub chassis in equal transmission distances, the feedback control modules in the main chassis and each sub chassis receive the clock signal through the reference clock input interface, and then the clock signal is transmitted to the read control module and the feedback control module through the first group of differential star-shaped fan-out interfaces, or transmitted to other instruments through the reference clock output interface, so as to realize timing control.
In other embodiments, where the system is a stand-alone enclosure, the feedback control module itself generates the clock signal without synchronization between the enclosures.
The method comprises the steps that data information is acquired by a main control chassis and/or a reading control module and a feedback control module in each sub chassis, and is converged to the feedback control module of the main control chassis for real-time calculation;
the calculation result is sent from the feedback control module of the main control chassis to the feedback control modules of other sub chassis through the data cascade interface, and then forwarded to the main control chassis and the read control modules of all the sub chassis, so as to realize the feedback transmission of data between the main control chassis and all the sub chassis;
in this embodiment, referring to fig. 3 again, data transmission is implemented between the main control chassis and each sub chassis having a cascade relationship through feedback data fanout and feedback control fanout. The data information is gathered to the feedback control module through the second group of differential star fan-out interfaces, then is connected to the feedback control module of the main control chassis through a cascade connection port of the front panel of the feedback control module, is calculated and processed in real time by combining with the FPGA, and is fanned out to the feedback control module of each sub chassis through the feedback cascade input/output interface after being processed, and the calculation result in each feedback control module is forwarded to the corresponding main control chassis and the read control module in each sub chassis through the third group of differential star fan-out interfaces, so that the feedback transmission of different chassis is realized.
Based on the above embodiments, referring to fig. 1, assuming that the chassis is an 18-slot chassis, one timing slot is removed and one system slot is removed, the available common PXIe slots are 16 (PXIe module 1, PXIe module 2, PXIe module 3, PXIe module 4, PXIe module 5,..and PXIe module 16), the feedback control module is located in the timing slot of the PXIe chassis, the feedback control module and each common PXIe module can implement direct communication between data (read information, control command), signal (synchronization signal) and clock (high frequency clock), and the feedback control module can provide the read control module with a high frequency clock greater than 100 mhz to improve the quality of the clock.
Referring to fig. 2, the clock of the feedback control module may be generated by itself (may use the internal crystal as a reference or may use the external clock as a reference) or may be input from a reference clock, and the clock generated by the feedback control module may be used by other external instruments through a reference clock output interface. The output of the synchronous cascade is used for sending a synchronous signal to synchronize the whole system, the input of the synchronous cascade is used for receiving the synchronous signal, and the received synchronous signal is fanned out to the case feedback control module and the reading control module.
Specifically, a pair of differential star fan-out interfaces are used to transfer the high frequency clock signals required by the control and read channels to achieve high precision timing control. The pair of differential star fan-out interfaces are used as low-delay channels from the reading module to the feedback control module, the data obtained by the feedback control module is calculated to be a result in real time through the FPGA, and then the data is fan-out to the control module through the pair of differential star fan-out interfaces so as to realize low-delay feedback. The single ended star fan out signal acts as a synchronization signal for feedback control modules to each module in the PXIe chassis.
Further, the feedback cascade input/output signal can be used to send the read data of one chassis to another chassis, so that one chassis can acquire more quantum information, and after the final feedback processing module processes the information, the feedback control instruction is distributed to each chassis.
Furthermore, the complex data network structure can be realized through flexibly configuring the input/output interface of the feedback information so as to meet the continuous changing requirements.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the invention.

Claims (9)

1. A feedback control system based on a PXIe chassis, comprising:
the main control machine box is a PXIe machine box;
the plurality of PXIe sub-chassis and the main control chassis are in one-stage cascade connection and/or multi-stage cascade connection;
the read control module is inserted into the PXIe slots of the main control chassis and each sub chassis;
the feedback control module is inserted into the timing slots of the main control chassis and each sub chassis;
the fan-out module is arranged between the main control chassis and each sub chassis;
the main control chassis and each sub chassis are connected through a data cascade interface on a feedback control module, and the data cascade interface comprises:
the reference clock interface is used for realizing clock beat synchronization among the PXIe chassis;
the synchronous cascade interface realizes the time starting point synchronization among the PXIe chassis;
and a feedback cascade interface for realizing data communication between the PXIe chassis.
2. The PXIe chassis-based feedback control system of claim 1, wherein information communication is implemented between the master chassis and each of the sub chassis via a feedback control module.
3. The PXIe chassis-based feedback control system of claim 1, wherein information communication is implemented between the read control module and the read control module through the feedback control module inside the main control chassis and each of the sub chassis.
4. The PXIe chassis-based feedback control system of claim 1, wherein the fan-out module provides a synchronization signal to achieve signal synchronization between the master chassis and each of the sub chassis.
5. The PXIe chassis-based feedback control system of claim 1, wherein the master chassis and each of the sub chassis are interconnected with external fan-out modules via a synchronization interface on the feedback control module.
6. The PXIe chassis-based feedback control system of claim 5, wherein the data cascading interface and the synchronization interface are both disposed on a front panel of the feedback control module.
7. A feedback control method based on a PXIe chassis is characterized by comprising the following steps:
the feedback control module of the main control chassis sends out a synchronous signal;
the fan-out system controls the synchronous signals to fan out to the feedback control modules of the main control chassis and each sub chassis, and further fan out to each reading control module in each chassis, so as to realize the system start synchronization;
the feedback control module acquires clock signals and transmits the clock signals to the read control module and the feedback control module in the main control cabinet and the inside of each sub cabinet to realize time sequence control;
the method comprises the steps that data information is acquired by a main control chassis and/or a reading control module and a feedback control module in each sub chassis, and is converged to the feedback control module of the main control chassis for real-time calculation;
the calculation result is sent from the feedback control module of the main control chassis to the feedback control modules of other sub chassis through the data cascade interface, and then is forwarded to the main control chassis and the read control modules of all the sub chassis, so that the feedback transmission of data between the main control chassis and all the sub chassis is realized.
8. The feedback control method as claimed in claim 7, wherein when the system is a multi-chassis cascade, the obtaining the clock signal is obtaining the clock signal from the outside, and the fan-out system controls the fan-out of the clock signal to the read control module and the feedback control module of the main control chassis and each sub chassis.
9. The method as set forth in claim 7, wherein when the system is a single chassis, the obtaining clock signal is that the feedback control module in the chassis has generated the clock signal itself and transmitted to the read control module and the feedback control module of the chassis.
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CN111880603B (en) * 2020-07-27 2022-06-17 浪潮集团有限公司 Multi-chassis feedback result control trigger synchronization method, device, equipment and medium
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