CN110211944B - Semiconductor device and forming method - Google Patents
Semiconductor device and forming method Download PDFInfo
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- CN110211944B CN110211944B CN201810166065.1A CN201810166065A CN110211944B CN 110211944 B CN110211944 B CN 110211944B CN 201810166065 A CN201810166065 A CN 201810166065A CN 110211944 B CN110211944 B CN 110211944B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
Abstract
The present invention provides a semiconductor device, including: the semiconductor device comprises a semiconductor substrate layer, a silicon oxide layer on the semiconductor substrate layer, a germanium material layer between the semiconductor substrate layer and the silicon oxide layer, an adhesive layer on the germanium material layer, and a through hole metal layer on the adhesive layer. The invention can prevent the germanium material layer from suffering from H2O2Thereby improving the performance and reliability of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a metal interconnection technology of devices in a semiconductor.
Background
The germanium (Ge) process integrated in CMOS has a wide application potential in the fields of silicon-based optoelectronics, radio frequency, and the like, such as application in photodetectors, high-speed modulators, and the like.
The germanium (Ge) process integrated in CMOS requires the fabrication of VIAs (VIA or CT) over the germanium material for electrical connection to other devices. In order to ensure good electrical contact in the existing VIA process, the corresponding cladding layer at the VIA or CT needs to be opened through the opening to expose the germanium material layer. In this process, a cleaning process for removing impurities such as a photoresist layer is usually carried out with H2O2. Germanium material, although having excellent characteristics, is readily able to follow H2O2A chemical reaction is generated such that the exposed germanium material layer is exposed to H2O2Ultimately affecting the performance and reliability of the semiconductor device.
Therefore, a method for forming a through hole in a germanium material layer that is compatible with existing CMOS processes while ensuring conductivity and preventing damage to the germanium material layer is desired.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a semiconductor device, including: the semiconductor device comprises a semiconductor substrate layer, a silicon oxide layer on the semiconductor substrate layer, a germanium material layer between the semiconductor substrate layer and the silicon oxide layer, an adhesive layer on the germanium material layer, and a through hole metal layer on the adhesive layer.
The material of the adhesion layer of the semiconductor device according to an aspect of the present invention is TiN or tantalum nitride.
In a semiconductor device according to an aspect of the present invention, an upper surface of the via metal layer is flush with an upper surface of the silicon oxide layer.
A semiconductor device according to an aspect of the invention further comprises a metal suicide layer between the semiconductor substrate layer and the silicon oxide layer.
A semiconductor device according to an aspect of the present invention is characterized in that a via metal layer is also provided on the metal silicide layer, and an adhesive layer is also provided between the via metal layer and the metal silicide layer on the metal silicide layer.
The invention provides a method for forming a semiconductor device, which is characterized by comprising the following steps: growing a silicon oxide layer on the semiconductor substrate layer; etching the silicon oxide layer at the position where the germanium material layer needs to grow until the semiconductor substrate layer is exposed, and then forming the germanium material layer; forming an adhesion layer on the silicon oxide layer and the germanium material layer; growing a silicon oxide layer on the bonding layer; removing the redundant silicon oxide layer and the redundant bonding layer to flatten the surface; regrowing a silicon oxide layer; etching the position above the germanium material layer needing to be opened to form a through hole; forming a through hole metal layer on the surface of the semiconductor device; and flattening the surface of the semiconductor device.
The method of growing the silicon oxide layer in the method of forming the semiconductor device according to an aspect of the present invention is one of atomic layer deposition, physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition processes.
In the method of forming a semiconductor device according to an aspect of the present invention, the etching of the silicon oxide layer employs a plasma etching process.
In a method of forming a semiconductor device according to an aspect of the present invention, titanium nitride is used as a material of the adhesion layer.
In a method for forming a semiconductor device according to an aspect of the present invention, a material of the adhesion layer is tantalum metal.
In the method for forming a semiconductor device according to an aspect of the present invention, the thickness of the adhesive layer in the step of plating an adhesive layer on the surface of the semiconductor device reaches or exceeds 100A.
In a method of forming a semiconductor device according to an aspect of the invention, after removing the excess silicon oxide layer and the excess adhesion layer, the adhesion layer remains over the germanium material layer.
In a method of forming a semiconductor device according to an aspect of the present invention, after removing the excess silicon oxide layer and the excess adhesion layer, the remaining silicon oxide layer includes a silicon oxide layer above the original germanium material layer and a silicon oxide layer beside the germanium material layer below the original adhesion layer.
In the step of etching the position where the opening is required above the germanium material layer to form the through hole in the method for forming a semiconductor device according to one aspect of the present invention, the etching etches away all of the silicon oxide at the position of the through hole and a part of the adhesion layer.
In the method of forming a semiconductor device according to an aspect of the present invention, a material of the via metal layer is metal tungsten or metal copper.
In a method of forming a semiconductor device according to an aspect of the present invention, after planarizing a surface of the semiconductor device, an adhesive layer other than a via hole is removed.
The method for forming the semiconductor device according to the aspect of the invention further comprises the step of growing and forming the metal silicide layer on the semiconductor substrate layer.
The method for forming the semiconductor device according to the aspect of the invention further comprises etching to form a through hole at the position needing to be opened above the metal silicide layer.
The invention can prevent the germanium material layer from suffering from H2O2OfAnd is bad, thereby improving the performance and reliability of the semiconductor device.
Drawings
Fig. 1-10 illustrate steps of forming a semiconductor device according to the present invention.
Detailed Description
Embodiments of the present invention are specifically described below with reference to the drawings. Those skilled in the art will appreciate the features and advantages of the invention from the detailed description that follows. It should be noted that the structures, proportions, sizes, and the like shown in the drawings are only used in combination with the text of the specification for the understanding of the present invention by the reader, and are not intended to limit the conditions for implementing the present invention.
Any fine adjustment of structure, dimension, and ratio relationship can be implemented without affecting the function and the achieved purpose of the invention, and still fall within the scope of the invention.
As shown in fig. 1, an oxide layer 102 is first grown on a semiconductor substrate layer 101. The semiconductor substrate 101 may be silicon or silicon-on-insulator (SOI) of a single crystal, polycrystalline, or amorphous structure, or may further include other materials such as indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, or the like.
The method of growing the oxide layer 102 may be any conventional vacuum deposition technique such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD) process, one preferred method being an Atomic Layer Deposition (ALD) process. The material used for the oxide layer 102 may be silicon oxide (SiO2), silicon oxynitride (SiNO), or the like. Silicon oxide is used here as an example of a material used for the oxide layer 102.
Although the present invention is directed to a method for forming a via in a germanium material layer on a semiconductor substrate layer, in practical use, it is often necessary to form a contact directly on the substrate layer, i.e. a conventional via is also directly formed in a partial region on the semiconductor substrate layer. Therefore, in these regions, a metal Silicide layer (Silicide)103 can be grown and formed directly on the semiconductor substrate layer 101. As shown in fig. 1, a metal silicide layer 103 may be formed between the semiconductor substrate layer 101 and the silicon oxide layer 102.
One requirement for the silicon oxide layer 102 is that its thickness needs to be greater than the thickness of the subsequently grown germanium material layer. For example, if the thickness of the layer of germanium material to be grown is 2500A, the thickness of the silicon oxide layer 102 needs to be greater than 2500A, which may be 3200A, for example.
As shown in fig. 2, etching is then performed where it is desired to grow a layer of germanium material until the substrate layer 101 is exposed. The etching step here may be a plasma etching process or other common etching processes.
The layer of germanium material 104 is then formed by growing single crystal germanium by a selective growth process at the previously etched locations. If ion implantation of the germanium material layer 104 is desired, ion implantation is performed next.
The surface of the device is then coated with an adhesive layer 105. As shown in fig. 3, the adhesion layer 105 will cover the upper surface of the silicon oxide layer 102, the walls of the etching holes formed in the silicon oxide layer 102 by etching as shown in fig. 2, and the upper surface of the germanium material layer 104.
Here, the material of the adhesion layer 105 typically employs, for example, titanium nitride (TiN).
In the step shown in fig. 3, according to an aspect of the present invention, in addition to using TiN as the material of adhesion layer 305, a material such as tantalum nitride may be used. Such that adhesion layer 305 of tantalum nitride will cover the upper surface of silicon oxide layer 102, the walls of the etch holes formed in silicon oxide layer 102, and the upper surface of germanium material layer 104.
An etching process is required in the subsequent step of forming the via hole, and the adhesive layer 105 at the corresponding position in the step is required not to be completely etched away, and in order to ensure this, the adhesive layer 105 must have a certain thickness. As an example, the thickness of the adhesive layer 105 needs to reach or exceed 100A.
As shown in fig. 4, a silicon oxide layer 106 is grown on the surface of the device. The thickness of the silicon oxide layer 106 formed in this step needs to be at least greater than the "step height" of the adhesion layer 105 at the location of the grown germanium material layer 104. As can be seen from fig. 4, the "step height" herein refers to the size of the fluctuation of the adhesion layer 105 in height at the germanium material layer 104 due to the difference in height between the germanium material layer 104 and the silicon oxide layer 102. In other words, the silicon oxide layer 106 needs to cover the entire adhesion layer 105 thereunder. The silicon oxide layer 106 may be formed by, for example, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the like.
As shown in fig. 5, the excess silicon oxide layer and the excess adhesion layer 105 are then removed. The remaining adhesion layer in fig. 5 is above the layer of germanium material 104, while the remaining silicon oxide layer 107 comprises the silicon oxide layer 106 that was above the layer of germanium material 104 and the silicon oxide layer 102 below the adhesion layer 105 beside the layer of germanium material 104.
As shown in fig. 6, a layer of silicon oxide is then grown over the entire device. Thus, the total thickness of the silicon oxide layer 107 on the germanium material layer 104 is greater than the design height of its corresponding via, and the total thickness of the silicon oxide layer 107 on the metal silicide layer 103 is also greater than the design height of its corresponding via.
A metal suicide layer 103, a germanium material layer 104, and an adhesion layer 105 are included in the substrate layer 101 and the silicon oxide 107 layer.
As shown in fig. 7, next a via 110 is etched at the location where an opening is desired above the layer of germanium material 104, the etching step etches away the silicon oxide at the location of the via and a portion of the adhesion layer 105, but the adhesion layer 105 is not completely etched away because the thickness of the adhesion layer 105 is designed to be sufficiently resistant to the etching effect. In addition, the germanium material layer 104 below the adhesion layer 105 is not damaged because of the protection of the adhesion layer 105.
In addition, the via hole 111 is also formed by etching at a position where a conventional via hole needs to be formed, for example, at a position above the metal silicide layer 103 in fig. 7.
The step of forming the through hole by etching may specifically include, for example, the following steps:
first, a bottom anti-reflection layer (BARC) and a photoresist layer are spin-coated (spin on) on the surface of the silicon oxide layer, the photoresist is patterned by using a photolithography process such as exposure and development, and then the through holes 110 and 111 are formed by etching using a dry etching process, for example, a Reactive Ion Etching (RIE) process, with the patterned photoresist as a mask. In this embodiment, the etchant gas introduced into the reaction chamber is a mixed gas comprising SF6, CHF3, CF4, chlorine Cl2, oxygen O2, nitrogen N2, helium He, and other inert gases such as hydrogen Ar and neon Ne, the flow rate is 100-.
As shown in fig. 8, an adhesive layer is formed on the surface of the device. The entire adhesion layer 108 will thus cover all exposed surfaces of the silicon oxide layer 107, the original adhesion layer 105 (which was present only on the germanium material layer 104) and also the metal suicide layer 103.
If TiN, for example, is used as the material of the adhesion layer 105 in the step shown in fig. 3, TiN may be used as the material of the adhesion layer formed again here.
In the step shown in fig. 3, in addition to using TiN as the material of adhesion layer 105, a material such as tantalum nitride may be used according to an aspect of the present invention. If tantalum nitride is used as the initial adhesion layer material, according to one aspect of the present invention, an additional adhesion layer of tantalum nitride is formed on the surface of the device. Thus, the final tantalum nitride adhesion layer 108 will cover all exposed surfaces of the silicon oxide layer 107, the original adhesion layer, and the metal silicide layer 103.
As shown in fig. 9, a via metal layer 109 is formed on the upper surface of the device, i.e., the upper surface of the adhesive layer 108. The material of the via metal layer may be, for example, metal tungsten. The metal tungsten may be formed, for example, by forming a seed layer, then plating metal tungsten on the seed layer using a PVD (physical vapor deposition) process or a plating process, and annealing the metal tungsten. The material of the via metal layer may also be, for example, metallic copper.
As shown in fig. 10, a planarization process, such as chemical mechanical polishing, is performed on the surface of the device to remove the portion of the device above the design height, thereby forming the final semiconductor device including the via 109.
According to an aspect of the present invention, there is provided a semiconductor device as shown in fig. 10, comprising a semiconductor substrate layer 101, a silicon oxide layer 102 on the semiconductor substrate layer 101, a germanium material layer 104 between the semiconductor substrate layer 101 and the silicon oxide layer 102, an adhesion layer 108 on the germanium material layer 104, and a via metal layer 109 on the adhesion layer 108. The upper surface of the via metal layer 109 is flush with the upper surface of the silicon oxide layer 102.
The semiconductor device according to an aspect of the present invention further includes a metal silicon layer 103 between the semiconductor substrate layer 101 and the silicon oxide layer 102, an adhesive layer 108 on the metal silicon layer 103, and a via metal layer 109 on the adhesive layer 108. The upper surface of the via metal layer 109 is flush with the upper surface of the silicon oxide layer 102.
Although the present invention has been fully disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A semiconductor device, comprising:
a semiconductor substrate layer,
a silicon oxide layer on the semiconductor substrate layer,
a layer of germanium material between the semiconductor substrate layer and the silicon oxide layer,
an adhesion layer on the germanium material layer,
and a via metal layer on the adhesion layer;
wherein the material of the adhesion layer is titanium nitride or tantalum nitride.
2. The semiconductor device of claim 1, wherein an upper surface of the via metal layer is flush with an upper surface of the silicon oxide layer.
3. The semiconductor device of claim 1, further comprising a metal silicide layer between the semiconductor substrate layer and the silicon oxide layer.
4. The semiconductor device according to claim 3, wherein a via metal layer is also provided on the metal silicide layer, and an adhesive layer is also provided between the via metal layer and the metal silicide layer on the metal silicide layer.
5. A method of forming a semiconductor device, comprising:
growing a silicon oxide layer on the semiconductor substrate layer;
etching the silicon oxide layer at the position where the germanium material layer needs to grow until the semiconductor substrate layer is exposed, and then forming the germanium material layer;
forming an adhesion layer on the silicon oxide layer and the germanium material layer;
growing a silicon oxide layer on the bonding layer;
removing the redundant silicon oxide layer and the redundant bonding layer to flatten the surface;
regrowing a silicon oxide layer;
etching the position above the germanium material layer needing to be opened to form a through hole;
forming a through hole metal layer on the surface of the semiconductor device;
and flattening the surface of the semiconductor device.
6. The method of forming a semiconductor device according to claim 5, wherein the silicon oxide layer is grown by one of atomic layer deposition, physical vapor deposition, chemical vapor deposition, and plasma enhanced chemical vapor deposition.
7. The method of forming a semiconductor device according to claim 5, wherein etching the silicon oxide layer uses a plasma etching process.
8. The method for forming a semiconductor device according to claim 5, wherein a material of the adhesion layer is titanium nitride.
9. The method for forming a semiconductor device according to claim 5, wherein a material of the adhesion layer is tantalum nitride.
10. The method for forming a semiconductor device according to claim 5, wherein a thickness of the adhesive layer reaches or exceeds 100A in the step of plating an adhesive layer on the surface of the semiconductor device.
11. The method of forming a semiconductor device of claim 5, wherein after removing the excess silicon oxide layer and the excess adhesion layer, the adhesion layer remains over the germanium material layer.
12. The method of forming a semiconductor device of claim 5, wherein after removing the excess silicon oxide layer and the excess adhesion layer, the remaining silicon oxide layer comprises a silicon oxide layer above the original germanium material layer and a silicon oxide layer next to the germanium material layer and below the adhesion layer.
13. The method for forming a semiconductor device according to claim 5, wherein in the step of etching to form a via hole at a position where an opening is required above the germanium material layer, the etching etches away all of the silicon oxide at the position of the via hole and a part of the adhesion layer.
14. The method for forming a semiconductor device according to claim 5, wherein a material of the via metal layer is metal tungsten or metal copper.
15. The method for forming a semiconductor device according to claim 5, wherein after the surface of the semiconductor device is planarized, the adhesive layer other than the via hole is removed.
16. A method of forming a semiconductor device according to claim 5, further comprising the step of growing a metal silicide layer on the semiconductor substrate layer.
17. The method of forming a semiconductor device according to claim 16, further comprising etching to form a via at a location over the metal silicide layer where an opening is desired.
18. The method of forming a semiconductor device according to claim 5, wherein the step of forming a via metal layer on the surface of the semiconductor device further comprises forming a new adhesion layer first and then forming the via metal layer on the new adhesion layer.
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| KR20030037179A (en) * | 2001-11-02 | 2003-05-12 | 아남반도체 주식회사 | Method for manufacturing semiconductor devices |
| CN106486506A (en) * | 2015-08-27 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Deep trench isolation structure and forming method thereof |
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| CN100561712C (en) * | 2006-12-04 | 2009-11-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
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| CN106486506A (en) * | 2015-08-27 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Deep trench isolation structure and forming method thereof |
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